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26#include "hw/sysbus.h"
27#include "hw/hw.h"
28#include "net/net.h"
29#include "hw/block/flash.h"
30#include "sysemu/sysemu.h"
31#include "hw/devices.h"
32#include "hw/boards.h"
33#include "sysemu/block-backend.h"
34#include "exec/address-spaces.h"
35
36#include "boot.h"
37
38#define LMB_BRAM_SIZE (128 * 1024)
39#define FLASH_SIZE (16 * 1024 * 1024)
40
41#define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb"
42
43#define MEMORY_BASEADDR 0x90000000
44#define FLASH_BASEADDR 0xa0000000
45#define INTC_BASEADDR 0x81800000
46#define TIMER_BASEADDR 0x83c00000
47#define UARTLITE_BASEADDR 0x84000000
48#define ETHLITE_BASEADDR 0x81000000
49
50#define TIMER_IRQ 0
51#define ETHLITE_IRQ 1
52#define UARTLITE_IRQ 3
53
54static void
55petalogix_s3adsp1800_init(MachineState *machine)
56{
57 ram_addr_t ram_size = machine->ram_size;
58 DeviceState *dev;
59 MicroBlazeCPU *cpu;
60 DriveInfo *dinfo;
61 int i;
62 hwaddr ddr_base = MEMORY_BASEADDR;
63 MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
64 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
65 qemu_irq irq[32];
66 MemoryRegion *sysmem = get_system_memory();
67
68 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
69 object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
70
71
72 memory_region_init_ram(phys_lmb_bram, NULL,
73 "petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE,
74 &error_fatal);
75 vmstate_register_ram_global(phys_lmb_bram);
76 memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);
77
78 memory_region_init_ram(phys_ram, NULL, "petalogix_s3adsp1800.ram",
79 ram_size, &error_fatal);
80 vmstate_register_ram_global(phys_ram);
81 memory_region_add_subregion(sysmem, ddr_base, phys_ram);
82
83 dinfo = drive_get(IF_PFLASH, 0, 0);
84 pflash_cfi01_register(FLASH_BASEADDR,
85 NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,
86 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
87 (64 * 1024), FLASH_SIZE >> 16,
88 1, 0x89, 0x18, 0x0000, 0x0, 1);
89
90 dev = qdev_create(NULL, "xlnx.xps-intc");
91 qdev_prop_set_uint32(dev, "kind-of-intr",
92 1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
93 qdev_init_nofail(dev);
94 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
95 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
96 qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
97 for (i = 0; i < 32; i++) {
98 irq[i] = qdev_get_gpio_in(dev, i);
99 }
100
101 sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR,
102 irq[UARTLITE_IRQ]);
103
104
105 dev = qdev_create(NULL, "xlnx.xps-timer");
106 qdev_prop_set_uint32(dev, "one-timer-only", 0);
107 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
108 qdev_init_nofail(dev);
109 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
110 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
111
112 qemu_check_nic_model(&nd_table[0], "xlnx.xps-ethernetlite");
113 dev = qdev_create(NULL, "xlnx.xps-ethernetlite");
114 qdev_set_nic_properties(dev, &nd_table[0]);
115 qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
116 qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
117 qdev_init_nofail(dev);
118 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
119 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
120
121 microblaze_load_kernel(cpu, ddr_base, ram_size,
122 machine->initrd_filename,
123 BINARY_DEVICE_TREE_FILE,
124 NULL);
125}
126
127static void petalogix_s3adsp1800_machine_init(MachineClass *mc)
128{
129 mc->desc = "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800";
130 mc->init = petalogix_s3adsp1800_init;
131 mc->is_default = 1;
132}
133
134DEFINE_MACHINE("petalogix-s3adsp1800", petalogix_s3adsp1800_machine_init)
135