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24#include "hw/hw.h"
25#include "hw/pci/pci.h"
26#include "net/net.h"
27#include "ne2000.h"
28#include "hw/loader.h"
29#include "sysemu/sysemu.h"
30
31
32
33
34#define MAX_ETH_FRAME_SIZE 1514
35
36#define E8390_CMD 0x00
37
38#define EN0_CLDALO 0x01
39#define EN0_STARTPG 0x01
40#define EN0_CLDAHI 0x02
41#define EN0_STOPPG 0x02
42#define EN0_BOUNDARY 0x03
43#define EN0_TSR 0x04
44#define EN0_TPSR 0x04
45#define EN0_NCR 0x05
46#define EN0_TCNTLO 0x05
47#define EN0_FIFO 0x06
48#define EN0_TCNTHI 0x06
49#define EN0_ISR 0x07
50#define EN0_CRDALO 0x08
51#define EN0_RSARLO 0x08
52#define EN0_CRDAHI 0x09
53#define EN0_RSARHI 0x09
54#define EN0_RCNTLO 0x0a
55#define EN0_RTL8029ID0 0x0a
56#define EN0_RCNTHI 0x0b
57#define EN0_RTL8029ID1 0x0b
58#define EN0_RSR 0x0c
59#define EN0_RXCR 0x0c
60#define EN0_TXCR 0x0d
61#define EN0_COUNTER0 0x0d
62#define EN0_DCFG 0x0e
63#define EN0_COUNTER1 0x0e
64#define EN0_IMR 0x0f
65#define EN0_COUNTER2 0x0f
66
67#define EN1_PHYS 0x11
68#define EN1_CURPAG 0x17
69#define EN1_MULT 0x18
70
71#define EN2_STARTPG 0x21
72#define EN2_STOPPG 0x22
73
74#define EN3_CONFIG0 0x33
75#define EN3_CONFIG1 0x34
76#define EN3_CONFIG2 0x35
77#define EN3_CONFIG3 0x36
78
79
80#define E8390_STOP 0x01
81#define E8390_START 0x02
82#define E8390_TRANS 0x04
83#define E8390_RREAD 0x08
84#define E8390_RWRITE 0x10
85#define E8390_NODMA 0x20
86#define E8390_PAGE0 0x00
87#define E8390_PAGE1 0x40
88#define E8390_PAGE2 0x80
89
90
91#define ENISR_RX 0x01
92#define ENISR_TX 0x02
93#define ENISR_RX_ERR 0x04
94#define ENISR_TX_ERR 0x08
95#define ENISR_OVER 0x10
96#define ENISR_COUNTERS 0x20
97#define ENISR_RDC 0x40
98#define ENISR_RESET 0x80
99#define ENISR_ALL 0x3f
100
101
102#define ENRSR_RXOK 0x01
103#define ENRSR_CRC 0x02
104#define ENRSR_FAE 0x04
105#define ENRSR_FO 0x08
106#define ENRSR_MPA 0x10
107#define ENRSR_PHY 0x20
108#define ENRSR_DIS 0x40
109#define ENRSR_DEF 0x80
110
111
112#define ENTSR_PTX 0x01
113#define ENTSR_ND 0x02
114#define ENTSR_COL 0x04
115#define ENTSR_ABT 0x08
116#define ENTSR_CRS 0x10
117#define ENTSR_FU 0x20
118#define ENTSR_CDH 0x40
119#define ENTSR_OWC 0x80
120
121typedef struct PCINE2000State {
122 PCIDevice dev;
123 NE2000State ne2000;
124} PCINE2000State;
125
126void ne2000_reset(NE2000State *s)
127{
128 int i;
129
130 s->isr = ENISR_RESET;
131 memcpy(s->mem, &s->c.macaddr, 6);
132 s->mem[14] = 0x57;
133 s->mem[15] = 0x57;
134
135
136 for(i = 15;i >= 0; i--) {
137 s->mem[2 * i] = s->mem[i];
138 s->mem[2 * i + 1] = s->mem[i];
139 }
140}
141
142static void ne2000_update_irq(NE2000State *s)
143{
144 int isr;
145 isr = (s->isr & s->imr) & 0x7f;
146#if defined(DEBUG_NE2000)
147 printf("NE2000: Set IRQ to %d (%02x %02x)\n",
148 isr ? 1 : 0, s->isr, s->imr);
149#endif
150 qemu_set_irq(s->irq, (isr != 0));
151}
152
153static int ne2000_buffer_full(NE2000State *s)
154{
155 int avail, index, boundary;
156
157 if (s->stop <= s->start) {
158 return 1;
159 }
160
161 index = s->curpag << 8;
162 boundary = s->boundary << 8;
163 if (index < boundary)
164 avail = boundary - index;
165 else
166 avail = (s->stop - s->start) - (index - boundary);
167 if (avail < (MAX_ETH_FRAME_SIZE + 4))
168 return 1;
169 return 0;
170}
171
172#define MIN_BUF_SIZE 60
173
174ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
175{
176 NE2000State *s = qemu_get_nic_opaque(nc);
177 int size = size_;
178 uint8_t *p;
179 unsigned int total_len, next, avail, len, index, mcast_idx;
180 uint8_t buf1[60];
181 static const uint8_t broadcast_macaddr[6] =
182 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
183
184#if defined(DEBUG_NE2000)
185 printf("NE2000: received len=%d\n", size);
186#endif
187
188 if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
189 return -1;
190
191
192 if (s->rxcr & 0x10) {
193
194 } else {
195 if (!memcmp(buf, broadcast_macaddr, 6)) {
196
197 if (!(s->rxcr & 0x04))
198 return size;
199 } else if (buf[0] & 0x01) {
200
201 if (!(s->rxcr & 0x08))
202 return size;
203 mcast_idx = compute_mcast_idx(buf);
204 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
205 return size;
206 } else if (s->mem[0] == buf[0] &&
207 s->mem[2] == buf[1] &&
208 s->mem[4] == buf[2] &&
209 s->mem[6] == buf[3] &&
210 s->mem[8] == buf[4] &&
211 s->mem[10] == buf[5]) {
212
213 } else {
214 return size;
215 }
216 }
217
218
219
220 if (size < MIN_BUF_SIZE) {
221 memcpy(buf1, buf, size);
222 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
223 buf = buf1;
224 size = MIN_BUF_SIZE;
225 }
226
227 index = s->curpag << 8;
228 if (index >= NE2000_PMEM_END) {
229 index = s->start;
230 }
231
232 total_len = size + 4;
233
234 next = index + ((total_len + 4 + 255) & ~0xff);
235 if (next >= s->stop)
236 next -= (s->stop - s->start);
237
238 p = s->mem + index;
239 s->rsr = ENRSR_RXOK;
240
241 if (buf[0] & 0x01)
242 s->rsr |= ENRSR_PHY;
243 p[0] = s->rsr;
244 p[1] = next >> 8;
245 p[2] = total_len;
246 p[3] = total_len >> 8;
247 index += 4;
248
249
250 while (size > 0) {
251 if (index <= s->stop)
252 avail = s->stop - index;
253 else
254 break;
255 len = size;
256 if (len > avail)
257 len = avail;
258 memcpy(s->mem + index, buf, len);
259 buf += len;
260 index += len;
261 if (index == s->stop)
262 index = s->start;
263 size -= len;
264 }
265 s->curpag = next >> 8;
266
267
268 s->isr |= ENISR_RX;
269 ne2000_update_irq(s);
270
271 return size_;
272}
273
274static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
275{
276 NE2000State *s = opaque;
277 int offset, page, index;
278
279 addr &= 0xf;
280#ifdef DEBUG_NE2000
281 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
282#endif
283 if (addr == E8390_CMD) {
284
285 s->cmd = val;
286 if (!(val & E8390_STOP)) {
287 s->isr &= ~ENISR_RESET;
288
289 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
290 s->rcnt == 0) {
291 s->isr |= ENISR_RDC;
292 ne2000_update_irq(s);
293 }
294 if (val & E8390_TRANS) {
295 index = (s->tpsr << 8);
296
297 if (index >= NE2000_PMEM_END)
298 index -= NE2000_PMEM_SIZE;
299
300 if (index + s->tcnt <= NE2000_PMEM_END) {
301 qemu_send_packet(qemu_get_queue(s->nic), s->mem + index,
302 s->tcnt);
303 }
304
305 s->tsr = ENTSR_PTX;
306 s->isr |= ENISR_TX;
307 s->cmd &= ~E8390_TRANS;
308 ne2000_update_irq(s);
309 }
310 }
311 } else {
312 page = s->cmd >> 6;
313 offset = addr | (page << 4);
314 switch(offset) {
315 case EN0_STARTPG:
316 if (val << 8 <= NE2000_PMEM_END) {
317 s->start = val << 8;
318 }
319 break;
320 case EN0_STOPPG:
321 if (val << 8 <= NE2000_PMEM_END) {
322 s->stop = val << 8;
323 }
324 break;
325 case EN0_BOUNDARY:
326 if (val << 8 < NE2000_PMEM_END) {
327 s->boundary = val;
328 }
329 break;
330 case EN0_IMR:
331 s->imr = val;
332 ne2000_update_irq(s);
333 break;
334 case EN0_TPSR:
335 s->tpsr = val;
336 break;
337 case EN0_TCNTLO:
338 s->tcnt = (s->tcnt & 0xff00) | val;
339 break;
340 case EN0_TCNTHI:
341 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
342 break;
343 case EN0_RSARLO:
344 s->rsar = (s->rsar & 0xff00) | val;
345 break;
346 case EN0_RSARHI:
347 s->rsar = (s->rsar & 0x00ff) | (val << 8);
348 break;
349 case EN0_RCNTLO:
350 s->rcnt = (s->rcnt & 0xff00) | val;
351 break;
352 case EN0_RCNTHI:
353 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
354 break;
355 case EN0_RXCR:
356 s->rxcr = val;
357 break;
358 case EN0_DCFG:
359 s->dcfg = val;
360 break;
361 case EN0_ISR:
362 s->isr &= ~(val & 0x7f);
363 ne2000_update_irq(s);
364 break;
365 case EN1_PHYS ... EN1_PHYS + 5:
366 s->phys[offset - EN1_PHYS] = val;
367 break;
368 case EN1_CURPAG:
369 if (val << 8 < NE2000_PMEM_END) {
370 s->curpag = val;
371 }
372 break;
373 case EN1_MULT ... EN1_MULT + 7:
374 s->mult[offset - EN1_MULT] = val;
375 break;
376 }
377 }
378}
379
380static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
381{
382 NE2000State *s = opaque;
383 int offset, page, ret;
384
385 addr &= 0xf;
386 if (addr == E8390_CMD) {
387 ret = s->cmd;
388 } else {
389 page = s->cmd >> 6;
390 offset = addr | (page << 4);
391 switch(offset) {
392 case EN0_TSR:
393 ret = s->tsr;
394 break;
395 case EN0_BOUNDARY:
396 ret = s->boundary;
397 break;
398 case EN0_ISR:
399 ret = s->isr;
400 break;
401 case EN0_RSARLO:
402 ret = s->rsar & 0x00ff;
403 break;
404 case EN0_RSARHI:
405 ret = s->rsar >> 8;
406 break;
407 case EN1_PHYS ... EN1_PHYS + 5:
408 ret = s->phys[offset - EN1_PHYS];
409 break;
410 case EN1_CURPAG:
411 ret = s->curpag;
412 break;
413 case EN1_MULT ... EN1_MULT + 7:
414 ret = s->mult[offset - EN1_MULT];
415 break;
416 case EN0_RSR:
417 ret = s->rsr;
418 break;
419 case EN2_STARTPG:
420 ret = s->start >> 8;
421 break;
422 case EN2_STOPPG:
423 ret = s->stop >> 8;
424 break;
425 case EN0_RTL8029ID0:
426 ret = 0x50;
427 break;
428 case EN0_RTL8029ID1:
429 ret = 0x43;
430 break;
431 case EN3_CONFIG0:
432 ret = 0;
433 break;
434 case EN3_CONFIG2:
435 ret = 0x40;
436 break;
437 case EN3_CONFIG3:
438 ret = 0x40;
439 break;
440 default:
441 ret = 0x00;
442 break;
443 }
444 }
445#ifdef DEBUG_NE2000
446 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
447#endif
448 return ret;
449}
450
451static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
452 uint32_t val)
453{
454 if (addr < 32 ||
455 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
456 s->mem[addr] = val;
457 }
458}
459
460static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
461 uint32_t val)
462{
463 addr &= ~1;
464 if (addr < 32 ||
465 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
466 *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
467 }
468}
469
470static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
471 uint32_t val)
472{
473 addr &= ~1;
474 if (addr < 32
475 || (addr >= NE2000_PMEM_START
476 && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
477 stl_le_p(s->mem + addr, val);
478 }
479}
480
481static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
482{
483 if (addr < 32 ||
484 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
485 return s->mem[addr];
486 } else {
487 return 0xff;
488 }
489}
490
491static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
492{
493 addr &= ~1;
494 if (addr < 32 ||
495 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
496 return le16_to_cpu(*(uint16_t *)(s->mem + addr));
497 } else {
498 return 0xffff;
499 }
500}
501
502static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
503{
504 addr &= ~1;
505 if (addr < 32
506 || (addr >= NE2000_PMEM_START
507 && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
508 return ldl_le_p(s->mem + addr);
509 } else {
510 return 0xffffffff;
511 }
512}
513
514static inline void ne2000_dma_update(NE2000State *s, int len)
515{
516 s->rsar += len;
517
518
519 if (s->rsar == s->stop)
520 s->rsar = s->start;
521
522 if (s->rcnt <= len) {
523 s->rcnt = 0;
524
525 s->isr |= ENISR_RDC;
526 ne2000_update_irq(s);
527 } else {
528 s->rcnt -= len;
529 }
530}
531
532static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
533{
534 NE2000State *s = opaque;
535
536#ifdef DEBUG_NE2000
537 printf("NE2000: asic write val=0x%04x\n", val);
538#endif
539 if (s->rcnt == 0)
540 return;
541 if (s->dcfg & 0x01) {
542
543 ne2000_mem_writew(s, s->rsar, val);
544 ne2000_dma_update(s, 2);
545 } else {
546
547 ne2000_mem_writeb(s, s->rsar, val);
548 ne2000_dma_update(s, 1);
549 }
550}
551
552static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
553{
554 NE2000State *s = opaque;
555 int ret;
556
557 if (s->dcfg & 0x01) {
558
559 ret = ne2000_mem_readw(s, s->rsar);
560 ne2000_dma_update(s, 2);
561 } else {
562
563 ret = ne2000_mem_readb(s, s->rsar);
564 ne2000_dma_update(s, 1);
565 }
566#ifdef DEBUG_NE2000
567 printf("NE2000: asic read val=0x%04x\n", ret);
568#endif
569 return ret;
570}
571
572static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
573{
574 NE2000State *s = opaque;
575
576#ifdef DEBUG_NE2000
577 printf("NE2000: asic writel val=0x%04x\n", val);
578#endif
579 if (s->rcnt == 0)
580 return;
581
582 ne2000_mem_writel(s, s->rsar, val);
583 ne2000_dma_update(s, 4);
584}
585
586static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
587{
588 NE2000State *s = opaque;
589 int ret;
590
591
592 ret = ne2000_mem_readl(s, s->rsar);
593 ne2000_dma_update(s, 4);
594#ifdef DEBUG_NE2000
595 printf("NE2000: asic readl val=0x%04x\n", ret);
596#endif
597 return ret;
598}
599
600static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
601{
602
603}
604
605static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
606{
607 NE2000State *s = opaque;
608 ne2000_reset(s);
609 return 0;
610}
611
612static int ne2000_post_load(void* opaque, int version_id)
613{
614 NE2000State* s = opaque;
615
616 if (version_id < 2) {
617 s->rxcr = 0x0c;
618 }
619 return 0;
620}
621
622const VMStateDescription vmstate_ne2000 = {
623 .name = "ne2000",
624 .version_id = 2,
625 .minimum_version_id = 0,
626 .post_load = ne2000_post_load,
627 .fields = (VMStateField[]) {
628 VMSTATE_UINT8_V(rxcr, NE2000State, 2),
629 VMSTATE_UINT8(cmd, NE2000State),
630 VMSTATE_UINT32(start, NE2000State),
631 VMSTATE_UINT32(stop, NE2000State),
632 VMSTATE_UINT8(boundary, NE2000State),
633 VMSTATE_UINT8(tsr, NE2000State),
634 VMSTATE_UINT8(tpsr, NE2000State),
635 VMSTATE_UINT16(tcnt, NE2000State),
636 VMSTATE_UINT16(rcnt, NE2000State),
637 VMSTATE_UINT32(rsar, NE2000State),
638 VMSTATE_UINT8(rsr, NE2000State),
639 VMSTATE_UINT8(isr, NE2000State),
640 VMSTATE_UINT8(dcfg, NE2000State),
641 VMSTATE_UINT8(imr, NE2000State),
642 VMSTATE_BUFFER(phys, NE2000State),
643 VMSTATE_UINT8(curpag, NE2000State),
644 VMSTATE_BUFFER(mult, NE2000State),
645 VMSTATE_UNUSED(4),
646 VMSTATE_BUFFER(mem, NE2000State),
647 VMSTATE_END_OF_LIST()
648 }
649};
650
651static const VMStateDescription vmstate_pci_ne2000 = {
652 .name = "ne2000",
653 .version_id = 3,
654 .minimum_version_id = 3,
655 .fields = (VMStateField[]) {
656 VMSTATE_PCI_DEVICE(dev, PCINE2000State),
657 VMSTATE_STRUCT(ne2000, PCINE2000State, 0, vmstate_ne2000, NE2000State),
658 VMSTATE_END_OF_LIST()
659 }
660};
661
662static uint64_t ne2000_read(void *opaque, hwaddr addr,
663 unsigned size)
664{
665 NE2000State *s = opaque;
666
667 if (addr < 0x10 && size == 1) {
668 return ne2000_ioport_read(s, addr);
669 } else if (addr == 0x10) {
670 if (size <= 2) {
671 return ne2000_asic_ioport_read(s, addr);
672 } else {
673 return ne2000_asic_ioport_readl(s, addr);
674 }
675 } else if (addr == 0x1f && size == 1) {
676 return ne2000_reset_ioport_read(s, addr);
677 }
678 return ((uint64_t)1 << (size * 8)) - 1;
679}
680
681static void ne2000_write(void *opaque, hwaddr addr,
682 uint64_t data, unsigned size)
683{
684 NE2000State *s = opaque;
685
686 if (addr < 0x10 && size == 1) {
687 ne2000_ioport_write(s, addr, data);
688 } else if (addr == 0x10) {
689 if (size <= 2) {
690 ne2000_asic_ioport_write(s, addr, data);
691 } else {
692 ne2000_asic_ioport_writel(s, addr, data);
693 }
694 } else if (addr == 0x1f && size == 1) {
695 ne2000_reset_ioport_write(s, addr, data);
696 }
697}
698
699static const MemoryRegionOps ne2000_ops = {
700 .read = ne2000_read,
701 .write = ne2000_write,
702 .endianness = DEVICE_LITTLE_ENDIAN,
703};
704
705
706
707
708void ne2000_setup_io(NE2000State *s, DeviceState *dev, unsigned size)
709{
710 memory_region_init_io(&s->io, OBJECT(dev), &ne2000_ops, s, "ne2000", size);
711}
712
713static NetClientInfo net_ne2000_info = {
714 .type = NET_CLIENT_OPTIONS_KIND_NIC,
715 .size = sizeof(NICState),
716 .receive = ne2000_receive,
717};
718
719static void pci_ne2000_realize(PCIDevice *pci_dev, Error **errp)
720{
721 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
722 NE2000State *s;
723 uint8_t *pci_conf;
724
725 pci_conf = d->dev.config;
726 pci_conf[PCI_INTERRUPT_PIN] = 1;
727
728 s = &d->ne2000;
729 ne2000_setup_io(s, DEVICE(pci_dev), 0x100);
730 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
731 s->irq = pci_allocate_irq(&d->dev);
732
733 qemu_macaddr_default_if_unset(&s->c.macaddr);
734 ne2000_reset(s);
735
736 s->nic = qemu_new_nic(&net_ne2000_info, &s->c,
737 object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
738 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->c.macaddr.a);
739}
740
741static void pci_ne2000_exit(PCIDevice *pci_dev)
742{
743 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
744 NE2000State *s = &d->ne2000;
745
746 qemu_del_nic(s->nic);
747 qemu_free_irq(s->irq);
748}
749
750static void ne2000_instance_init(Object *obj)
751{
752 PCIDevice *pci_dev = PCI_DEVICE(obj);
753 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
754 NE2000State *s = &d->ne2000;
755
756 device_add_bootindex_property(obj, &s->c.bootindex,
757 "bootindex", "/ethernet-phy@0",
758 &pci_dev->qdev, NULL);
759}
760
761static Property ne2000_properties[] = {
762 DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c),
763 DEFINE_PROP_END_OF_LIST(),
764};
765
766static void ne2000_class_init(ObjectClass *klass, void *data)
767{
768 DeviceClass *dc = DEVICE_CLASS(klass);
769 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
770
771 k->realize = pci_ne2000_realize;
772 k->exit = pci_ne2000_exit;
773 k->romfile = "efi-ne2k_pci.rom",
774 k->vendor_id = PCI_VENDOR_ID_REALTEK;
775 k->device_id = PCI_DEVICE_ID_REALTEK_8029;
776 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
777 dc->vmsd = &vmstate_pci_ne2000;
778 dc->props = ne2000_properties;
779 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
780}
781
782static const TypeInfo ne2000_info = {
783 .name = "ne2k_pci",
784 .parent = TYPE_PCI_DEVICE,
785 .instance_size = sizeof(PCINE2000State),
786 .class_init = ne2000_class_init,
787 .instance_init = ne2000_instance_init,
788};
789
790static void ne2000_register_types(void)
791{
792 type_register_static(&ne2000_info);
793}
794
795type_init(ne2000_register_types)
796