LXR qemu/hw/pci/pcie

   1/*
   2 * pcie_port.c
   3 *
   4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5 *                    VA Linux Systems Japan K.K.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along
  18 * with this program; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "hw/pci/pcie_port.h"
  22#include "hw/hotplug.h"
  23
  24void pcie_port_init_reg(PCIDevice *d)
  25{
  26    /* Unlike pci bridge,
  27       66MHz and fast back to back don't apply to pci express port. */
  28    pci_set_word(d->config + PCI_STATUS, 0);
  29    pci_set_word(d->config + PCI_SEC_STATUS, 0);
  30
  31    /*
  32     * Unlike conventional pci bridge, for some bits the spec states:
  33     * Does not apply to PCI Express and must be hardwired to 0.
  34     */
  35    pci_word_test_and_clear_mask(d->wmask + PCI_BRIDGE_CONTROL,
  36                                 PCI_BRIDGE_CTL_MASTER_ABORT |
  37                                 PCI_BRIDGE_CTL_FAST_BACK |
  38                                 PCI_BRIDGE_CTL_DISCARD |
  39                                 PCI_BRIDGE_CTL_SEC_DISCARD |
  40                                 PCI_BRIDGE_CTL_DISCARD_STATUS |
  41                                 PCI_BRIDGE_CTL_DISCARD_SERR);
  42}
  43
  44/**************************************************************************
  45 * (chassis number, pcie physical slot number) -> pcie slot conversion
  46 */
  47struct PCIEChassis {
  48    uint8_t     number;
  49
  50    QLIST_HEAD(, PCIESlot) slots;
  51    QLIST_ENTRY(PCIEChassis) next;
  52};
  53
  54static QLIST_HEAD(, PCIEChassis) chassis = QLIST_HEAD_INITIALIZER(chassis);
  55
  56static struct PCIEChassis *pcie_chassis_find(uint8_t chassis_number)
  57{
  58    struct PCIEChassis *c;
  59    QLIST_FOREACH(c, &chassis, next) {
  60        if (c->number == chassis_number) {
  61            break;
  62        }
  63    }
  64    return c;
  65}
  66
  67void pcie_chassis_create(uint8_t chassis_number)
  68{
  69    struct PCIEChassis *c;
  70    c = pcie_chassis_find(chassis_number);
  71    if (c) {
  72        return;
  73    }
  74    c = g_malloc0(sizeof(*c));
  75    c->number = chassis_number;
  76    QLIST_INIT(&c->slots);
  77    QLIST_INSERT_HEAD(&chassis, c, next);
  78}
  79
  80static PCIESlot *pcie_chassis_find_slot_with_chassis(struct PCIEChassis *c,
  81                                                     uint8_t slot)
  82{
  83    PCIESlot *s;
  84    QLIST_FOREACH(s, &c->slots, next) {
  85        if (s->slot == slot) {
  86            break;
  87        }
  88    }
  89    return s;
  90}
  91
  92PCIESlot *pcie_chassis_find_slot(uint8_t chassis_number, uint16_t slot)
  93{
  94    struct PCIEChassis *c;
  95    c = pcie_chassis_find(chassis_number);
  96    if (!c) {
  97        return NULL;
  98    }
  99    return pcie_chassis_find_slot_with_chassis(c, slot);
 100}
 101
 102int pcie_chassis_add_slot(struct PCIESlot *slot)
 103{
 104    struct PCIEChassis *c;
 105    c = pcie_chassis_find(slot->chassis);
 106    if (!c) {
 107        return -ENODEV;
 108    }
 109    if (pcie_chassis_find_slot_with_chassis(c, slot->slot)) {
 110        return -EBUSY;
 111    }
 112    QLIST_INSERT_HEAD(&c->slots, slot, next);
 113    return 0;
 114}
 115
 116void pcie_chassis_del_slot(PCIESlot *s)
 117{
 118    QLIST_REMOVE(s, next);
 119}
 120
 121static Property pcie_port_props[] = {
 122    DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
 123    DEFINE_PROP_UINT16("aer_log_max", PCIEPort,
 124                       parent_obj.parent_obj.exp.aer_log.log_max,
 125                       PCIE_AER_LOG_MAX_DEFAULT),
 126    DEFINE_PROP_END_OF_LIST()
 127};
 128
 129static void pcie_port_class_init(ObjectClass *oc, void *data)
 130{
 131    DeviceClass *dc = DEVICE_CLASS(oc);
 132
 133    dc->props = pcie_port_props;
 134}
 135
 136static const TypeInfo pcie_port_type_info = {
 137    .name = TYPE_PCIE_PORT,
 138    .parent = TYPE_PCI_BRIDGE,
 139    .instance_size = sizeof(PCIEPort),
 140    .abstract = true,
 141    .class_init = pcie_port_class_init,
 142};
 143
 144static Property pcie_slot_props[] = {
 145    DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
 146    DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
 147    DEFINE_PROP_END_OF_LIST()
 148};
 149
 150static void pcie_slot_class_init(ObjectClass *oc, void *data)
 151{
 152    DeviceClass *dc = DEVICE_CLASS(oc);
 153    HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
 154
 155    dc->props = pcie_slot_props;
 156    hc->plug = pcie_cap_slot_hotplug_cb;
 157    hc->unplug_request = pcie_cap_slot_hot_unplug_request_cb;
 158}
 159
 160static const TypeInfo pcie_slot_type_info = {
 161    .name = TYPE_PCIE_SLOT,
 162    .parent = TYPE_PCIE_PORT,
 163    .instance_size = sizeof(PCIESlot),
 164    .abstract = true,
 165    .class_init = pcie_slot_class_init,
 166    .interfaces = (InterfaceInfo[]) {
 167        { TYPE_HOTPLUG_HANDLER },
 168        { }
 169    }
 170};
 171
 172static void pcie_port_register_types(void)
 173{
 174    type_register_static(&pcie_port_type_info);
 175    type_register_static(&pcie_slot_type_info);
 176}
 177
 178type_init(pcie_port_register_types)
 179