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25#include "hw/sysbus.h"
26#include "hw/hw.h"
27#include "hw/char/serial.h"
28#include "hw/block/flash.h"
29#include "sysemu/sysemu.h"
30#include "hw/devices.h"
31#include "hw/boards.h"
32#include "sysemu/device_tree.h"
33#include "hw/loader.h"
34#include "elf.h"
35#include "qemu/error-report.h"
36#include "qemu/log.h"
37#include "exec/address-spaces.h"
38
39#include "hw/ppc/ppc.h"
40#include "hw/ppc/ppc4xx.h"
41#include "ppc405.h"
42
43#include "sysemu/block-backend.h"
44
45#define EPAPR_MAGIC (0x45504150)
46#define FLASH_SIZE (16 * 1024 * 1024)
47
48#define INTC_BASEADDR 0x81800000
49#define UART16550_BASEADDR 0x83e01003
50#define TIMER_BASEADDR 0x83c00000
51#define PFLASH_BASEADDR 0xfc000000
52
53#define TIMER_IRQ 3
54#define UART16550_IRQ 9
55
56static struct boot_info
57{
58 uint32_t bootstrap_pc;
59 uint32_t cmdline;
60 uint32_t fdt;
61 uint32_t ima_size;
62 void *vfdt;
63} boot_info;
64
65
66static void mmubooke_create_initial_mapping(CPUPPCState *env,
67 target_ulong va,
68 hwaddr pa)
69{
70 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
71
72 tlb->attr = 0;
73 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
74 tlb->size = 1U << 31;
75 tlb->EPN = va & TARGET_PAGE_MASK;
76 tlb->RPN = pa & TARGET_PAGE_MASK;
77 tlb->PID = 0;
78
79 tlb = &env->tlb.tlbe[1];
80 tlb->attr = 0;
81 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
82 tlb->size = 1U << 31;
83 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
84 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
85 tlb->PID = 0;
86}
87
88static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size,
89 int do_init,
90 const char *cpu_model,
91 uint32_t sysclk)
92{
93 PowerPCCPU *cpu;
94 CPUPPCState *env;
95 qemu_irq *irqs;
96
97 cpu = cpu_ppc_init(cpu_model);
98 if (cpu == NULL) {
99 fprintf(stderr, "Unable to initialize CPU!\n");
100 exit(1);
101 }
102 env = &cpu->env;
103
104 ppc_booke_timers_init(cpu, sysclk, 0);
105
106 ppc_dcr_init(env, NULL, NULL);
107
108
109 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
110 irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
111 irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
112 ppcuic_init(env, irqs, 0x0C0, 0, 1);
113 return cpu;
114}
115
116static void main_cpu_reset(void *opaque)
117{
118 PowerPCCPU *cpu = opaque;
119 CPUPPCState *env = &cpu->env;
120 struct boot_info *bi = env->load_info;
121
122 cpu_reset(CPU(cpu));
123
124
125
126
127
128
129
130
131
132 env->gpr[1] = (16<<20) - 8;
133
134 env->gpr[3] = bi->fdt;
135 env->nip = bi->bootstrap_pc;
136
137
138 mmubooke_create_initial_mapping(env, 0, 0);
139 env->gpr[6] = tswap32(EPAPR_MAGIC);
140 env->gpr[7] = bi->ima_size;
141}
142
143#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
144static int xilinx_load_device_tree(hwaddr addr,
145 uint32_t ramsize,
146 hwaddr initrd_base,
147 hwaddr initrd_size,
148 const char *kernel_cmdline)
149{
150 char *path;
151 int fdt_size;
152 void *fdt = NULL;
153 int r;
154 const char *dtb_filename;
155
156 dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
157 if (dtb_filename) {
158 fdt = load_device_tree(dtb_filename, &fdt_size);
159 if (!fdt) {
160 error_report("Error while loading device tree file '%s'",
161 dtb_filename);
162 }
163 } else {
164
165 fdt = load_device_tree("ppc.dtb", &fdt_size);
166 if (!fdt) {
167 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
168 if (path) {
169 fdt = load_device_tree(path, &fdt_size);
170 g_free(path);
171 }
172 }
173 }
174 if (!fdt) {
175 return 0;
176 }
177
178 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
179 initrd_base);
180 if (r < 0) {
181 error_report("couldn't set /chosen/linux,initrd-start");
182 }
183
184 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
185 (initrd_base + initrd_size));
186 if (r < 0) {
187 error_report("couldn't set /chosen/linux,initrd-end");
188 }
189
190 r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
191 if (r < 0)
192 fprintf(stderr, "couldn't set /chosen/bootargs\n");
193 cpu_physical_memory_write(addr, fdt, fdt_size);
194 return fdt_size;
195}
196
197static void virtex_init(MachineState *machine)
198{
199 ram_addr_t ram_size = machine->ram_size;
200 const char *kernel_filename = machine->kernel_filename;
201 const char *kernel_cmdline = machine->kernel_cmdline;
202 hwaddr initrd_base = 0;
203 int initrd_size = 0;
204 MemoryRegion *address_space_mem = get_system_memory();
205 DeviceState *dev;
206 PowerPCCPU *cpu;
207 CPUPPCState *env;
208 hwaddr ram_base = 0;
209 DriveInfo *dinfo;
210 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
211 qemu_irq irq[32], *cpu_irq;
212 int kernel_size;
213 int i;
214
215
216 if (machine->cpu_model == NULL) {
217 machine->cpu_model = "440-Xilinx";
218 }
219
220 cpu = ppc440_init_xilinx(&ram_size, 1, machine->cpu_model, 400000000);
221 env = &cpu->env;
222 qemu_register_reset(main_cpu_reset, cpu);
223
224 memory_region_allocate_system_memory(phys_ram, NULL, "ram", ram_size);
225 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
226
227 dinfo = drive_get(IF_PFLASH, 0, 0);
228 pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE,
229 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
230 (64 * 1024), FLASH_SIZE >> 16,
231 1, 0x89, 0x18, 0x0000, 0x0, 1);
232
233 cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
234 dev = qdev_create(NULL, "xlnx.xps-intc");
235 qdev_prop_set_uint32(dev, "kind-of-intr", 0);
236 qdev_init_nofail(dev);
237 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
238 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
239 for (i = 0; i < 32; i++) {
240 irq[i] = qdev_get_gpio_in(dev, i);
241 }
242
243 serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
244 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);
245
246
247 dev = qdev_create(NULL, "xlnx.xps-timer");
248 qdev_prop_set_uint32(dev, "one-timer-only", 0);
249 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
250 qdev_init_nofail(dev);
251 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
252 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
253
254 if (kernel_filename) {
255 uint64_t entry, low, high;
256 hwaddr boot_offset;
257
258
259 kernel_size = load_elf(kernel_filename, NULL, NULL,
260 &entry, &low, &high, 1, PPC_ELF_MACHINE, 0);
261 boot_info.bootstrap_pc = entry & 0x00ffffff;
262
263 if (kernel_size < 0) {
264 boot_offset = 0x1200000;
265
266 kernel_size = load_image_targphys(kernel_filename,
267 boot_offset,
268 ram_size);
269 boot_info.bootstrap_pc = boot_offset;
270 high = boot_info.bootstrap_pc + kernel_size + 8192;
271 }
272
273 boot_info.ima_size = kernel_size;
274
275
276 if (machine->initrd_filename) {
277 initrd_base = high = ROUND_UP(high, 4);
278 initrd_size = load_image_targphys(machine->initrd_filename,
279 high, ram_size - high);
280
281 if (initrd_size < 0) {
282 error_report("couldn't load ram disk '%s'",
283 machine->initrd_filename);
284 exit(1);
285 }
286 high = ROUND_UP(high + initrd_size, 4);
287 }
288
289
290 boot_info.fdt = high + (8192 * 2);
291 boot_info.fdt &= ~8191;
292
293 xilinx_load_device_tree(boot_info.fdt, ram_size,
294 initrd_base, initrd_size,
295 kernel_cmdline);
296 }
297 env->load_info = &boot_info;
298}
299
300static void virtex_machine_init(MachineClass *mc)
301{
302 mc->desc = "Xilinx Virtex ML507 reference design";
303 mc->init = virtex_init;
304}
305
306DEFINE_MACHINE("virtex-ml507", virtex_machine_init)
307
