qemu/hw/timer/slavio_timer.c
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   1/*
   2 * QEMU Sparc SLAVIO timer controller emulation
   3 *
   4 * Copyright (c) 2003-2005 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "hw/sparc/sun4m.h"
  26#include "qemu/timer.h"
  27#include "hw/ptimer.h"
  28#include "hw/sysbus.h"
  29#include "trace.h"
  30#include "qemu/main-loop.h"
  31
  32/*
  33 * Registers of hardware timer in sun4m.
  34 *
  35 * This is the timer/counter part of chip STP2001 (Slave I/O), also
  36 * produced as NCR89C105. See
  37 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  38 *
  39 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
  40 * are zero. Bit 31 is 1 when count has been reached.
  41 *
  42 * Per-CPU timers interrupt local CPU, system timer uses normal
  43 * interrupt routing.
  44 *
  45 */
  46
  47#define MAX_CPUS 16
  48
  49typedef struct CPUTimerState {
  50    qemu_irq irq;
  51    ptimer_state *timer;
  52    uint32_t count, counthigh, reached;
  53    /* processor only */
  54    uint32_t run;
  55    uint64_t limit;
  56} CPUTimerState;
  57
  58#define TYPE_SLAVIO_TIMER "slavio_timer"
  59#define SLAVIO_TIMER(obj) \
  60    OBJECT_CHECK(SLAVIO_TIMERState, (obj), TYPE_SLAVIO_TIMER)
  61
  62typedef struct SLAVIO_TIMERState {
  63    SysBusDevice parent_obj;
  64
  65    uint32_t num_cpus;
  66    uint32_t cputimer_mode;
  67    CPUTimerState cputimer[MAX_CPUS + 1];
  68} SLAVIO_TIMERState;
  69
  70typedef struct TimerContext {
  71    MemoryRegion iomem;
  72    SLAVIO_TIMERState *s;
  73    unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
  74} TimerContext;
  75
  76#define SYS_TIMER_SIZE 0x14
  77#define CPU_TIMER_SIZE 0x10
  78
  79#define TIMER_LIMIT         0
  80#define TIMER_COUNTER       1
  81#define TIMER_COUNTER_NORST 2
  82#define TIMER_STATUS        3
  83#define TIMER_MODE          4
  84
  85#define TIMER_COUNT_MASK32 0xfffffe00
  86#define TIMER_LIMIT_MASK32 0x7fffffff
  87#define TIMER_MAX_COUNT64  0x7ffffffffffffe00ULL
  88#define TIMER_MAX_COUNT32  0x7ffffe00ULL
  89#define TIMER_REACHED      0x80000000
  90#define TIMER_PERIOD       500ULL // 500ns
  91#define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
  92#define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)
  93
  94static int slavio_timer_is_user(TimerContext *tc)
  95{
  96    SLAVIO_TIMERState *s = tc->s;
  97    unsigned int timer_index = tc->timer_index;
  98
  99    return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
 100}
 101
 102// Update count, set irq, update expire_time
 103// Convert from ptimer countdown units
 104static void slavio_timer_get_out(CPUTimerState *t)
 105{
 106    uint64_t count, limit;
 107
 108    if (t->limit == 0) { /* free-run system or processor counter */
 109        limit = TIMER_MAX_COUNT32;
 110    } else {
 111        limit = t->limit;
 112    }
 113    count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
 114
 115    trace_slavio_timer_get_out(t->limit, t->counthigh, t->count);
 116    t->count = count & TIMER_COUNT_MASK32;
 117    t->counthigh = count >> 32;
 118}
 119
 120// timer callback
 121static void slavio_timer_irq(void *opaque)
 122{
 123    TimerContext *tc = opaque;
 124    SLAVIO_TIMERState *s = tc->s;
 125    CPUTimerState *t = &s->cputimer[tc->timer_index];
 126
 127    slavio_timer_get_out(t);
 128    trace_slavio_timer_irq(t->counthigh, t->count);
 129    /* if limit is 0 (free-run), there will be no match */
 130    if (t->limit != 0) {
 131        t->reached = TIMER_REACHED;
 132    }
 133    /* there is no interrupt if user timer or free-run */
 134    if (!slavio_timer_is_user(tc) && t->limit != 0) {
 135        qemu_irq_raise(t->irq);
 136    }
 137}
 138
 139static uint64_t slavio_timer_mem_readl(void *opaque, hwaddr addr,
 140                                       unsigned size)
 141{
 142    TimerContext *tc = opaque;
 143    SLAVIO_TIMERState *s = tc->s;
 144    uint32_t saddr, ret;
 145    unsigned int timer_index = tc->timer_index;
 146    CPUTimerState *t = &s->cputimer[timer_index];
 147
 148    saddr = addr >> 2;
 149    switch (saddr) {
 150    case TIMER_LIMIT:
 151        // read limit (system counter mode) or read most signifying
 152        // part of counter (user mode)
 153        if (slavio_timer_is_user(tc)) {
 154            // read user timer MSW
 155            slavio_timer_get_out(t);
 156            ret = t->counthigh | t->reached;
 157        } else {
 158            // read limit
 159            // clear irq
 160            qemu_irq_lower(t->irq);
 161            t->reached = 0;
 162            ret = t->limit & TIMER_LIMIT_MASK32;
 163        }
 164        break;
 165    case TIMER_COUNTER:
 166        // read counter and reached bit (system mode) or read lsbits
 167        // of counter (user mode)
 168        slavio_timer_get_out(t);
 169        if (slavio_timer_is_user(tc)) { // read user timer LSW
 170            ret = t->count & TIMER_MAX_COUNT64;
 171        } else { // read limit
 172            ret = (t->count & TIMER_MAX_COUNT32) |
 173                t->reached;
 174        }
 175        break;
 176    case TIMER_STATUS:
 177        // only available in processor counter/timer
 178        // read start/stop status
 179        if (timer_index > 0) {
 180            ret = t->run;
 181        } else {
 182            ret = 0;
 183        }
 184        break;
 185    case TIMER_MODE:
 186        // only available in system counter
 187        // read user/system mode
 188        ret = s->cputimer_mode;
 189        break;
 190    default:
 191        trace_slavio_timer_mem_readl_invalid(addr);
 192        ret = 0;
 193        break;
 194    }
 195    trace_slavio_timer_mem_readl(addr, ret);
 196    return ret;
 197}
 198
 199static void slavio_timer_mem_writel(void *opaque, hwaddr addr,
 200                                    uint64_t val, unsigned size)
 201{
 202    TimerContext *tc = opaque;
 203    SLAVIO_TIMERState *s = tc->s;
 204    uint32_t saddr;
 205    unsigned int timer_index = tc->timer_index;
 206    CPUTimerState *t = &s->cputimer[timer_index];
 207
 208    trace_slavio_timer_mem_writel(addr, val);
 209    saddr = addr >> 2;
 210    switch (saddr) {
 211    case TIMER_LIMIT:
 212        if (slavio_timer_is_user(tc)) {
 213            uint64_t count;
 214
 215            // set user counter MSW, reset counter
 216            t->limit = TIMER_MAX_COUNT64;
 217            t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
 218            t->reached = 0;
 219            count = ((uint64_t)t->counthigh << 32) | t->count;
 220            trace_slavio_timer_mem_writel_limit(timer_index, count);
 221            ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
 222        } else {
 223            // set limit, reset counter
 224            qemu_irq_lower(t->irq);
 225            t->limit = val & TIMER_MAX_COUNT32;
 226            if (t->timer) {
 227                if (t->limit == 0) { /* free-run */
 228                    ptimer_set_limit(t->timer,
 229                                     LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
 230                } else {
 231                    ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
 232                }
 233            }
 234        }
 235        break;
 236    case TIMER_COUNTER:
 237        if (slavio_timer_is_user(tc)) {
 238            uint64_t count;
 239
 240            // set user counter LSW, reset counter
 241            t->limit = TIMER_MAX_COUNT64;
 242            t->count = val & TIMER_MAX_COUNT64;
 243            t->reached = 0;
 244            count = ((uint64_t)t->counthigh) << 32 | t->count;
 245            trace_slavio_timer_mem_writel_limit(timer_index, count);
 246            ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
 247        } else {
 248            trace_slavio_timer_mem_writel_counter_invalid();
 249        }
 250        break;
 251    case TIMER_COUNTER_NORST:
 252        // set limit without resetting counter
 253        t->limit = val & TIMER_MAX_COUNT32;
 254        if (t->limit == 0) { /* free-run */
 255            ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
 256        } else {
 257            ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
 258        }
 259        break;
 260    case TIMER_STATUS:
 261        if (slavio_timer_is_user(tc)) {
 262            // start/stop user counter
 263            if (val & 1) {
 264                trace_slavio_timer_mem_writel_status_start(timer_index);
 265                ptimer_run(t->timer, 0);
 266            } else {
 267                trace_slavio_timer_mem_writel_status_stop(timer_index);
 268                ptimer_stop(t->timer);
 269            }
 270        }
 271        t->run = val & 1;
 272        break;
 273    case TIMER_MODE:
 274        if (timer_index == 0) {
 275            unsigned int i;
 276
 277            for (i = 0; i < s->num_cpus; i++) {
 278                unsigned int processor = 1 << i;
 279                CPUTimerState *curr_timer = &s->cputimer[i + 1];
 280
 281                // check for a change in timer mode for this processor
 282                if ((val & processor) != (s->cputimer_mode & processor)) {
 283                    if (val & processor) { // counter -> user timer
 284                        qemu_irq_lower(curr_timer->irq);
 285                        // counters are always running
 286                        if (!curr_timer->run) {
 287                            ptimer_stop(curr_timer->timer);
 288                        }
 289                        // user timer limit is always the same
 290                        curr_timer->limit = TIMER_MAX_COUNT64;
 291                        ptimer_set_limit(curr_timer->timer,
 292                                         LIMIT_TO_PERIODS(curr_timer->limit),
 293                                         1);
 294                        // set this processors user timer bit in config
 295                        // register
 296                        s->cputimer_mode |= processor;
 297                        trace_slavio_timer_mem_writel_mode_user(timer_index);
 298                    } else { // user timer -> counter
 299                        // start the counter
 300                        ptimer_run(curr_timer->timer, 0);
 301                        // clear this processors user timer bit in config
 302                        // register
 303                        s->cputimer_mode &= ~processor;
 304                        trace_slavio_timer_mem_writel_mode_counter(timer_index);
 305                    }
 306                }
 307            }
 308        } else {
 309            trace_slavio_timer_mem_writel_mode_invalid();
 310        }
 311        break;
 312    default:
 313        trace_slavio_timer_mem_writel_invalid(addr);
 314        break;
 315    }
 316}
 317
 318static const MemoryRegionOps slavio_timer_mem_ops = {
 319    .read = slavio_timer_mem_readl,
 320    .write = slavio_timer_mem_writel,
 321    .endianness = DEVICE_NATIVE_ENDIAN,
 322    .valid = {
 323        .min_access_size = 4,
 324        .max_access_size = 4,
 325    },
 326};
 327
 328static const VMStateDescription vmstate_timer = {
 329    .name ="timer",
 330    .version_id = 3,
 331    .minimum_version_id = 3,
 332    .fields = (VMStateField[]) {
 333        VMSTATE_UINT64(limit, CPUTimerState),
 334        VMSTATE_UINT32(count, CPUTimerState),
 335        VMSTATE_UINT32(counthigh, CPUTimerState),
 336        VMSTATE_UINT32(reached, CPUTimerState),
 337        VMSTATE_UINT32(run    , CPUTimerState),
 338        VMSTATE_PTIMER(timer, CPUTimerState),
 339        VMSTATE_END_OF_LIST()
 340    }
 341};
 342
 343static const VMStateDescription vmstate_slavio_timer = {
 344    .name ="slavio_timer",
 345    .version_id = 3,
 346    .minimum_version_id = 3,
 347    .fields = (VMStateField[]) {
 348        VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
 349                             vmstate_timer, CPUTimerState),
 350        VMSTATE_END_OF_LIST()
 351    }
 352};
 353
 354static void slavio_timer_reset(DeviceState *d)
 355{
 356    SLAVIO_TIMERState *s = SLAVIO_TIMER(d);
 357    unsigned int i;
 358    CPUTimerState *curr_timer;
 359
 360    for (i = 0; i <= MAX_CPUS; i++) {
 361        curr_timer = &s->cputimer[i];
 362        curr_timer->limit = 0;
 363        curr_timer->count = 0;
 364        curr_timer->reached = 0;
 365        if (i <= s->num_cpus) {
 366            ptimer_set_limit(curr_timer->timer,
 367                             LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
 368            ptimer_run(curr_timer->timer, 0);
 369            curr_timer->run = 1;
 370        }
 371    }
 372    s->cputimer_mode = 0;
 373}
 374
 375static int slavio_timer_init1(SysBusDevice *dev)
 376{
 377    SLAVIO_TIMERState *s = SLAVIO_TIMER(dev);
 378    QEMUBH *bh;
 379    unsigned int i;
 380    TimerContext *tc;
 381
 382    for (i = 0; i <= MAX_CPUS; i++) {
 383        uint64_t size;
 384        char timer_name[20];
 385
 386        tc = g_malloc0(sizeof(TimerContext));
 387        tc->s = s;
 388        tc->timer_index = i;
 389
 390        bh = qemu_bh_new(slavio_timer_irq, tc);
 391        s->cputimer[i].timer = ptimer_init(bh);
 392        ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
 393
 394        size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE;
 395        snprintf(timer_name, sizeof(timer_name), "timer-%i", i);
 396        memory_region_init_io(&tc->iomem, OBJECT(s), &slavio_timer_mem_ops, tc,
 397                              timer_name, size);
 398        sysbus_init_mmio(dev, &tc->iomem);
 399
 400        sysbus_init_irq(dev, &s->cputimer[i].irq);
 401    }
 402
 403    return 0;
 404}
 405
 406static Property slavio_timer_properties[] = {
 407    DEFINE_PROP_UINT32("num_cpus",  SLAVIO_TIMERState, num_cpus,  0),
 408    DEFINE_PROP_END_OF_LIST(),
 409};
 410
 411static void slavio_timer_class_init(ObjectClass *klass, void *data)
 412{
 413    DeviceClass *dc = DEVICE_CLASS(klass);
 414    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 415
 416    k->init = slavio_timer_init1;
 417    dc->reset = slavio_timer_reset;
 418    dc->vmsd = &vmstate_slavio_timer;
 419    dc->props = slavio_timer_properties;
 420}
 421
 422static const TypeInfo slavio_timer_info = {
 423    .name          = TYPE_SLAVIO_TIMER,
 424    .parent        = TYPE_SYS_BUS_DEVICE,
 425    .instance_size = sizeof(SLAVIO_TIMERState),
 426    .class_init    = slavio_timer_class_init,
 427};
 428
 429static void slavio_timer_register_types(void)
 430{
 431    type_register_static(&slavio_timer_info);
 432}
 433
 434type_init(slavio_timer_register_types)
 435