LXR qemu/include/exec/cpu-common.h

   1#ifndef CPU_COMMON_H
   2#define CPU_COMMON_H 1
   3
   4/* CPU interfaces that are target independent.  */
   5
   6#ifndef CONFIG_USER_ONLY
   7#include "exec/hwaddr.h"
   8#endif
   9
  10#ifndef NEED_CPU_H
  11#include "exec/poison.h"
  12#endif
  13
  14#include "qemu/bswap.h"
  15#include "qemu/queue.h"
  16#include "qemu/fprintf-fn.h"
  17#include "qemu/typedefs.h"
  18
  19/**
  20 * CPUListState:
  21 * @cpu_fprintf: Print function.
  22 * @file: File to print to using @cpu_fprint.
  23 *
  24 * State commonly used for iterating over CPU models.
  25 */
  26typedef struct CPUListState {
  27    fprintf_function cpu_fprintf;
  28    FILE *file;
  29} CPUListState;
  30
  31typedef enum MMUAccessType {
  32    MMU_DATA_LOAD  = 0,
  33    MMU_DATA_STORE = 1,
  34    MMU_INST_FETCH = 2
  35} MMUAccessType;
  36
  37#if !defined(CONFIG_USER_ONLY)
  38
  39enum device_endian {
  40    DEVICE_NATIVE_ENDIAN,
  41    DEVICE_BIG_ENDIAN,
  42    DEVICE_LITTLE_ENDIAN,
  43};
  44
  45/* address in the RAM (different from a physical address) */
  46#if defined(CONFIG_XEN_BACKEND)
  47typedef uint64_t ram_addr_t;
  48#  define RAM_ADDR_MAX UINT64_MAX
  49#  define RAM_ADDR_FMT "%" PRIx64
  50#else
  51typedef uintptr_t ram_addr_t;
  52#  define RAM_ADDR_MAX UINTPTR_MAX
  53#  define RAM_ADDR_FMT "%" PRIxPTR
  54#endif
  55
  56extern ram_addr_t ram_size;
  57ram_addr_t get_current_ram_size(void);
  58
  59/* memory API */
  60
  61typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
  62typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
  63
  64void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
  65/* This should not be used by devices.  */
  66MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
  67RAMBlock *qemu_ram_block_by_name(const char *name);
  68RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
  69                                   ram_addr_t *ram_addr, ram_addr_t *offset);
  70void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
  71void qemu_ram_unset_idstr(ram_addr_t addr);
  72const char *qemu_ram_get_idstr(RAMBlock *rb);
  73
  74void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
  75                            int len, int is_write);
  76static inline void cpu_physical_memory_read(hwaddr addr,
  77                                            void *buf, int len)
  78{
  79    cpu_physical_memory_rw(addr, buf, len, 0);
  80}
  81static inline void cpu_physical_memory_write(hwaddr addr,
  82                                             const void *buf, int len)
  83{
  84    cpu_physical_memory_rw(addr, (void *)buf, len, 1);
  85}
  86void *cpu_physical_memory_map(hwaddr addr,
  87                              hwaddr *plen,
  88                              int is_write);
  89void cpu_physical_memory_unmap(void *buffer, hwaddr len,
  90                               int is_write, hwaddr access_len);
  91void cpu_register_map_client(QEMUBH *bh);
  92void cpu_unregister_map_client(QEMUBH *bh);
  93
  94bool cpu_physical_memory_is_io(hwaddr phys_addr);
  95
  96/* Coalesced MMIO regions are areas where write operations can be reordered.
  97 * This usually implies that write operations are side-effect free.  This allows
  98 * batching which can make a major impact on performance when using
  99 * virtualization.
 100 */
 101void qemu_flush_coalesced_mmio_buffer(void);
 102
 103uint32_t ldub_phys(AddressSpace *as, hwaddr addr);
 104uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr);
 105uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr);
 106uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
 107uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
 108uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
 109uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
 110void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 111void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 112void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 113void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 114void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 115void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
 116void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
 117
 118#ifdef NEED_CPU_H
 119uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
 120uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
 121uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
 122void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
 123void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 124void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 125void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
 126#endif
 127
 128void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
 129                                   const uint8_t *buf, int len);
 130void cpu_flush_icache_range(hwaddr start, int len);
 131
 132extern struct MemoryRegion io_mem_rom;
 133extern struct MemoryRegion io_mem_notdirty;
 134
 135typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr,
 136    ram_addr_t offset, ram_addr_t length, void *opaque);
 137
 138int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
 139
 140#endif
 141
 142#endif /* !CPU_COMMON_H */
 143