1#if !defined(__HW_SPAPR_H__)
2#define __HW_SPAPR_H__
3
4#include "sysemu/dma.h"
5#include "hw/boards.h"
6#include "hw/ppc/xics.h"
7#include "hw/ppc/spapr_drc.h"
8#include "hw/mem/pc-dimm.h"
9
10struct VIOsPAPRBus;
11struct sPAPRPHBState;
12struct sPAPRNVRAM;
13typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState;
14typedef struct sPAPREventLogEntry sPAPREventLogEntry;
15
16#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
17#define SPAPR_ENTRY_POINT 0x100
18
19typedef struct sPAPRMachineClass sPAPRMachineClass;
20typedef struct sPAPRMachineState sPAPRMachineState;
21
22#define TYPE_SPAPR_MACHINE "spapr-machine"
23#define SPAPR_MACHINE(obj) \
24 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
25#define SPAPR_MACHINE_GET_CLASS(obj) \
26 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
27#define SPAPR_MACHINE_CLASS(klass) \
28 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
29
30
31
32
33struct sPAPRMachineClass {
34
35 MachineClass parent_class;
36
37
38 bool dr_lmb_enabled;
39};
40
41
42
43
44struct sPAPRMachineState {
45
46 MachineState parent_obj;
47
48 struct VIOsPAPRBus *vio_bus;
49 QLIST_HEAD(, sPAPRPHBState) phbs;
50 struct sPAPRNVRAM *nvram;
51 XICSState *icp;
52 DeviceState *rtc;
53
54 void *htab;
55 uint32_t htab_shift;
56 hwaddr rma_size;
57 int vrma_adjust;
58 hwaddr fdt_addr, rtas_addr;
59 ssize_t rtas_size;
60 void *rtas_blob;
61 void *fdt_skel;
62 uint64_t rtc_offset;
63 struct PPCTimebase tb;
64 bool has_graphics;
65
66 uint32_t check_exception_irq;
67 Notifier epow_notifier;
68 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
69
70
71 int htab_save_index;
72 bool htab_first_pass;
73 int htab_fd;
74 bool htab_fd_stale;
75
76
77 QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list;
78
79
80 char *kvm_type;
81 MemoryHotplugState hotplug_memory;
82};
83
84#define H_SUCCESS 0
85#define H_BUSY 1
86#define H_CLOSED 2
87#define H_NOT_AVAILABLE 3
88#define H_CONSTRAINED 4
89#define H_PARTIAL 5
90#define H_IN_PROGRESS 14
91#define H_PAGE_REGISTERED 15
92#define H_PARTIAL_STORE 16
93#define H_PENDING 17
94#define H_CONTINUE 18
95#define H_LONG_BUSY_START_RANGE 9900
96#define H_LONG_BUSY_ORDER_1_MSEC 9900
97
98#define H_LONG_BUSY_ORDER_10_MSEC 9901
99
100#define H_LONG_BUSY_ORDER_100_MSEC 9902
101
102#define H_LONG_BUSY_ORDER_1_SEC 9903
103
104#define H_LONG_BUSY_ORDER_10_SEC 9904
105
106#define H_LONG_BUSY_ORDER_100_SEC 9905
107
108#define H_LONG_BUSY_END_RANGE 9905
109#define H_HARDWARE -1
110#define H_FUNCTION -2
111#define H_PRIVILEGE -3
112#define H_PARAMETER -4
113#define H_BAD_MODE -5
114#define H_PTEG_FULL -6
115#define H_NOT_FOUND -7
116#define H_RESERVED_DABR -8
117#define H_NO_MEM -9
118#define H_AUTHORITY -10
119#define H_PERMISSION -11
120#define H_DROPPED -12
121#define H_SOURCE_PARM -13
122#define H_DEST_PARM -14
123#define H_REMOTE_PARM -15
124#define H_RESOURCE -16
125#define H_ADAPTER_PARM -17
126#define H_RH_PARM -18
127#define H_RCQ_PARM -19
128#define H_SCQ_PARM -20
129#define H_EQ_PARM -21
130#define H_RT_PARM -22
131#define H_ST_PARM -23
132#define H_SIGT_PARM -24
133#define H_TOKEN_PARM -25
134#define H_MLENGTH_PARM -27
135#define H_MEM_PARM -28
136#define H_MEM_ACCESS_PARM -29
137#define H_ATTR_PARM -30
138#define H_PORT_PARM -31
139#define H_MCG_PARM -32
140#define H_VL_PARM -33
141#define H_TSIZE_PARM -34
142#define H_TRACE_PARM -35
143
144#define H_MASK_PARM -37
145#define H_MCG_FULL -38
146#define H_ALIAS_EXIST -39
147#define H_P_COUNTER -40
148#define H_TABLE_FULL -41
149#define H_ALT_TABLE -42
150#define H_MR_CONDITION -43
151#define H_NOT_ENOUGH_RESOURCES -44
152#define H_R_STATE -45
153#define H_RESCINDEND -46
154#define H_P2 -55
155#define H_P3 -56
156#define H_P4 -57
157#define H_P5 -58
158#define H_P6 -59
159#define H_P7 -60
160#define H_P8 -61
161#define H_P9 -62
162#define H_UNSUPPORTED_FLAG -256
163#define H_MULTI_THREADS_ACTIVE -9005
164
165
166
167
168
169
170
171
172
173
174#define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
175 && (x <= H_LONG_BUSY_END_RANGE))
176
177
178#define H_LARGE_PAGE (1ULL<<(63-16))
179#define H_EXACT (1ULL<<(63-24))
180#define H_R_XLATE (1ULL<<(63-25))
181#define H_READ_4 (1ULL<<(63-26))
182#define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
183#define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
184#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
185#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
186#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
187#define H_AVPN (1ULL<<(63-32))
188#define H_ANDCOND (1ULL<<(63-33))
189#define H_ICACHE_INVALIDATE (1ULL<<(63-40))
190#define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))
191#define H_ZERO_PAGE (1ULL<<(63-48))
192#define H_COPY_PAGE (1ULL<<(63-49))
193#define H_N (1ULL<<(63-61))
194#define H_PP1 (1ULL<<(63-62))
195#define H_PP2 (1ULL<<(63-63))
196
197
198#define H_SET_MODE_RESOURCE_SET_CIABR 1
199#define H_SET_MODE_RESOURCE_SET_DAWR 2
200#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
201#define H_SET_MODE_RESOURCE_LE 4
202
203
204#define H_SET_MODE_ENDIAN_BIG 0
205#define H_SET_MODE_ENDIAN_LITTLE 1
206
207
208#define H_SET_MODE_ADDR_TRANS_NONE 0
209#define H_SET_MODE_ADDR_TRANS_0001_8000 2
210#define H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000 3
211
212
213#define H_VASI_INVALID 0
214#define H_VASI_ENABLED 1
215#define H_VASI_ABORTED 2
216#define H_VASI_SUSPENDING 3
217#define H_VASI_SUSPENDED 4
218#define H_VASI_RESUMED 5
219#define H_VASI_COMPLETED 6
220
221
222#define H_DABRX_HYPERVISOR (1ULL<<(63-61))
223#define H_DABRX_KERNEL (1ULL<<(63-62))
224#define H_DABRX_USER (1ULL<<(63-63))
225
226
227#define H_CB_ALIGNMENT 4096
228
229
230#define H_REMOVE 0x04
231#define H_ENTER 0x08
232#define H_READ 0x0c
233#define H_CLEAR_MOD 0x10
234#define H_CLEAR_REF 0x14
235#define H_PROTECT 0x18
236#define H_GET_TCE 0x1c
237#define H_PUT_TCE 0x20
238#define H_SET_SPRG0 0x24
239#define H_SET_DABR 0x28
240#define H_PAGE_INIT 0x2c
241#define H_SET_ASR 0x30
242#define H_ASR_ON 0x34
243#define H_ASR_OFF 0x38
244#define H_LOGICAL_CI_LOAD 0x3c
245#define H_LOGICAL_CI_STORE 0x40
246#define H_LOGICAL_CACHE_LOAD 0x44
247#define H_LOGICAL_CACHE_STORE 0x48
248#define H_LOGICAL_ICBI 0x4c
249#define H_LOGICAL_DCBF 0x50
250#define H_GET_TERM_CHAR 0x54
251#define H_PUT_TERM_CHAR 0x58
252#define H_REAL_TO_LOGICAL 0x5c
253#define H_HYPERVISOR_DATA 0x60
254#define H_EOI 0x64
255#define H_CPPR 0x68
256#define H_IPI 0x6c
257#define H_IPOLL 0x70
258#define H_XIRR 0x74
259#define H_PERFMON 0x7c
260#define H_MIGRATE_DMA 0x78
261#define H_REGISTER_VPA 0xDC
262#define H_CEDE 0xE0
263#define H_CONFER 0xE4
264#define H_PROD 0xE8
265#define H_GET_PPP 0xEC
266#define H_SET_PPP 0xF0
267#define H_PURR 0xF4
268#define H_PIC 0xF8
269#define H_REG_CRQ 0xFC
270#define H_FREE_CRQ 0x100
271#define H_VIO_SIGNAL 0x104
272#define H_SEND_CRQ 0x108
273#define H_COPY_RDMA 0x110
274#define H_REGISTER_LOGICAL_LAN 0x114
275#define H_FREE_LOGICAL_LAN 0x118
276#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
277#define H_SEND_LOGICAL_LAN 0x120
278#define H_BULK_REMOVE 0x124
279#define H_MULTICAST_CTRL 0x130
280#define H_SET_XDABR 0x134
281#define H_STUFF_TCE 0x138
282#define H_PUT_TCE_INDIRECT 0x13C
283#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
284#define H_VTERM_PARTNER_INFO 0x150
285#define H_REGISTER_VTERM 0x154
286#define H_FREE_VTERM 0x158
287#define H_RESET_EVENTS 0x15C
288#define H_ALLOC_RESOURCE 0x160
289#define H_FREE_RESOURCE 0x164
290#define H_MODIFY_QP 0x168
291#define H_QUERY_QP 0x16C
292#define H_REREGISTER_PMR 0x170
293#define H_REGISTER_SMR 0x174
294#define H_QUERY_MR 0x178
295#define H_QUERY_MW 0x17C
296#define H_QUERY_HCA 0x180
297#define H_QUERY_PORT 0x184
298#define H_MODIFY_PORT 0x188
299#define H_DEFINE_AQP1 0x18C
300#define H_GET_TRACE_BUFFER 0x190
301#define H_DEFINE_AQP0 0x194
302#define H_RESIZE_MR 0x198
303#define H_ATTACH_MCQP 0x19C
304#define H_DETACH_MCQP 0x1A0
305#define H_CREATE_RPT 0x1A4
306#define H_REMOVE_RPT 0x1A8
307#define H_REGISTER_RPAGES 0x1AC
308#define H_DISABLE_AND_GETC 0x1B0
309#define H_ERROR_DATA 0x1B4
310#define H_GET_HCA_INFO 0x1B8
311#define H_GET_PERF_COUNT 0x1BC
312#define H_MANAGE_TRACE 0x1C0
313#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
314#define H_QUERY_INT_STATE 0x1E4
315#define H_POLL_PENDING 0x1D8
316#define H_ILLAN_ATTRIBUTES 0x244
317#define H_MODIFY_HEA_QP 0x250
318#define H_QUERY_HEA_QP 0x254
319#define H_QUERY_HEA 0x258
320#define H_QUERY_HEA_PORT 0x25C
321#define H_MODIFY_HEA_PORT 0x260
322#define H_REG_BCMC 0x264
323#define H_DEREG_BCMC 0x268
324#define H_REGISTER_HEA_RPAGES 0x26C
325#define H_DISABLE_AND_GET_HEA 0x270
326#define H_GET_HEA_INFO 0x274
327#define H_ALLOC_HEA_RESOURCE 0x278
328#define H_ADD_CONN 0x284
329#define H_DEL_CONN 0x288
330#define H_JOIN 0x298
331#define H_VASI_STATE 0x2A4
332#define H_ENABLE_CRQ 0x2B0
333#define H_GET_EM_PARMS 0x2B8
334#define H_SET_MPP 0x2D0
335#define H_GET_MPP 0x2D4
336#define H_XIRR_X 0x2FC
337#define H_RANDOM 0x300
338#define H_SET_MODE 0x31C
339#define MAX_HCALL_OPCODE H_SET_MODE
340
341
342
343
344
345
346
347
348
349#define KVMPPC_HCALL_BASE 0xf000
350#define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
351#define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
352
353#define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
354#define KVMPPC_HCALL_MAX KVMPPC_H_CAS
355
356typedef struct sPAPRDeviceTreeUpdateHeader {
357 uint32_t version_id;
358} sPAPRDeviceTreeUpdateHeader;
359
360#define hcall_dprintf(fmt, ...) \
361 do { \
362 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
363 } while (0)
364
365typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
366 target_ulong opcode,
367 target_ulong *args);
368
369void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
370target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
371 target_ulong *args);
372
373int spapr_allocate_irq(int hint, bool lsi);
374int spapr_allocate_irq_block(int num, bool lsi, bool msi);
375
376
377#define RTAS_EEH_DISABLE 0
378#define RTAS_EEH_ENABLE 1
379#define RTAS_EEH_THAW_IO 2
380#define RTAS_EEH_THAW_DMA 3
381
382
383#define RTAS_GET_PE_ADDR 0
384#define RTAS_GET_PE_MODE 1
385#define RTAS_PE_MODE_NONE 0
386#define RTAS_PE_MODE_NOT_SHARED 1
387#define RTAS_PE_MODE_SHARED 2
388
389
390#define RTAS_EEH_PE_STATE_NORMAL 0
391#define RTAS_EEH_PE_STATE_RESET 1
392#define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
393#define RTAS_EEH_PE_STATE_STOPPED_DMA 4
394#define RTAS_EEH_PE_STATE_UNAVAIL 5
395#define RTAS_EEH_NOT_SUPPORT 0
396#define RTAS_EEH_SUPPORT 1
397#define RTAS_EEH_PE_UNAVAIL_INFO 1000
398#define RTAS_EEH_PE_RECOVER_INFO 0
399
400
401#define RTAS_SLOT_RESET_DEACTIVATE 0
402#define RTAS_SLOT_RESET_HOT 1
403#define RTAS_SLOT_RESET_FUNDAMENTAL 3
404
405
406#define RTAS_SLOT_TEMP_ERR_LOG 1
407#define RTAS_SLOT_PERM_ERR_LOG 2
408
409
410#define RTAS_OUT_SUCCESS 0
411#define RTAS_OUT_NO_ERRORS_FOUND 1
412#define RTAS_OUT_HW_ERROR -1
413#define RTAS_OUT_BUSY -2
414#define RTAS_OUT_PARAM_ERROR -3
415#define RTAS_OUT_NOT_SUPPORTED -3
416#define RTAS_OUT_NO_SUCH_INDICATOR -3
417#define RTAS_OUT_NOT_AUTHORIZED -9002
418
419
420#define RTAS_TOKEN_BASE 0x2000
421
422#define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
423#define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
424#define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
425#define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
426#define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
427#define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
428#define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
429#define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
430#define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
431#define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
432#define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
433#define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
434#define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
435#define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
436#define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
437#define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
438#define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
439#define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
440#define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
441#define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
442#define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
443#define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
444#define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
445#define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
446#define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
447#define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
448#define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
449#define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
450#define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
451#define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
452#define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
453#define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
454#define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
455#define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
456#define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
457#define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
458#define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
459#define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
460
461#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x26)
462
463
464#define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
465#define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
466#define RTAS_SYSPARM_UUID 48
467
468
469
470
471
472
473
474#define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
475#define RTAS_SENSOR_TYPE_DR 9002
476#define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
477#define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
478
479
480
481
482#define DIAGNOSTICS_RUN_MODE_DISABLED 0
483#define DIAGNOSTICS_RUN_MODE_STAGGERED 1
484#define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
485#define DIAGNOSTICS_RUN_MODE_PERIODIC 3
486
487static inline uint64_t ppc64_phys_to_real(uint64_t addr)
488{
489 return addr & ~0xF000000000000000ULL;
490}
491
492static inline uint32_t rtas_ld(target_ulong phys, int n)
493{
494 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
495}
496
497static inline uint64_t rtas_ldq(target_ulong phys, int n)
498{
499 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
500}
501
502static inline void rtas_st(target_ulong phys, int n, uint32_t val)
503{
504 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
505}
506
507static inline void rtas_st_buffer_direct(target_ulong phys,
508 target_ulong phys_len,
509 uint8_t *buffer, uint16_t buffer_len)
510{
511 cpu_physical_memory_write(ppc64_phys_to_real(phys), buffer,
512 MIN(buffer_len, phys_len));
513}
514
515static inline void rtas_st_buffer(target_ulong phys, target_ulong phys_len,
516 uint8_t *buffer, uint16_t buffer_len)
517{
518 if (phys_len < 2) {
519 return;
520 }
521 stw_be_phys(&address_space_memory,
522 ppc64_phys_to_real(phys), buffer_len);
523 rtas_st_buffer_direct(phys + 2, phys_len - 2, buffer, buffer_len);
524}
525
526typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
527 uint32_t token,
528 uint32_t nargs, target_ulong args,
529 uint32_t nret, target_ulong rets);
530void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
531target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
532 uint32_t token, uint32_t nargs, target_ulong args,
533 uint32_t nret, target_ulong rets);
534int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
535 hwaddr rtas_size);
536
537#define SPAPR_TCE_PAGE_SHIFT 12
538#define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
539#define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
540
541#define SPAPR_VIO_BASE_LIOBN 0x00000000
542#define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
543#define SPAPR_PCI_LIOBN(phb_index, window_num) \
544 (0x80000000 | ((phb_index) << 8) | (window_num))
545#define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
546#define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
547
548#define RTAS_ERROR_LOG_MAX 2048
549
550#define RTAS_EVENT_SCAN_RATE 1
551
552typedef struct sPAPRTCETable sPAPRTCETable;
553
554#define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
555#define SPAPR_TCE_TABLE(obj) \
556 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
557
558struct sPAPRTCETable {
559 DeviceState parent;
560 uint32_t liobn;
561 uint32_t nb_table;
562 uint64_t bus_offset;
563 uint32_t page_shift;
564 uint64_t *table;
565 bool bypass;
566 bool need_vfio;
567 int fd;
568 MemoryRegion iommu;
569 struct VIOsPAPRDevice *vdev;
570 QLIST_ENTRY(sPAPRTCETable) list;
571};
572
573sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn);
574
575struct sPAPREventLogEntry {
576 int log_type;
577 bool exception;
578 void *data;
579 QTAILQ_ENTRY(sPAPREventLogEntry) next;
580};
581
582void spapr_events_init(sPAPRMachineState *sm);
583void spapr_events_fdt_skel(void *fdt, uint32_t epow_irq);
584int spapr_h_cas_compose_response(sPAPRMachineState *sm,
585 target_ulong addr, target_ulong size,
586 bool cpu_update, bool memory_update);
587sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn,
588 uint64_t bus_offset,
589 uint32_t page_shift,
590 uint32_t nb_table,
591 bool need_vfio);
592void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
593
594MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
595int spapr_dma_dt(void *fdt, int node_off, const char *propname,
596 uint32_t liobn, uint64_t window, uint32_t size);
597int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
598 sPAPRTCETable *tcet);
599void spapr_pci_switch_vga(bool big_endian);
600void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
601void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
602void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
603 uint32_t count);
604void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
605 uint32_t count);
606
607
608struct sPAPRConfigureConnectorState {
609 uint32_t drc_index;
610 int fdt_offset;
611 int fdt_depth;
612 QTAILQ_ENTRY(sPAPRConfigureConnectorState) next;
613};
614
615void spapr_ccs_reset_hook(void *opaque);
616
617#define TYPE_SPAPR_RTC "spapr-rtc"
618#define TYPE_SPAPR_RNG "spapr-rng"
619
620void spapr_rtc_read(DeviceState *dev, struct tm *tm, uint32_t *ns);
621int spapr_rtc_import_offset(DeviceState *dev, int64_t legacy_offset);
622
623int spapr_rng_populate_dt(void *fdt);
624
625#define SPAPR_MEMORY_BLOCK_SIZE (1 << 28)
626
627
628
629
630
631
632#define SPAPR_MAX_RAM_SLOTS 32
633
634
635#define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30)
636
637
638
639
640
641#define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
642
643
644
645
646
647#define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
648
649#endif
650