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22#ifndef __ARM_KVM_H__
23#define __ARM_KVM_H__
24
25#define KVM_SPSR_EL1 0
26#define KVM_SPSR_SVC KVM_SPSR_EL1
27#define KVM_SPSR_ABT 1
28#define KVM_SPSR_UND 2
29#define KVM_SPSR_IRQ 3
30#define KVM_SPSR_FIQ 4
31#define KVM_NR_SPSR 5
32
33#ifndef __ASSEMBLY__
34#include <linux/psci.h>
35#include <asm/types.h>
36#include <asm/ptrace.h>
37
38#define __KVM_HAVE_GUEST_DEBUG
39#define __KVM_HAVE_IRQ_LINE
40#define __KVM_HAVE_READONLY_MEM
41
42#define KVM_REG_SIZE(id) \
43 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
44
45struct kvm_regs {
46 struct user_pt_regs regs;
47
48 __u64 sp_el1;
49 __u64 elr_el1;
50
51 __u64 spsr[KVM_NR_SPSR];
52
53 struct user_fpsimd_state fp_regs;
54};
55
56
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58
59
60
61#define KVM_ARM_TARGET_AEM_V8 0
62#define KVM_ARM_TARGET_FOUNDATION_V8 1
63#define KVM_ARM_TARGET_CORTEX_A57 2
64#define KVM_ARM_TARGET_XGENE_POTENZA 3
65#define KVM_ARM_TARGET_CORTEX_A53 4
66
67#define KVM_ARM_TARGET_GENERIC_V8 5
68
69#define KVM_ARM_NUM_TARGETS 6
70
71
72#define KVM_ARM_DEVICE_TYPE_SHIFT 0
73#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
74#define KVM_ARM_DEVICE_ID_SHIFT 16
75#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
76
77
78#define KVM_ARM_DEVICE_VGIC_V2 0
79
80
81#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
82#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
83
84#define KVM_VGIC_V2_DIST_SIZE 0x1000
85#define KVM_VGIC_V2_CPU_SIZE 0x2000
86
87
88#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
89#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
90
91#define KVM_VGIC_V3_DIST_SIZE SZ_64K
92#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
93
94#define KVM_ARM_VCPU_POWER_OFF 0
95#define KVM_ARM_VCPU_EL1_32BIT 1
96#define KVM_ARM_VCPU_PSCI_0_2 2
97
98struct kvm_vcpu_init {
99 __u32 target;
100 __u32 features[7];
101};
102
103struct kvm_sregs {
104};
105
106struct kvm_fpu {
107};
108
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120
121
122#define KVM_ARM_MAX_DBG_REGS 16
123struct kvm_guest_debug_arch {
124 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
125 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
126 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
127 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
128};
129
130struct kvm_debug_exit_arch {
131 __u32 hsr;
132 __u64 far;
133};
134
135
136
137
138
139#define KVM_GUESTDBG_USE_SW_BP (1 << 16)
140#define KVM_GUESTDBG_USE_HW (1 << 17)
141
142struct kvm_sync_regs {
143};
144
145struct kvm_arch_memory_slot {
146};
147
148
149#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
150#define KVM_REG_ARM_COPROC_SHIFT 16
151
152
153#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
154#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
155
156
157#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
158#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
159#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
160#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
161#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
162#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
163
164
165#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
166#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
167#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
168#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
169#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
170#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
171#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
172#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
173#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
174#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
175#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
176
177#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
178 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
179 KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
180
181#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
182 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
183 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
184 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
185 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
186 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
187 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
188
189#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
190
191#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
192#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
193#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
194
195
196#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
197#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
198#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
199#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
200#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
201#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
202#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
203#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
204#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
205#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
206
207
208#define KVM_ARM_IRQ_TYPE_SHIFT 24
209#define KVM_ARM_IRQ_TYPE_MASK 0xff
210#define KVM_ARM_IRQ_VCPU_SHIFT 16
211#define KVM_ARM_IRQ_VCPU_MASK 0xff
212#define KVM_ARM_IRQ_NUM_SHIFT 0
213#define KVM_ARM_IRQ_NUM_MASK 0xffff
214
215
216#define KVM_ARM_IRQ_TYPE_CPU 0
217#define KVM_ARM_IRQ_TYPE_SPI 1
218#define KVM_ARM_IRQ_TYPE_PPI 2
219
220
221#define KVM_ARM_IRQ_CPU_IRQ 0
222#define KVM_ARM_IRQ_CPU_FIQ 1
223
224
225
226
227
228
229#define KVM_ARM_IRQ_GIC_MAX 127
230
231
232#define KVM_NR_IRQCHIPS 1
233
234
235#define KVM_PSCI_FN_BASE 0x95c1ba5e
236#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
237
238#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
239#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
240#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
241#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
242
243#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
244#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
245#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
246#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
247
248#endif
249
250#endif
251