LXR qemu/target-arm/translate.h

   1#ifndef TARGET_ARM_TRANSLATE_H
   2#define TARGET_ARM_TRANSLATE_H
   3
   4/* internal defines */
   5typedef struct DisasContext {
   6    target_ulong pc;
   7    uint32_t insn;
   8    int is_jmp;
   9    /* Nonzero if this instruction has been conditionally skipped.  */
  10    int condjmp;
  11    /* The label that will be jumped to when the instruction is skipped.  */
  12    TCGLabel *condlabel;
  13    /* Thumb-2 conditional execution bits.  */
  14    int condexec_mask;
  15    int condexec_cond;
  16    struct TranslationBlock *tb;
  17    int singlestep_enabled;
  18    int thumb;
  19    int bswap_code;
  20#if !defined(CONFIG_USER_ONLY)
  21    int user;
  22#endif
  23    ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  24    bool ns;        /* Use non-secure CPREG bank on access */
  25    int fp_excp_el; /* FP exception EL or 0 if enabled */
  26    /* Flag indicating that exceptions from secure mode are routed to EL3. */
  27    bool secure_routed_to_el3;
  28    bool vfp_enabled; /* FP enabled via FPSCR.EN */
  29    int vec_len;
  30    int vec_stride;
  31    /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  32     * so that top level loop can generate correct syndrome information.
  33     */
  34    uint32_t svc_imm;
  35    int aarch64;
  36    int current_el;
  37    GHashTable *cp_regs;
  38    uint64_t features; /* CPU features bits */
  39    /* Because unallocated encodings generate different exception syndrome
  40     * information from traps due to FP being disabled, we can't do a single
  41     * "is fp access disabled" check at a high level in the decode tree.
  42     * To help in catching bugs where the access check was forgotten in some
  43     * code path, we set this flag when the access check is done, and assert
  44     * that it is set at the point where we actually touch the FP regs.
  45     */
  46    bool fp_access_checked;
  47    /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  48     * single-step support).
  49     */
  50    bool ss_active;
  51    bool pstate_ss;
  52    /* True if the insn just emitted was a load-exclusive instruction
  53     * (necessary for syndrome information for single step exceptions),
  54     * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  55     */
  56    bool is_ldex;
  57    /* True if a single-step exception will be taken to the current EL */
  58    bool ss_same_el;
  59    /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
  60    int c15_cpar;
  61#define TMP_A64_MAX 16
  62    int tmp_a64_count;
  63    TCGv_i64 tmp_a64[TMP_A64_MAX];
  64} DisasContext;
  65
  66typedef struct DisasCompare {
  67    TCGCond cond;
  68    TCGv_i32 value;
  69    bool value_global;
  70} DisasCompare;
  71
  72/* Share the TCG temporaries common between 32 and 64 bit modes.  */
  73extern TCGv_ptr cpu_env;
  74extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
  75extern TCGv_i64 cpu_exclusive_addr;
  76extern TCGv_i64 cpu_exclusive_val;
  77#ifdef CONFIG_USER_ONLY
  78extern TCGv_i64 cpu_exclusive_test;
  79extern TCGv_i32 cpu_exclusive_info;
  80#endif
  81
  82static inline int arm_dc_feature(DisasContext *dc, int feature)
  83{
  84    return (dc->features & (1ULL << feature)) != 0;
  85}
  86
  87static inline int get_mem_index(DisasContext *s)
  88{
  89    return s->mmu_idx;
  90}
  91
  92/* Function used to determine the target exception EL when otherwise not known
  93 * or default.
  94 */
  95static inline int default_exception_el(DisasContext *s)
  96{
  97    /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
  98     * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
  99     * exceptions can only be routed to ELs above 1, so we target the higher of
 100     * 1 or the current EL.
 101     */
 102    return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
 103            ? 3 : MAX(1, s->current_el);
 104}
 105
 106/* target-specific extra values for is_jmp */
 107/* These instructions trap after executing, so the A32/T32 decoder must
 108 * defer them until after the conditional execution state has been updated.
 109 * WFI also needs special handling when single-stepping.
 110 */
 111#define DISAS_WFI 4
 112#define DISAS_SWI 5
 113/* For instructions which unconditionally cause an exception we can skip
 114 * emitting unreachable code at the end of the TB in the A64 decoder
 115 */
 116#define DISAS_EXC 6
 117/* WFE */
 118#define DISAS_WFE 7
 119#define DISAS_HVC 8
 120#define DISAS_SMC 9
 121#define DISAS_YIELD 10
 122
 123#ifdef TARGET_AARCH64
 124void a64_translate_init(void);
 125void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);
 126void gen_a64_set_pc_im(uint64_t val);
 127void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 128                            fprintf_function cpu_fprintf, int flags);
 129#else
 130static inline void a64_translate_init(void)
 131{
 132}
 133
 134static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
 135{
 136}
 137
 138static inline void gen_a64_set_pc_im(uint64_t val)
 139{
 140}
 141
 142static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
 143                                          fprintf_function cpu_fprintf,
 144                                          int flags)
 145{
 146}
 147#endif
 148
 149void arm_test_cc(DisasCompare *cmp, int cc);
 150void arm_free_cc(DisasCompare *cmp);
 151void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 152void arm_gen_test_cc(int cc, TCGLabel *label);
 153
 154#endif /* TARGET_ARM_TRANSLATE_H */
 155