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23#include <stdio.h>
24#include <unistd.h>
25#include <sys/mman.h>
26#include <sys/types.h>
27#include <sys/stat.h>
28#include "hw/hw.h"
29#include "hw/i386/pc.h"
30#include "qemu/error-report.h"
31#include "ui/console.h"
32#include "hw/loader.h"
33#include "monitor/monitor.h"
34#include "qemu/range.h"
35#include "sysemu/sysemu.h"
36#include "hw/pci/pci.h"
37#include "hw/pci/msi.h"
38#include "kvm_i386.h"
39#include "hw/pci/pci-assign.h"
40
41#define MSIX_PAGE_SIZE 0x1000
42
43
44#define IORESOURCE_IO 0x00000100
45#define IORESOURCE_MEM 0x00000200
46#define IORESOURCE_IRQ 0x00000400
47#define IORESOURCE_DMA 0x00000800
48#define IORESOURCE_PREFETCH 0x00002000
49#define IORESOURCE_MEM_64 0x00100000
50
51typedef struct PCIRegion {
52 int type;
53 int valid;
54 uint64_t base_addr;
55 uint64_t size;
56 int resource_fd;
57} PCIRegion;
58
59typedef struct PCIDevRegions {
60 uint8_t bus, dev, func;
61 int irq;
62 uint16_t region_number;
63
64
65 PCIRegion regions[PCI_NUM_REGIONS - 1];
66 int config_fd;
67} PCIDevRegions;
68
69typedef struct AssignedDevRegion {
70 MemoryRegion container;
71 MemoryRegion real_iomem;
72 union {
73 uint8_t *r_virtbase;
74 uint32_t r_baseport;
75 } u;
76 pcibus_t e_size;
77 pcibus_t r_size;
78 PCIRegion *region;
79} AssignedDevRegion;
80
81#define ASSIGNED_DEVICE_PREFER_MSI_BIT 0
82#define ASSIGNED_DEVICE_SHARE_INTX_BIT 1
83
84#define ASSIGNED_DEVICE_PREFER_MSI_MASK (1 << ASSIGNED_DEVICE_PREFER_MSI_BIT)
85#define ASSIGNED_DEVICE_SHARE_INTX_MASK (1 << ASSIGNED_DEVICE_SHARE_INTX_BIT)
86
87typedef struct MSIXTableEntry {
88 uint32_t addr_lo;
89 uint32_t addr_hi;
90 uint32_t data;
91 uint32_t ctrl;
92} MSIXTableEntry;
93
94typedef enum AssignedIRQType {
95 ASSIGNED_IRQ_NONE = 0,
96 ASSIGNED_IRQ_INTX_HOST_INTX,
97 ASSIGNED_IRQ_INTX_HOST_MSI,
98 ASSIGNED_IRQ_MSI,
99 ASSIGNED_IRQ_MSIX
100} AssignedIRQType;
101
102typedef struct AssignedDevice {
103 PCIDevice dev;
104 PCIHostDeviceAddress host;
105 uint32_t dev_id;
106 uint32_t features;
107 int intpin;
108 AssignedDevRegion v_addrs[PCI_NUM_REGIONS - 1];
109 PCIDevRegions real_device;
110 PCIINTxRoute intx_route;
111 AssignedIRQType assigned_irq_type;
112 struct {
113#define ASSIGNED_DEVICE_CAP_MSI (1 << 0)
114#define ASSIGNED_DEVICE_CAP_MSIX (1 << 1)
115 uint32_t available;
116#define ASSIGNED_DEVICE_MSI_ENABLED (1 << 0)
117#define ASSIGNED_DEVICE_MSIX_ENABLED (1 << 1)
118#define ASSIGNED_DEVICE_MSIX_MASKED (1 << 2)
119 uint32_t state;
120 } cap;
121 uint8_t emulate_config_read[PCI_CONFIG_SPACE_SIZE];
122 uint8_t emulate_config_write[PCI_CONFIG_SPACE_SIZE];
123 int msi_virq_nr;
124 int *msi_virq;
125 MSIXTableEntry *msix_table;
126 hwaddr msix_table_addr;
127 uint16_t msix_max;
128 MemoryRegion mmio;
129 char *configfd_name;
130 int32_t bootindex;
131} AssignedDevice;
132
133#define TYPE_PCI_ASSIGN "kvm-pci-assign"
134#define PCI_ASSIGN(obj) OBJECT_CHECK(AssignedDevice, (obj), TYPE_PCI_ASSIGN)
135
136static void assigned_dev_update_irq_routing(PCIDevice *dev);
137
138static void assigned_dev_load_option_rom(AssignedDevice *dev);
139
140static void assigned_dev_unregister_msix_mmio(AssignedDevice *dev);
141
142static uint64_t assigned_dev_ioport_rw(AssignedDevRegion *dev_region,
143 hwaddr addr, int size,
144 uint64_t *data)
145{
146 uint64_t val = 0;
147 int fd = dev_region->region->resource_fd;
148
149 if (data) {
150 DEBUG("pwrite data=%" PRIx64 ", size=%d, e_phys=" TARGET_FMT_plx
151 ", addr="TARGET_FMT_plx"\n", *data, size, addr, addr);
152 if (pwrite(fd, data, size, addr) != size) {
153 error_report("%s - pwrite failed %s", __func__, strerror(errno));
154 }
155 } else {
156 if (pread(fd, &val, size, addr) != size) {
157 error_report("%s - pread failed %s", __func__, strerror(errno));
158 val = (1UL << (size * 8)) - 1;
159 }
160 DEBUG("pread val=%" PRIx64 ", size=%d, e_phys=" TARGET_FMT_plx
161 ", addr=" TARGET_FMT_plx "\n", val, size, addr, addr);
162 }
163 return val;
164}
165
166static void assigned_dev_ioport_write(void *opaque, hwaddr addr,
167 uint64_t data, unsigned size)
168{
169 assigned_dev_ioport_rw(opaque, addr, size, &data);
170}
171
172static uint64_t assigned_dev_ioport_read(void *opaque,
173 hwaddr addr, unsigned size)
174{
175 return assigned_dev_ioport_rw(opaque, addr, size, NULL);
176}
177
178static uint32_t slow_bar_readb(void *opaque, hwaddr addr)
179{
180 AssignedDevRegion *d = opaque;
181 uint8_t *in = d->u.r_virtbase + addr;
182 uint32_t r;
183
184 r = *in;
185 DEBUG("addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r);
186
187 return r;
188}
189
190static uint32_t slow_bar_readw(void *opaque, hwaddr addr)
191{
192 AssignedDevRegion *d = opaque;
193 uint16_t *in = (uint16_t *)(d->u.r_virtbase + addr);
194 uint32_t r;
195
196 r = *in;
197 DEBUG("addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r);
198
199 return r;
200}
201
202static uint32_t slow_bar_readl(void *opaque, hwaddr addr)
203{
204 AssignedDevRegion *d = opaque;
205 uint32_t *in = (uint32_t *)(d->u.r_virtbase + addr);
206 uint32_t r;
207
208 r = *in;
209 DEBUG("addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r);
210
211 return r;
212}
213
214static void slow_bar_writeb(void *opaque, hwaddr addr, uint32_t val)
215{
216 AssignedDevRegion *d = opaque;
217 uint8_t *out = d->u.r_virtbase + addr;
218
219 DEBUG("addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr, val);
220 *out = val;
221}
222
223static void slow_bar_writew(void *opaque, hwaddr addr, uint32_t val)
224{
225 AssignedDevRegion *d = opaque;
226 uint16_t *out = (uint16_t *)(d->u.r_virtbase + addr);
227
228 DEBUG("addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr, val);
229 *out = val;
230}
231
232static void slow_bar_writel(void *opaque, hwaddr addr, uint32_t val)
233{
234 AssignedDevRegion *d = opaque;
235 uint32_t *out = (uint32_t *)(d->u.r_virtbase + addr);
236
237 DEBUG("addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, val);
238 *out = val;
239}
240
241static const MemoryRegionOps slow_bar_ops = {
242 .old_mmio = {
243 .read = { slow_bar_readb, slow_bar_readw, slow_bar_readl, },
244 .write = { slow_bar_writeb, slow_bar_writew, slow_bar_writel, },
245 },
246 .endianness = DEVICE_NATIVE_ENDIAN,
247};
248
249static void assigned_dev_iomem_setup(PCIDevice *pci_dev, int region_num,
250 pcibus_t e_size)
251{
252 AssignedDevice *r_dev = PCI_ASSIGN(pci_dev);
253 AssignedDevRegion *region = &r_dev->v_addrs[region_num];
254 PCIRegion *real_region = &r_dev->real_device.regions[region_num];
255
256 if (e_size > 0) {
257 memory_region_init(®ion->container, OBJECT(pci_dev),
258 "assigned-dev-container", e_size);
259 memory_region_add_subregion(®ion->container, 0, ®ion->real_iomem);
260
261
262 if (real_region->base_addr <= r_dev->msix_table_addr &&
263 real_region->base_addr + real_region->size >
264 r_dev->msix_table_addr) {
265 uint64_t offset = r_dev->msix_table_addr - real_region->base_addr;
266
267 memory_region_add_subregion_overlap(®ion->container,
268 offset,
269 &r_dev->mmio,
270 1);
271 }
272 }
273}
274
275static const MemoryRegionOps assigned_dev_ioport_ops = {
276 .read = assigned_dev_ioport_read,
277 .write = assigned_dev_ioport_write,
278 .endianness = DEVICE_NATIVE_ENDIAN,
279};
280
281static void assigned_dev_ioport_setup(PCIDevice *pci_dev, int region_num,
282 pcibus_t size)
283{
284 AssignedDevice *r_dev = PCI_ASSIGN(pci_dev);
285 AssignedDevRegion *region = &r_dev->v_addrs[region_num];
286
287 region->e_size = size;
288 memory_region_init(®ion->container, OBJECT(pci_dev),
289 "assigned-dev-container", size);
290 memory_region_init_io(®ion->real_iomem, OBJECT(pci_dev),
291 &assigned_dev_ioport_ops, r_dev->v_addrs + region_num,
292 "assigned-dev-iomem", size);
293 memory_region_add_subregion(®ion->container, 0, ®ion->real_iomem);
294}
295
296static uint32_t assigned_dev_pci_read(PCIDevice *d, int pos, int len)
297{
298 AssignedDevice *pci_dev = PCI_ASSIGN(d);
299 uint32_t val;
300 ssize_t ret;
301 int fd = pci_dev->real_device.config_fd;
302
303again:
304 ret = pread(fd, &val, len, pos);
305 if (ret != len) {
306 if ((ret < 0) && (errno == EINTR || errno == EAGAIN)) {
307 goto again;
308 }
309
310 hw_error("pci read failed, ret = %zd errno = %d\n", ret, errno);
311 }
312
313 return val;
314}
315
316static uint8_t assigned_dev_pci_read_byte(PCIDevice *d, int pos)
317{
318 return (uint8_t)assigned_dev_pci_read(d, pos, 1);
319}
320
321static void assigned_dev_pci_write(PCIDevice *d, int pos, uint32_t val, int len)
322{
323 AssignedDevice *pci_dev = PCI_ASSIGN(d);
324 ssize_t ret;
325 int fd = pci_dev->real_device.config_fd;
326
327again:
328 ret = pwrite(fd, &val, len, pos);
329 if (ret != len) {
330 if ((ret < 0) && (errno == EINTR || errno == EAGAIN)) {
331 goto again;
332 }
333
334 hw_error("pci write failed, ret = %zd errno = %d\n", ret, errno);
335 }
336}
337
338static void assigned_dev_emulate_config_read(AssignedDevice *dev,
339 uint32_t offset, uint32_t len)
340{
341 memset(dev->emulate_config_read + offset, 0xff, len);
342}
343
344static void assigned_dev_direct_config_read(AssignedDevice *dev,
345 uint32_t offset, uint32_t len)
346{
347 memset(dev->emulate_config_read + offset, 0, len);
348}
349
350static void assigned_dev_direct_config_write(AssignedDevice *dev,
351 uint32_t offset, uint32_t len)
352{
353 memset(dev->emulate_config_write + offset, 0, len);
354}
355
356static uint8_t pci_find_cap_offset(PCIDevice *d, uint8_t cap, uint8_t start)
357{
358 int id;
359 int max_cap = 48;
360 int pos = start ? start : PCI_CAPABILITY_LIST;
361 int status;
362
363 status = assigned_dev_pci_read_byte(d, PCI_STATUS);
364 if ((status & PCI_STATUS_CAP_LIST) == 0) {
365 return 0;
366 }
367
368 while (max_cap--) {
369 pos = assigned_dev_pci_read_byte(d, pos);
370 if (pos < 0x40) {
371 break;
372 }
373
374 pos &= ~3;
375 id = assigned_dev_pci_read_byte(d, pos + PCI_CAP_LIST_ID);
376
377 if (id == 0xff) {
378 break;
379 }
380 if (id == cap) {
381 return pos;
382 }
383
384 pos += PCI_CAP_LIST_NEXT;
385 }
386 return 0;
387}
388
389static void assigned_dev_register_regions(PCIRegion *io_regions,
390 unsigned long regions_num,
391 AssignedDevice *pci_dev,
392 Error **errp)
393{
394 uint32_t i;
395 PCIRegion *cur_region = io_regions;
396
397 for (i = 0; i < regions_num; i++, cur_region++) {
398 if (!cur_region->valid) {
399 continue;
400 }
401
402
403 if (cur_region->type & IORESOURCE_MEM) {
404 int t = PCI_BASE_ADDRESS_SPACE_MEMORY;
405 if (cur_region->type & IORESOURCE_PREFETCH) {
406 t |= PCI_BASE_ADDRESS_MEM_PREFETCH;
407 }
408 if (cur_region->type & IORESOURCE_MEM_64) {
409 t |= PCI_BASE_ADDRESS_MEM_TYPE_64;
410 }
411
412
413 pci_dev->v_addrs[i].u.r_virtbase = mmap(NULL, cur_region->size,
414 PROT_WRITE | PROT_READ,
415 MAP_SHARED,
416 cur_region->resource_fd,
417 (off_t)0);
418
419 if (pci_dev->v_addrs[i].u.r_virtbase == MAP_FAILED) {
420 pci_dev->v_addrs[i].u.r_virtbase = NULL;
421 error_setg_errno(errp, errno, "Couldn't mmap 0x%" PRIx64 "!",
422 cur_region->base_addr);
423 return;
424 }
425
426 pci_dev->v_addrs[i].r_size = cur_region->size;
427 pci_dev->v_addrs[i].e_size = 0;
428
429
430 pci_dev->v_addrs[i].u.r_virtbase +=
431 (cur_region->base_addr & 0xFFF);
432
433 if (cur_region->size & 0xFFF) {
434 error_report("PCI region %d at address 0x%" PRIx64 " has "
435 "size 0x%" PRIx64 ", which is not a multiple of "
436 "4K. You might experience some performance hit "
437 "due to that.",
438 i, cur_region->base_addr, cur_region->size);
439 memory_region_init_io(&pci_dev->v_addrs[i].real_iomem,
440 OBJECT(pci_dev), &slow_bar_ops,
441 &pci_dev->v_addrs[i],
442 "assigned-dev-slow-bar",
443 cur_region->size);
444 } else {
445 void *virtbase = pci_dev->v_addrs[i].u.r_virtbase;
446 char name[32];
447 snprintf(name, sizeof(name), "%s.bar%d",
448 object_get_typename(OBJECT(pci_dev)), i);
449 memory_region_init_ram_ptr(&pci_dev->v_addrs[i].real_iomem,
450 OBJECT(pci_dev), name,
451 cur_region->size, virtbase);
452 vmstate_register_ram(&pci_dev->v_addrs[i].real_iomem,
453 &pci_dev->dev.qdev);
454 }
455
456 assigned_dev_iomem_setup(&pci_dev->dev, i, cur_region->size);
457 pci_register_bar((PCIDevice *) pci_dev, i, t,
458 &pci_dev->v_addrs[i].container);
459 continue;
460 } else {
461
462 uint32_t val;
463 int ret;
464
465
466
467
468 ret = pread(pci_dev->v_addrs[i].region->resource_fd, &val, 3, 0);
469 if (ret >= 0) {
470 error_report("Unexpected return from I/O port read: %d", ret);
471 abort();
472 } else if (errno != EINVAL) {
473 error_report("Kernel doesn't support ioport resource "
474 "access, hiding this region.");
475 close(pci_dev->v_addrs[i].region->resource_fd);
476 cur_region->valid = 0;
477 continue;
478 }
479
480 pci_dev->v_addrs[i].u.r_baseport = cur_region->base_addr;
481 pci_dev->v_addrs[i].r_size = cur_region->size;
482 pci_dev->v_addrs[i].e_size = 0;
483
484 assigned_dev_ioport_setup(&pci_dev->dev, i, cur_region->size);
485 pci_register_bar((PCIDevice *) pci_dev, i,
486 PCI_BASE_ADDRESS_SPACE_IO,
487 &pci_dev->v_addrs[i].container);
488 }
489 }
490
491
492}
493
494static void get_real_id(const char *devpath, const char *idname, uint16_t *val,
495 Error **errp)
496{
497 FILE *f;
498 char name[128];
499 long id;
500
501 snprintf(name, sizeof(name), "%s%s", devpath, idname);
502 f = fopen(name, "r");
503 if (f == NULL) {
504 error_setg_file_open(errp, errno, name);
505 return;
506 }
507 if (fscanf(f, "%li\n", &id) == 1) {
508 *val = id;
509 } else {
510 error_setg(errp, "Failed to parse contents of '%s'", name);
511 }
512 fclose(f);
513}
514
515static void get_real_vendor_id(const char *devpath, uint16_t *val,
516 Error **errp)
517{
518 get_real_id(devpath, "vendor", val, errp);
519}
520
521static void get_real_device_id(const char *devpath, uint16_t *val,
522 Error **errp)
523{
524 get_real_id(devpath, "device", val, errp);
525}
526
527static void get_real_device(AssignedDevice *pci_dev, Error **errp)
528{
529 char dir[128], name[128];
530 int fd, r = 0;
531 FILE *f;
532 uint64_t start, end, size, flags;
533 uint16_t id;
534 PCIRegion *rp;
535 PCIDevRegions *dev = &pci_dev->real_device;
536 Error *local_err = NULL;
537
538 dev->region_number = 0;
539
540 snprintf(dir, sizeof(dir), "/sys/bus/pci/devices/%04x:%02x:%02x.%x/",
541 pci_dev->host.domain, pci_dev->host.bus,
542 pci_dev->host.slot, pci_dev->host.function);
543
544 snprintf(name, sizeof(name), "%sconfig", dir);
545
546 if (pci_dev->configfd_name && *pci_dev->configfd_name) {
547 dev->config_fd = monitor_fd_param(cur_mon, pci_dev->configfd_name,
548 &local_err);
549 if (local_err) {
550 error_propagate(errp, local_err);
551 return;
552 }
553 } else {
554 dev->config_fd = open(name, O_RDWR);
555
556 if (dev->config_fd == -1) {
557 error_setg_file_open(errp, errno, name);
558 return;
559 }
560 }
561again:
562 r = read(dev->config_fd, pci_dev->dev.config,
563 pci_config_size(&pci_dev->dev));
564 if (r < 0) {
565 if (errno == EINTR || errno == EAGAIN) {
566 goto again;
567 }
568 error_setg_errno(errp, errno, "read(\"%s\")",
569 (pci_dev->configfd_name && *pci_dev->configfd_name) ?
570 pci_dev->configfd_name : name);
571 return;
572 }
573
574
575 if (pci_dev->dev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
576 pci_dev->dev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
577 } else {
578 pci_dev->dev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
579 }
580
581
582
583
584 memset(&pci_dev->dev.config[PCI_BASE_ADDRESS_0], 0, 24);
585 memset(&pci_dev->dev.config[PCI_ROM_ADDRESS], 0, 4);
586
587 snprintf(name, sizeof(name), "%sresource", dir);
588
589 f = fopen(name, "r");
590 if (f == NULL) {
591 error_setg_file_open(errp, errno, name);
592 return;
593 }
594
595 for (r = 0; r < PCI_ROM_SLOT; r++) {
596 if (fscanf(f, "%" SCNi64 " %" SCNi64 " %" SCNi64 "\n",
597 &start, &end, &flags) != 3) {
598 break;
599 }
600
601 rp = dev->regions + r;
602 rp->valid = 0;
603 rp->resource_fd = -1;
604 size = end - start + 1;
605 flags &= IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH
606 | IORESOURCE_MEM_64;
607 if (size == 0 || (flags & ~IORESOURCE_PREFETCH) == 0) {
608 continue;
609 }
610 if (flags & IORESOURCE_MEM) {
611 flags &= ~IORESOURCE_IO;
612 } else {
613 flags &= ~IORESOURCE_PREFETCH;
614 }
615 snprintf(name, sizeof(name), "%sresource%d", dir, r);
616 fd = open(name, O_RDWR);
617 if (fd == -1) {
618 continue;
619 }
620 rp->resource_fd = fd;
621
622 rp->type = flags;
623 rp->valid = 1;
624 rp->base_addr = start;
625 rp->size = size;
626 pci_dev->v_addrs[r].region = rp;
627 DEBUG("region %d size %" PRIu64 " start 0x%" PRIx64
628 " type %d resource_fd %d\n",
629 r, rp->size, start, rp->type, rp->resource_fd);
630 }
631
632 fclose(f);
633
634
635 get_real_vendor_id(dir, &id, &local_err);
636 if (local_err) {
637 error_propagate(errp, local_err);
638 return;
639 }
640 pci_dev->dev.config[0] = id & 0xff;
641 pci_dev->dev.config[1] = (id & 0xff00) >> 8;
642
643
644 get_real_device_id(dir, &id, &local_err);
645 if (local_err) {
646 error_propagate(errp, local_err);
647 return;
648 }
649 pci_dev->dev.config[2] = id & 0xff;
650 pci_dev->dev.config[3] = (id & 0xff00) >> 8;
651
652 pci_word_test_and_clear_mask(pci_dev->emulate_config_write + PCI_COMMAND,
653 PCI_COMMAND_MASTER | PCI_COMMAND_INTX_DISABLE);
654
655 dev->region_number = r;
656}
657
658static void free_msi_virqs(AssignedDevice *dev)
659{
660 int i;
661
662 for (i = 0; i < dev->msi_virq_nr; i++) {
663 if (dev->msi_virq[i] >= 0) {
664 kvm_irqchip_release_virq(kvm_state, dev->msi_virq[i]);
665 dev->msi_virq[i] = -1;
666 }
667 }
668 g_free(dev->msi_virq);
669 dev->msi_virq = NULL;
670 dev->msi_virq_nr = 0;
671}
672
673static void free_assigned_device(AssignedDevice *dev)
674{
675 int i;
676
677 if (dev->cap.available & ASSIGNED_DEVICE_CAP_MSIX) {
678 assigned_dev_unregister_msix_mmio(dev);
679 }
680 for (i = 0; i < dev->real_device.region_number; i++) {
681 PCIRegion *pci_region = &dev->real_device.regions[i];
682 AssignedDevRegion *region = &dev->v_addrs[i];
683
684 if (!pci_region->valid) {
685 continue;
686 }
687 if (pci_region->type & IORESOURCE_IO) {
688 if (region->u.r_baseport) {
689 memory_region_del_subregion(®ion->container,
690 ®ion->real_iomem);
691 }
692 } else if (pci_region->type & IORESOURCE_MEM) {
693 if (region->u.r_virtbase) {
694 memory_region_del_subregion(®ion->container,
695 ®ion->real_iomem);
696
697
698 if (pci_region->base_addr <= dev->msix_table_addr &&
699 pci_region->base_addr + pci_region->size >
700 dev->msix_table_addr) {
701 memory_region_del_subregion(®ion->container,
702 &dev->mmio);
703 }
704 if (munmap(region->u.r_virtbase,
705 (pci_region->size + 0xFFF) & 0xFFFFF000)) {
706 error_report("Failed to unmap assigned device region: %s",
707 strerror(errno));
708 }
709 }
710 }
711 if (pci_region->resource_fd >= 0) {
712 close(pci_region->resource_fd);
713 }
714 }
715
716 if (dev->real_device.config_fd >= 0) {
717 close(dev->real_device.config_fd);
718 }
719
720 free_msi_virqs(dev);
721}
722
723
724
725
726
727
728static char *assign_failed_examine(const AssignedDevice *dev)
729{
730 char name[PATH_MAX], dir[PATH_MAX], driver[PATH_MAX] = {}, *ns;
731 uint16_t vendor_id, device_id;
732 int r;
733 Error *local_err = NULL;
734
735 snprintf(dir, sizeof(dir), "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/",
736 dev->host.domain, dev->host.bus, dev->host.slot,
737 dev->host.function);
738
739 snprintf(name, sizeof(name), "%sdriver", dir);
740
741 r = readlink(name, driver, sizeof(driver));
742 if ((r <= 0) || r >= sizeof(driver)) {
743 goto fail;
744 }
745
746 driver[r] = 0;
747 ns = strrchr(driver, '/');
748 if (!ns) {
749 goto fail;
750 }
751
752 ns++;
753
754 if ((get_real_vendor_id(dir, &vendor_id, &local_err), local_err) ||
755 (get_real_device_id(dir, &device_id, &local_err), local_err)) {
756
757
758
759 error_free(local_err);
760 goto fail;
761 }
762
763 return g_strdup_printf(
764 "*** The driver '%s' is occupying your device %04x:%02x:%02x.%x.\n"
765 "***\n"
766 "*** You can try the following commands to free it:\n"
767 "***\n"
768 "*** $ echo \"%04x %04x\" > /sys/bus/pci/drivers/pci-stub/new_id\n"
769 "*** $ echo \"%04x:%02x:%02x.%x\" > /sys/bus/pci/drivers/%s/unbind\n"
770 "*** $ echo \"%04x:%02x:%02x.%x\" > /sys/bus/pci/drivers/"
771 "pci-stub/bind\n"
772 "*** $ echo \"%04x %04x\" > /sys/bus/pci/drivers/pci-stub/remove_id\n"
773 "***",
774 ns, dev->host.domain, dev->host.bus, dev->host.slot,
775 dev->host.function, vendor_id, device_id,
776 dev->host.domain, dev->host.bus, dev->host.slot, dev->host.function,
777 ns, dev->host.domain, dev->host.bus, dev->host.slot,
778 dev->host.function, vendor_id, device_id);
779
780fail:
781 return g_strdup("Couldn't find out why.");
782}
783
784static void assign_device(AssignedDevice *dev, Error **errp)
785{
786 uint32_t flags = KVM_DEV_ASSIGN_ENABLE_IOMMU;
787 int r;
788
789
790 if (!kvm_check_extension(kvm_state, KVM_CAP_PCI_SEGMENT) &&
791 dev->host.domain) {
792 error_setg(errp, "Can't assign device inside non-zero PCI segment "
793 "as this KVM module doesn't support it.");
794 return;
795 }
796
797 if (!kvm_check_extension(kvm_state, KVM_CAP_IOMMU)) {
798 error_setg(errp, "No IOMMU found. Unable to assign device \"%s\"",
799 dev->dev.qdev.id);
800 return;
801 }
802
803 if (dev->features & ASSIGNED_DEVICE_SHARE_INTX_MASK &&
804 kvm_has_intx_set_mask()) {
805 flags |= KVM_DEV_ASSIGN_PCI_2_3;
806 }
807
808 r = kvm_device_pci_assign(kvm_state, &dev->host, flags, &dev->dev_id);
809 if (r < 0) {
810 switch (r) {
811 case -EBUSY: {
812 char *cause;
813
814 cause = assign_failed_examine(dev);
815 error_setg_errno(errp, -r, "Failed to assign device \"%s\"\n%s",
816 dev->dev.qdev.id, cause);
817 g_free(cause);
818 break;
819 }
820 default:
821 error_setg_errno(errp, -r, "Failed to assign device \"%s\"",
822 dev->dev.qdev.id);
823 break;
824 }
825 }
826}
827
828static void verify_irqchip_in_kernel(Error **errp)
829{
830 if (kvm_irqchip_in_kernel()) {
831 return;
832 }
833 error_setg(errp, "pci-assign requires KVM with in-kernel irqchip enabled");
834}
835
836static int assign_intx(AssignedDevice *dev, Error **errp)
837{
838 AssignedIRQType new_type;
839 PCIINTxRoute intx_route;
840 bool intx_host_msi;
841 int r;
842 Error *local_err = NULL;
843
844
845 if (assigned_dev_pci_read_byte(&dev->dev, PCI_INTERRUPT_PIN) == 0) {
846 pci_device_set_intx_routing_notifier(&dev->dev, NULL);
847 return 0;
848 }
849
850 verify_irqchip_in_kernel(&local_err);
851 if (local_err) {
852 error_propagate(errp, local_err);
853 return -ENOTSUP;
854 }
855
856 pci_device_set_intx_routing_notifier(&dev->dev,
857 assigned_dev_update_irq_routing);
858
859 intx_route = pci_device_route_intx_to_irq(&dev->dev, dev->intpin);
860 assert(intx_route.mode != PCI_INTX_INVERTED);
861
862 if (!pci_intx_route_changed(&dev->intx_route, &intx_route)) {
863 return 0;
864 }
865
866 switch (dev->assigned_irq_type) {
867 case ASSIGNED_IRQ_INTX_HOST_INTX:
868 case ASSIGNED_IRQ_INTX_HOST_MSI:
869 intx_host_msi = dev->assigned_irq_type == ASSIGNED_IRQ_INTX_HOST_MSI;
870 r = kvm_device_intx_deassign(kvm_state, dev->dev_id, intx_host_msi);
871 break;
872 case ASSIGNED_IRQ_MSI:
873 r = kvm_device_msi_deassign(kvm_state, dev->dev_id);
874 break;
875 case ASSIGNED_IRQ_MSIX:
876 r = kvm_device_msix_deassign(kvm_state, dev->dev_id);
877 break;
878 default:
879 r = 0;
880 break;
881 }
882 if (r) {
883 perror("assign_intx: deassignment of previous interrupt failed");
884 }
885 dev->assigned_irq_type = ASSIGNED_IRQ_NONE;
886
887 if (intx_route.mode == PCI_INTX_DISABLED) {
888 dev->intx_route = intx_route;
889 return 0;
890 }
891
892retry:
893 if (dev->features & ASSIGNED_DEVICE_PREFER_MSI_MASK &&
894 dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
895 intx_host_msi = true;
896 new_type = ASSIGNED_IRQ_INTX_HOST_MSI;
897 } else {
898 intx_host_msi = false;
899 new_type = ASSIGNED_IRQ_INTX_HOST_INTX;
900 }
901
902 r = kvm_device_intx_assign(kvm_state, dev->dev_id, intx_host_msi,
903 intx_route.irq);
904 if (r < 0) {
905 if (r == -EIO && !(dev->features & ASSIGNED_DEVICE_PREFER_MSI_MASK) &&
906 dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
907
908
909 error_report("Host-side INTx sharing not supported, "
910 "using MSI instead");
911 error_printf("Some devices do not work properly in this mode.\n");
912 dev->features |= ASSIGNED_DEVICE_PREFER_MSI_MASK;
913 goto retry;
914 }
915 error_setg_errno(errp, -r,
916 "Failed to assign irq for \"%s\"\n"
917 "Perhaps you are assigning a device "
918 "that shares an IRQ with another device?",
919 dev->dev.qdev.id);
920 return r;
921 }
922
923 dev->intx_route = intx_route;
924 dev->assigned_irq_type = new_type;
925 return r;
926}
927
928static void deassign_device(AssignedDevice *dev)
929{
930 int r;
931
932 r = kvm_device_pci_deassign(kvm_state, dev->dev_id);
933 assert(r == 0);
934}
935
936
937
938
939static void assigned_dev_update_irq_routing(PCIDevice *dev)
940{
941 AssignedDevice *assigned_dev = PCI_ASSIGN(dev);
942 Error *err = NULL;
943 int r;
944
945 r = assign_intx(assigned_dev, &err);
946 if (r < 0) {
947 error_report_err(err);
948 err = NULL;
949 qdev_unplug(&dev->qdev, &err);
950 assert(!err);
951 }
952}
953
954static void assigned_dev_update_msi(PCIDevice *pci_dev)
955{
956 AssignedDevice *assigned_dev = PCI_ASSIGN(pci_dev);
957 uint8_t ctrl_byte = pci_get_byte(pci_dev->config + pci_dev->msi_cap +
958 PCI_MSI_FLAGS);
959 int r;
960
961
962
963
964 if (assigned_dev->assigned_irq_type == ASSIGNED_IRQ_MSI ||
965 (ctrl_byte & PCI_MSI_FLAGS_ENABLE)) {
966 r = kvm_device_msi_deassign(kvm_state, assigned_dev->dev_id);
967
968 if (r && r != -ENXIO) {
969 perror("assigned_dev_update_msi: deassign irq");
970 }
971
972 free_msi_virqs(assigned_dev);
973
974 assigned_dev->assigned_irq_type = ASSIGNED_IRQ_NONE;
975 pci_device_set_intx_routing_notifier(pci_dev, NULL);
976 }
977
978 if (ctrl_byte & PCI_MSI_FLAGS_ENABLE) {
979 MSIMessage msg = msi_get_message(pci_dev, 0);
980 int virq;
981
982 virq = kvm_irqchip_add_msi_route(kvm_state, msg, pci_dev);
983 if (virq < 0) {
984 perror("assigned_dev_update_msi: kvm_irqchip_add_msi_route");
985 return;
986 }
987
988 assigned_dev->msi_virq = g_malloc(sizeof(*assigned_dev->msi_virq));
989 assigned_dev->msi_virq_nr = 1;
990 assigned_dev->msi_virq[0] = virq;
991 if (kvm_device_msi_assign(kvm_state, assigned_dev->dev_id, virq) < 0) {
992 perror("assigned_dev_update_msi: kvm_device_msi_assign");
993 }
994
995 assigned_dev->intx_route.mode = PCI_INTX_DISABLED;
996 assigned_dev->intx_route.irq = -1;
997 assigned_dev->assigned_irq_type = ASSIGNED_IRQ_MSI;
998 } else {
999 Error *local_err = NULL;
1000
1001 assign_intx(assigned_dev, &local_err);
1002 if (local_err) {
1003 error_report_err(local_err);
1004 }
1005 }
1006}
1007
1008static void assigned_dev_update_msi_msg(PCIDevice *pci_dev)
1009{
1010 AssignedDevice *assigned_dev = PCI_ASSIGN(pci_dev);
1011 uint8_t ctrl_byte = pci_get_byte(pci_dev->config + pci_dev->msi_cap +
1012 PCI_MSI_FLAGS);
1013
1014 if (assigned_dev->assigned_irq_type != ASSIGNED_IRQ_MSI ||
1015 !(ctrl_byte & PCI_MSI_FLAGS_ENABLE)) {
1016 return;
1017 }
1018
1019 kvm_irqchip_update_msi_route(kvm_state, assigned_dev->msi_virq[0],
1020 msi_get_message(pci_dev, 0), pci_dev);
1021}
1022
1023static bool assigned_dev_msix_masked(MSIXTableEntry *entry)
1024{
1025 return (entry->ctrl & cpu_to_le32(0x1)) != 0;
1026}
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036static bool assigned_dev_msix_skipped(MSIXTableEntry *entry)
1037{
1038 return !entry->data;
1039}
1040
1041static int assigned_dev_update_msix_mmio(PCIDevice *pci_dev)
1042{
1043 AssignedDevice *adev = PCI_ASSIGN(pci_dev);
1044 uint16_t entries_nr = 0;
1045 int i, r = 0;
1046 MSIXTableEntry *entry = adev->msix_table;
1047 MSIMessage msg;
1048
1049
1050 for (i = 0; i < adev->msix_max; i++, entry++) {
1051 if (assigned_dev_msix_skipped(entry)) {
1052 continue;
1053 }
1054 entries_nr++;
1055 }
1056
1057 DEBUG("MSI-X entries: %d\n", entries_nr);
1058
1059
1060 if (!entries_nr) {
1061 return 0;
1062 }
1063
1064 r = kvm_device_msix_init_vectors(kvm_state, adev->dev_id, entries_nr);
1065 if (r != 0) {
1066 error_report("fail to set MSI-X entry number for MSIX! %s",
1067 strerror(-r));
1068 return r;
1069 }
1070
1071 free_msi_virqs(adev);
1072
1073 adev->msi_virq_nr = adev->msix_max;
1074 adev->msi_virq = g_malloc(adev->msix_max * sizeof(*adev->msi_virq));
1075
1076 entry = adev->msix_table;
1077 for (i = 0; i < adev->msix_max; i++, entry++) {
1078 adev->msi_virq[i] = -1;
1079
1080 if (assigned_dev_msix_skipped(entry)) {
1081 continue;
1082 }
1083
1084 msg.address = entry->addr_lo | ((uint64_t)entry->addr_hi << 32);
1085 msg.data = entry->data;
1086 r = kvm_irqchip_add_msi_route(kvm_state, msg, pci_dev);
1087 if (r < 0) {
1088 return r;
1089 }
1090 adev->msi_virq[i] = r;
1091
1092 DEBUG("MSI-X vector %d, gsi %d, addr %08x_%08x, data %08x\n", i,
1093 r, entry->addr_hi, entry->addr_lo, entry->data);
1094
1095 r = kvm_device_msix_set_vector(kvm_state, adev->dev_id, i,
1096 adev->msi_virq[i]);
1097 if (r) {
1098 error_report("fail to set MSI-X entry! %s", strerror(-r));
1099 break;
1100 }
1101 }
1102
1103 return r;
1104}
1105
1106static void assigned_dev_update_msix(PCIDevice *pci_dev)
1107{
1108 AssignedDevice *assigned_dev = PCI_ASSIGN(pci_dev);
1109 uint16_t ctrl_word = pci_get_word(pci_dev->config + pci_dev->msix_cap +
1110 PCI_MSIX_FLAGS);
1111 int r;
1112
1113
1114
1115
1116 if ((assigned_dev->assigned_irq_type == ASSIGNED_IRQ_MSIX) ||
1117 (ctrl_word & PCI_MSIX_FLAGS_ENABLE)) {
1118 r = kvm_device_msix_deassign(kvm_state, assigned_dev->dev_id);
1119
1120 if (r && r != -ENXIO) {
1121 perror("assigned_dev_update_msix: deassign irq");
1122 }
1123
1124 free_msi_virqs(assigned_dev);
1125
1126 assigned_dev->assigned_irq_type = ASSIGNED_IRQ_NONE;
1127 pci_device_set_intx_routing_notifier(pci_dev, NULL);
1128 }
1129
1130 if (ctrl_word & PCI_MSIX_FLAGS_ENABLE) {
1131 if (assigned_dev_update_msix_mmio(pci_dev) < 0) {
1132 perror("assigned_dev_update_msix_mmio");
1133 return;
1134 }
1135
1136 if (assigned_dev->msi_virq_nr > 0) {
1137 if (kvm_device_msix_assign(kvm_state, assigned_dev->dev_id) < 0) {
1138 perror("assigned_dev_enable_msix: assign irq");
1139 return;
1140 }
1141 }
1142 assigned_dev->intx_route.mode = PCI_INTX_DISABLED;
1143 assigned_dev->intx_route.irq = -1;
1144 assigned_dev->assigned_irq_type = ASSIGNED_IRQ_MSIX;
1145 } else {
1146 Error *local_err = NULL;
1147
1148 assign_intx(assigned_dev, &local_err);
1149 if (local_err) {
1150 error_report_err(local_err);
1151 }
1152 }
1153}
1154
1155static uint32_t assigned_dev_pci_read_config(PCIDevice *pci_dev,
1156 uint32_t address, int len)
1157{
1158 AssignedDevice *assigned_dev = PCI_ASSIGN(pci_dev);
1159 uint32_t virt_val = pci_default_read_config(pci_dev, address, len);
1160 uint32_t real_val, emulate_mask, full_emulation_mask;
1161
1162 emulate_mask = 0;
1163 memcpy(&emulate_mask, assigned_dev->emulate_config_read + address, len);
1164 emulate_mask = le32_to_cpu(emulate_mask);
1165
1166 full_emulation_mask = 0xffffffff >> (32 - len * 8);
1167
1168 if (emulate_mask != full_emulation_mask) {
1169 real_val = assigned_dev_pci_read(pci_dev, address, len);
1170 return (virt_val & emulate_mask) | (real_val & ~emulate_mask);
1171 } else {
1172 return virt_val;
1173 }
1174}
1175
1176static void assigned_dev_pci_write_config(PCIDevice *pci_dev, uint32_t address,
1177 uint32_t val, int len)
1178{
1179 AssignedDevice *assigned_dev = PCI_ASSIGN(pci_dev);
1180 uint16_t old_cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1181 uint32_t emulate_mask, full_emulation_mask;
1182 int ret;
1183
1184 pci_default_write_config(pci_dev, address, val, len);
1185
1186 if (kvm_has_intx_set_mask() &&
1187 range_covers_byte(address, len, PCI_COMMAND + 1)) {
1188 bool intx_masked = (pci_get_word(pci_dev->config + PCI_COMMAND) &
1189 PCI_COMMAND_INTX_DISABLE);
1190
1191 if (intx_masked != !!(old_cmd & PCI_COMMAND_INTX_DISABLE)) {
1192 ret = kvm_device_intx_set_mask(kvm_state, assigned_dev->dev_id,
1193 intx_masked);
1194 if (ret) {
1195 perror("assigned_dev_pci_write_config: set intx mask");
1196 }
1197 }
1198 }
1199 if (assigned_dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
1200 if (range_covers_byte(address, len,
1201 pci_dev->msi_cap + PCI_MSI_FLAGS)) {
1202 assigned_dev_update_msi(pci_dev);
1203 } else if (ranges_overlap(address, len,
1204 pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 6)) {
1205 assigned_dev_update_msi_msg(pci_dev);
1206 }
1207 }
1208 if (assigned_dev->cap.available & ASSIGNED_DEVICE_CAP_MSIX) {
1209 if (range_covers_byte(address, len,
1210 pci_dev->msix_cap + PCI_MSIX_FLAGS + 1)) {
1211 assigned_dev_update_msix(pci_dev);
1212 }
1213 }
1214
1215 emulate_mask = 0;
1216 memcpy(&emulate_mask, assigned_dev->emulate_config_write + address, len);
1217 emulate_mask = le32_to_cpu(emulate_mask);
1218
1219 full_emulation_mask = 0xffffffff >> (32 - len * 8);
1220
1221 if (emulate_mask != full_emulation_mask) {
1222 if (emulate_mask) {
1223 val &= ~emulate_mask;
1224 val |= assigned_dev_pci_read(pci_dev, address, len) & emulate_mask;
1225 }
1226 assigned_dev_pci_write(pci_dev, address, val, len);
1227 }
1228}
1229
1230static void assigned_dev_setup_cap_read(AssignedDevice *dev, uint32_t offset,
1231 uint32_t len)
1232{
1233 assigned_dev_direct_config_read(dev, offset, len);
1234 assigned_dev_emulate_config_read(dev, offset + PCI_CAP_LIST_NEXT, 1);
1235}
1236
1237static int assigned_device_pci_cap_init(PCIDevice *pci_dev, Error **errp)
1238{
1239 AssignedDevice *dev = PCI_ASSIGN(pci_dev);
1240 PCIRegion *pci_region = dev->real_device.regions;
1241 int ret, pos;
1242 Error *local_err = NULL;
1243
1244
1245 pci_set_byte(pci_dev->config + PCI_CAPABILITY_LIST, 0);
1246 pci_set_word(pci_dev->config + PCI_STATUS,
1247 pci_get_word(pci_dev->config + PCI_STATUS) &
1248 ~PCI_STATUS_CAP_LIST);
1249
1250
1251
1252 pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSI, 0);
1253 if (pos != 0 && kvm_check_extension(kvm_state, KVM_CAP_ASSIGN_DEV_IRQ)) {
1254 verify_irqchip_in_kernel(&local_err);
1255 if (local_err) {
1256 error_propagate(errp, local_err);
1257 return -ENOTSUP;
1258 }
1259 dev->cap.available |= ASSIGNED_DEVICE_CAP_MSI;
1260
1261 ret = pci_add_capability2(pci_dev, PCI_CAP_ID_MSI, pos, 10,
1262 &local_err);
1263 if (ret < 0) {
1264 error_propagate(errp, local_err);
1265 return ret;
1266 }
1267 pci_dev->msi_cap = pos;
1268
1269 pci_set_word(pci_dev->config + pos + PCI_MSI_FLAGS,
1270 pci_get_word(pci_dev->config + pos + PCI_MSI_FLAGS) &
1271 PCI_MSI_FLAGS_QMASK);
1272 pci_set_long(pci_dev->config + pos + PCI_MSI_ADDRESS_LO, 0);
1273 pci_set_word(pci_dev->config + pos + PCI_MSI_DATA_32, 0);
1274
1275
1276 pci_set_word(pci_dev->wmask + pos + PCI_MSI_FLAGS,
1277 PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
1278 pci_set_long(pci_dev->wmask + pos + PCI_MSI_ADDRESS_LO, 0xfffffffc);
1279 pci_set_word(pci_dev->wmask + pos + PCI_MSI_DATA_32, 0xffff);
1280 }
1281
1282 pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSIX, 0);
1283 if (pos != 0 && kvm_device_msix_supported(kvm_state)) {
1284 int bar_nr;
1285 uint32_t msix_table_entry;
1286 uint16_t msix_max;
1287
1288 verify_irqchip_in_kernel(&local_err);
1289 if (local_err) {
1290 error_propagate(errp, local_err);
1291 return -ENOTSUP;
1292 }
1293 dev->cap.available |= ASSIGNED_DEVICE_CAP_MSIX;
1294 ret = pci_add_capability2(pci_dev, PCI_CAP_ID_MSIX, pos, 12,
1295 &local_err);
1296 if (ret < 0) {
1297 error_propagate(errp, local_err);
1298 return ret;
1299 }
1300 pci_dev->msix_cap = pos;
1301
1302 msix_max = (pci_get_word(pci_dev->config + pos + PCI_MSIX_FLAGS) &
1303 PCI_MSIX_FLAGS_QSIZE) + 1;
1304 msix_max = MIN(msix_max, KVM_MAX_MSIX_PER_DEV);
1305 pci_set_word(pci_dev->config + pos + PCI_MSIX_FLAGS, msix_max - 1);
1306
1307
1308 pci_set_word(pci_dev->wmask + pos + PCI_MSIX_FLAGS,
1309 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
1310
1311 msix_table_entry = pci_get_long(pci_dev->config + pos + PCI_MSIX_TABLE);
1312 bar_nr = msix_table_entry & PCI_MSIX_FLAGS_BIRMASK;
1313 msix_table_entry &= ~PCI_MSIX_FLAGS_BIRMASK;
1314 dev->msix_table_addr = pci_region[bar_nr].base_addr + msix_table_entry;
1315 dev->msix_max = msix_max;
1316 }
1317
1318
1319 pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_PM, 0);
1320 if (pos) {
1321 uint16_t pmc;
1322
1323 ret = pci_add_capability2(pci_dev, PCI_CAP_ID_PM, pos, PCI_PM_SIZEOF,
1324 &local_err);
1325 if (ret < 0) {
1326 error_propagate(errp, local_err);
1327 return ret;
1328 }
1329
1330 assigned_dev_setup_cap_read(dev, pos, PCI_PM_SIZEOF);
1331
1332 pmc = pci_get_word(pci_dev->config + pos + PCI_CAP_FLAGS);
1333 pmc &= (PCI_PM_CAP_VER_MASK | PCI_PM_CAP_DSI);
1334 pci_set_word(pci_dev->config + pos + PCI_CAP_FLAGS, pmc);
1335
1336
1337
1338 pci_set_word(pci_dev->config + pos + PCI_PM_CTRL,
1339 PCI_PM_CTRL_NO_SOFT_RESET);
1340
1341 pci_set_byte(pci_dev->config + pos + PCI_PM_PPB_EXTENSIONS, 0);
1342 pci_set_byte(pci_dev->config + pos + PCI_PM_DATA_REGISTER, 0);
1343 }
1344
1345 pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_EXP, 0);
1346 if (pos) {
1347 uint8_t version, size = 0;
1348 uint16_t type, devctl, lnksta;
1349 uint32_t devcap, lnkcap;
1350
1351 version = pci_get_byte(pci_dev->config + pos + PCI_EXP_FLAGS);
1352 version &= PCI_EXP_FLAGS_VERS;
1353 if (version == 1) {
1354 size = 0x14;
1355 } else if (version == 2) {
1356
1357
1358
1359
1360
1361
1362 size = MIN(0x3c, PCI_CONFIG_SPACE_SIZE - pos);
1363 if (size < 0x34) {
1364 error_setg(errp, "Invalid size PCIe cap-id 0x%x",
1365 PCI_CAP_ID_EXP);
1366 return -EINVAL;
1367 } else if (size != 0x3c) {
1368 error_report("WARNING, %s: PCIe cap-id 0x%x has "
1369 "non-standard size 0x%x; std size should be 0x3c",
1370 __func__, PCI_CAP_ID_EXP, size);
1371 }
1372 } else if (version == 0) {
1373 uint16_t vid, did;
1374 vid = pci_get_word(pci_dev->config + PCI_VENDOR_ID);
1375 did = pci_get_word(pci_dev->config + PCI_DEVICE_ID);
1376 if (vid == PCI_VENDOR_ID_INTEL && did == 0x10ed) {
1377
1378
1379
1380
1381 size = 0x3c;
1382 }
1383 }
1384
1385 if (size == 0) {
1386 error_setg(errp, "Unsupported PCI express capability version %d",
1387 version);
1388 return -EINVAL;
1389 }
1390
1391 ret = pci_add_capability2(pci_dev, PCI_CAP_ID_EXP, pos, size,
1392 &local_err);
1393 if (ret < 0) {
1394 error_propagate(errp, local_err);
1395 return ret;
1396 }
1397
1398 assigned_dev_setup_cap_read(dev, pos, size);
1399
1400 type = pci_get_word(pci_dev->config + pos + PCI_EXP_FLAGS);
1401 type = (type & PCI_EXP_FLAGS_TYPE) >> 4;
1402 if (type != PCI_EXP_TYPE_ENDPOINT &&
1403 type != PCI_EXP_TYPE_LEG_END && type != PCI_EXP_TYPE_RC_END) {
1404 error_setg(errp, "Device assignment only supports endpoint "
1405 "assignment, device type %d", type);
1406 return -EINVAL;
1407 }
1408
1409
1410
1411
1412
1413 devcap = pci_get_long(pci_dev->config + pos + PCI_EXP_DEVCAP);
1414 devcap &= ~PCI_EXP_DEVCAP_FLR;
1415 pci_set_long(pci_dev->config + pos + PCI_EXP_DEVCAP, devcap);
1416
1417
1418
1419
1420
1421 devctl = pci_get_word(pci_dev->config + pos + PCI_EXP_DEVCTL);
1422 devctl = (devctl & (PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_PAYLOAD)) |
1423 PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
1424 pci_set_word(pci_dev->config + pos + PCI_EXP_DEVCTL, devctl);
1425 devctl = PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_AUX_PME;
1426 pci_set_word(pci_dev->wmask + pos + PCI_EXP_DEVCTL, ~devctl);
1427
1428
1429 pci_set_word(pci_dev->config + pos + PCI_EXP_DEVSTA, 0);
1430
1431
1432 lnkcap = pci_get_long(pci_dev->config + pos + PCI_EXP_LNKCAP);
1433 lnkcap &= (PCI_EXP_LNKCAP_SLS | PCI_EXP_LNKCAP_MLW |
1434 PCI_EXP_LNKCAP_ASPMS | PCI_EXP_LNKCAP_L0SEL |
1435 PCI_EXP_LNKCAP_L1EL);
1436 pci_set_long(pci_dev->config + pos + PCI_EXP_LNKCAP, lnkcap);
1437
1438
1439
1440
1441 lnksta = pci_get_word(pci_dev->config + pos + PCI_EXP_LNKSTA);
1442 lnksta &= (PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW);
1443 pci_set_word(pci_dev->config + pos + PCI_EXP_LNKSTA, lnksta);
1444
1445 if (version >= 2) {
1446
1447 pci_set_long(pci_dev->config + pos + PCI_EXP_SLTCAP, 0);
1448 pci_set_word(pci_dev->config + pos + PCI_EXP_SLTCTL, 0);
1449 pci_set_word(pci_dev->config + pos + PCI_EXP_SLTSTA, 0);
1450
1451
1452 pci_set_word(pci_dev->config + pos + PCI_EXP_RTCTL, 0);
1453 pci_set_word(pci_dev->config + pos + PCI_EXP_RTCAP, 0);
1454 pci_set_long(pci_dev->config + pos + PCI_EXP_RTSTA, 0);
1455
1456
1457
1458 }
1459 }
1460
1461 pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_PCIX, 0);
1462 if (pos) {
1463 uint16_t cmd;
1464 uint32_t status;
1465
1466
1467 ret = pci_add_capability2(pci_dev, PCI_CAP_ID_PCIX, pos, 8,
1468 &local_err);
1469 if (ret < 0) {
1470 error_propagate(errp, local_err);
1471 return ret;
1472 }
1473
1474 assigned_dev_setup_cap_read(dev, pos, 8);
1475
1476
1477 cmd = pci_get_word(pci_dev->config + pos + PCI_X_CMD);
1478 cmd &= (PCI_X_CMD_DPERR_E | PCI_X_CMD_ERO | PCI_X_CMD_MAX_READ |
1479 PCI_X_CMD_MAX_SPLIT);
1480 pci_set_word(pci_dev->config + pos + PCI_X_CMD, cmd);
1481
1482
1483
1484 status = pci_get_long(pci_dev->config + pos + PCI_X_STATUS);
1485 status &= ~(PCI_X_STATUS_BUS | PCI_X_STATUS_DEVFN);
1486 status |= pci_requester_id(pci_dev);
1487 status &= ~(PCI_X_STATUS_SPL_DISC | PCI_X_STATUS_UNX_SPL |
1488 PCI_X_STATUS_SPL_ERR);
1489 pci_set_long(pci_dev->config + pos + PCI_X_STATUS, status);
1490 }
1491
1492 pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_VPD, 0);
1493 if (pos) {
1494
1495 ret = pci_add_capability2(pci_dev, PCI_CAP_ID_VPD, pos, 8,
1496 &local_err);
1497 if (ret < 0) {
1498 error_propagate(errp, local_err);
1499 return ret;
1500 }
1501
1502 assigned_dev_setup_cap_read(dev, pos, 8);
1503
1504
1505 assigned_dev_direct_config_write(dev, pos + 2, 6);
1506 }
1507
1508
1509 for (pos = 0; (pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_VNDR, pos));
1510 pos += PCI_CAP_LIST_NEXT) {
1511 uint8_t len = pci_get_byte(pci_dev->config + pos + PCI_CAP_FLAGS);
1512
1513 ret = pci_add_capability2(pci_dev, PCI_CAP_ID_VNDR, pos, len,
1514 &local_err);
1515 if (ret < 0) {
1516 error_propagate(errp, local_err);
1517 return ret;
1518 }
1519
1520 assigned_dev_setup_cap_read(dev, pos, len);
1521
1522
1523 assigned_dev_direct_config_write(dev, pos + 2, len - 2);
1524 }
1525
1526
1527
1528 if ((pci_get_word(pci_dev->config + PCI_STATUS) & PCI_STATUS_CAP_LIST) !=
1529 (assigned_dev_pci_read_byte(pci_dev, PCI_STATUS) &
1530 PCI_STATUS_CAP_LIST)) {
1531 dev->emulate_config_read[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1532 }
1533
1534 return 0;
1535}
1536
1537static uint64_t
1538assigned_dev_msix_mmio_read(void *opaque, hwaddr addr,
1539 unsigned size)
1540{
1541 AssignedDevice *adev = opaque;
1542 uint64_t val;
1543
1544 memcpy(&val, (void *)((uint8_t *)adev->msix_table + addr), size);
1545
1546 return val;
1547}
1548
1549static void assigned_dev_msix_mmio_write(void *opaque, hwaddr addr,
1550 uint64_t val, unsigned size)
1551{
1552 AssignedDevice *adev = opaque;
1553 PCIDevice *pdev = &adev->dev;
1554 uint16_t ctrl;
1555 MSIXTableEntry orig;
1556 int i = addr >> 4;
1557
1558 if (i >= adev->msix_max) {
1559 return;
1560 }
1561
1562 ctrl = pci_get_word(pdev->config + pdev->msix_cap + PCI_MSIX_FLAGS);
1563
1564 DEBUG("write to MSI-X table offset 0x%lx, val 0x%lx\n", addr, val);
1565
1566 if (ctrl & PCI_MSIX_FLAGS_ENABLE) {
1567 orig = adev->msix_table[i];
1568 }
1569
1570 memcpy((uint8_t *)adev->msix_table + addr, &val, size);
1571
1572 if (ctrl & PCI_MSIX_FLAGS_ENABLE) {
1573 MSIXTableEntry *entry = &adev->msix_table[i];
1574
1575 if (!assigned_dev_msix_masked(&orig) &&
1576 assigned_dev_msix_masked(entry)) {
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588 } else if (assigned_dev_msix_masked(&orig) &&
1589 !assigned_dev_msix_masked(entry)) {
1590
1591 if (i >= adev->msi_virq_nr || adev->msi_virq[i] < 0) {
1592
1593 assigned_dev_update_msix(pdev);
1594 return;
1595 } else {
1596
1597 MSIMessage msg;
1598 int ret;
1599
1600 msg.address = entry->addr_lo |
1601 ((uint64_t)entry->addr_hi << 32);
1602 msg.data = entry->data;
1603
1604 ret = kvm_irqchip_update_msi_route(kvm_state,
1605 adev->msi_virq[i], msg,
1606 pdev);
1607 if (ret) {
1608 error_report("Error updating irq routing entry (%d)", ret);
1609 }
1610 }
1611 }
1612 }
1613}
1614
1615static const MemoryRegionOps assigned_dev_msix_mmio_ops = {
1616 .read = assigned_dev_msix_mmio_read,
1617 .write = assigned_dev_msix_mmio_write,
1618 .endianness = DEVICE_NATIVE_ENDIAN,
1619 .valid = {
1620 .min_access_size = 4,
1621 .max_access_size = 8,
1622 },
1623 .impl = {
1624 .min_access_size = 4,
1625 .max_access_size = 8,
1626 },
1627};
1628
1629static void assigned_dev_msix_reset(AssignedDevice *dev)
1630{
1631 MSIXTableEntry *entry;
1632 int i;
1633
1634 if (!dev->msix_table) {
1635 return;
1636 }
1637
1638 memset(dev->msix_table, 0, MSIX_PAGE_SIZE);
1639
1640 for (i = 0, entry = dev->msix_table; i < dev->msix_max; i++, entry++) {
1641 entry->ctrl = cpu_to_le32(0x1);
1642 }
1643}
1644
1645static void assigned_dev_register_msix_mmio(AssignedDevice *dev, Error **errp)
1646{
1647 dev->msix_table = mmap(NULL, MSIX_PAGE_SIZE, PROT_READ|PROT_WRITE,
1648 MAP_ANONYMOUS|MAP_PRIVATE, 0, 0);
1649 if (dev->msix_table == MAP_FAILED) {
1650 error_setg_errno(errp, errno, "failed to allocate msix_table");
1651 dev->msix_table = NULL;
1652 return;
1653 }
1654
1655 assigned_dev_msix_reset(dev);
1656
1657 memory_region_init_io(&dev->mmio, OBJECT(dev), &assigned_dev_msix_mmio_ops,
1658 dev, "assigned-dev-msix", MSIX_PAGE_SIZE);
1659}
1660
1661static void assigned_dev_unregister_msix_mmio(AssignedDevice *dev)
1662{
1663 if (!dev->msix_table) {
1664 return;
1665 }
1666
1667 if (munmap(dev->msix_table, MSIX_PAGE_SIZE) == -1) {
1668 error_report("error unmapping msix_table! %s", strerror(errno));
1669 }
1670 dev->msix_table = NULL;
1671}
1672
1673static const VMStateDescription vmstate_assigned_device = {
1674 .name = "pci-assign",
1675 .unmigratable = 1,
1676};
1677
1678static void reset_assigned_device(DeviceState *dev)
1679{
1680 PCIDevice *pci_dev = PCI_DEVICE(dev);
1681 AssignedDevice *adev = PCI_ASSIGN(pci_dev);
1682 char reset_file[64];
1683 const char reset[] = "1";
1684 int fd, ret;
1685
1686
1687
1688
1689
1690
1691
1692
1693 if (adev->assigned_irq_type == ASSIGNED_IRQ_MSIX) {
1694 uint16_t ctrl = pci_get_word(pci_dev->config +
1695 pci_dev->msix_cap + PCI_MSIX_FLAGS);
1696
1697 pci_set_word(pci_dev->config + pci_dev->msix_cap + PCI_MSIX_FLAGS,
1698 ctrl & ~PCI_MSIX_FLAGS_ENABLE);
1699 assigned_dev_update_msix(pci_dev);
1700 } else if (adev->assigned_irq_type == ASSIGNED_IRQ_MSI) {
1701 uint8_t ctrl = pci_get_byte(pci_dev->config +
1702 pci_dev->msi_cap + PCI_MSI_FLAGS);
1703
1704 pci_set_byte(pci_dev->config + pci_dev->msi_cap + PCI_MSI_FLAGS,
1705 ctrl & ~PCI_MSI_FLAGS_ENABLE);
1706 assigned_dev_update_msi(pci_dev);
1707 }
1708
1709 snprintf(reset_file, sizeof(reset_file),
1710 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/reset",
1711 adev->host.domain, adev->host.bus, adev->host.slot,
1712 adev->host.function);
1713
1714
1715
1716
1717
1718
1719
1720 fd = open(reset_file, O_WRONLY);
1721 if (fd != -1) {
1722 ret = write(fd, reset, strlen(reset));
1723 (void)ret;
1724 close(fd);
1725 }
1726
1727
1728
1729
1730
1731 assigned_dev_pci_write_config(pci_dev, PCI_COMMAND, 0, 1);
1732}
1733
1734static void assigned_realize(struct PCIDevice *pci_dev, Error **errp)
1735{
1736 AssignedDevice *dev = PCI_ASSIGN(pci_dev);
1737 uint8_t e_intx;
1738 int r;
1739 Error *local_err = NULL;
1740
1741 if (!kvm_enabled()) {
1742 error_setg(&local_err, "pci-assign requires KVM support");
1743 goto exit_with_error;
1744 }
1745
1746 if (!dev->host.domain && !dev->host.bus && !dev->host.slot &&
1747 !dev->host.function) {
1748 error_setg(&local_err, "no host device specified");
1749 goto exit_with_error;
1750 }
1751
1752
1753
1754
1755
1756 assigned_dev_emulate_config_read(dev, 0, PCI_CONFIG_SPACE_SIZE);
1757 assigned_dev_direct_config_read(dev, PCI_STATUS, 2);
1758 assigned_dev_direct_config_read(dev, PCI_REVISION_ID, 1);
1759 assigned_dev_direct_config_read(dev, PCI_CLASS_PROG, 3);
1760 assigned_dev_direct_config_read(dev, PCI_CACHE_LINE_SIZE, 1);
1761 assigned_dev_direct_config_read(dev, PCI_LATENCY_TIMER, 1);
1762 assigned_dev_direct_config_read(dev, PCI_BIST, 1);
1763 assigned_dev_direct_config_read(dev, PCI_CARDBUS_CIS, 4);
1764 assigned_dev_direct_config_read(dev, PCI_SUBSYSTEM_VENDOR_ID, 2);
1765 assigned_dev_direct_config_read(dev, PCI_SUBSYSTEM_ID, 2);
1766 assigned_dev_direct_config_read(dev, PCI_CAPABILITY_LIST + 1, 7);
1767 assigned_dev_direct_config_read(dev, PCI_MIN_GNT, 1);
1768 assigned_dev_direct_config_read(dev, PCI_MAX_LAT, 1);
1769 memcpy(dev->emulate_config_write, dev->emulate_config_read,
1770 sizeof(dev->emulate_config_read));
1771
1772 get_real_device(dev, &local_err);
1773 if (local_err) {
1774 goto out;
1775 }
1776
1777 if (assigned_device_pci_cap_init(pci_dev, &local_err) < 0) {
1778 goto out;
1779 }
1780
1781
1782 if (dev->cap.available & ASSIGNED_DEVICE_CAP_MSIX) {
1783 assigned_dev_register_msix_mmio(dev, &local_err);
1784 if (local_err) {
1785 goto out;
1786 }
1787 }
1788
1789
1790 assigned_dev_register_regions(dev->real_device.regions,
1791 dev->real_device.region_number, dev,
1792 &local_err);
1793 if (local_err) {
1794 goto out;
1795 }
1796
1797
1798 e_intx = dev->dev.config[PCI_INTERRUPT_PIN] - 1;
1799 dev->intpin = e_intx;
1800 dev->intx_route.mode = PCI_INTX_DISABLED;
1801 dev->intx_route.irq = -1;
1802
1803
1804 assign_device(dev, &local_err);
1805 if (local_err) {
1806 goto out;
1807 }
1808
1809
1810 r = assign_intx(dev, &local_err);
1811 if (r < 0) {
1812 goto assigned_out;
1813 }
1814
1815 assigned_dev_load_option_rom(dev);
1816
1817 return;
1818
1819assigned_out:
1820 deassign_device(dev);
1821
1822out:
1823 free_assigned_device(dev);
1824
1825exit_with_error:
1826 assert(local_err);
1827 error_propagate(errp, local_err);
1828}
1829
1830static void assigned_exitfn(struct PCIDevice *pci_dev)
1831{
1832 AssignedDevice *dev = PCI_ASSIGN(pci_dev);
1833
1834 deassign_device(dev);
1835 free_assigned_device(dev);
1836}
1837
1838static void assigned_dev_instance_init(Object *obj)
1839{
1840 PCIDevice *pci_dev = PCI_DEVICE(obj);
1841 AssignedDevice *d = PCI_ASSIGN(pci_dev);
1842
1843 device_add_bootindex_property(obj, &d->bootindex,
1844 "bootindex", NULL,
1845 &pci_dev->qdev, NULL);
1846}
1847
1848static Property assigned_dev_properties[] = {
1849 DEFINE_PROP_PCI_HOST_DEVADDR("host", AssignedDevice, host),
1850 DEFINE_PROP_BIT("prefer_msi", AssignedDevice, features,
1851 ASSIGNED_DEVICE_PREFER_MSI_BIT, false),
1852 DEFINE_PROP_BIT("share_intx", AssignedDevice, features,
1853 ASSIGNED_DEVICE_SHARE_INTX_BIT, true),
1854 DEFINE_PROP_STRING("configfd", AssignedDevice, configfd_name),
1855 DEFINE_PROP_END_OF_LIST(),
1856};
1857
1858static void assign_class_init(ObjectClass *klass, void *data)
1859{
1860 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1861 DeviceClass *dc = DEVICE_CLASS(klass);
1862
1863 k->realize = assigned_realize;
1864 k->exit = assigned_exitfn;
1865 k->config_read = assigned_dev_pci_read_config;
1866 k->config_write = assigned_dev_pci_write_config;
1867 dc->props = assigned_dev_properties;
1868 dc->vmsd = &vmstate_assigned_device;
1869 dc->reset = reset_assigned_device;
1870 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
1871 dc->desc = "KVM-based PCI passthrough";
1872}
1873
1874static const TypeInfo assign_info = {
1875 .name = TYPE_PCI_ASSIGN,
1876 .parent = TYPE_PCI_DEVICE,
1877 .instance_size = sizeof(AssignedDevice),
1878 .class_init = assign_class_init,
1879 .instance_init = assigned_dev_instance_init,
1880};
1881
1882static void assign_register_types(void)
1883{
1884 type_register_static(&assign_info);
1885}
1886
1887type_init(assign_register_types)
1888
1889static void assigned_dev_load_option_rom(AssignedDevice *dev)
1890{
1891 int size = 0;
1892
1893 pci_assign_dev_load_option_rom(&dev->dev, OBJECT(dev), &size,
1894 dev->host.domain, dev->host.bus,
1895 dev->host.slot, dev->host.function);
1896
1897 if (!size) {
1898 error_report("pci-assign: Invalid ROM.");
1899 }
1900}
1901
