LXR qemu/hw/pci-host/gpex.c

   1/*
   2 * QEMU Generic PCI Express Bridge Emulation
   3 *
   4 * Copyright (C) 2015 Alexander Graf <agraf@suse.de>
   5 *
   6 * Code loosely based on q35.c.
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a copy
   9 * of this software and associated documentation files (the "Software"), to deal
  10 * in the Software without restriction, including without limitation the rights
  11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12 * copies of the Software, and to permit persons to whom the Software is
  13 * furnished to do so, subject to the following conditions:
  14 *
  15 * The above copyright notice and this permission notice shall be included in
  16 * all copies or substantial portions of the Software.
  17 *
  18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24 * THE SOFTWARE.
  25 *
  26 * Check out these documents for more information on the device:
  27 *
  28 * http://www.kernel.org/doc/Documentation/devicetree/bindings/pci/host-generic-pci.txt
  29 * http://www.firmware.org/1275/practice/imap/imap0_9d.pdf
  30 */
  31#include "hw/hw.h"
  32#include "hw/pci-host/gpex.h"
  33
  34/****************************************************************************
  35 * GPEX host
  36 */
  37
  38static void gpex_set_irq(void *opaque, int irq_num, int level)
  39{
  40    GPEXHost *s = opaque;
  41
  42    qemu_set_irq(s->irq[irq_num], level);
  43}
  44
  45static void gpex_host_realize(DeviceState *dev, Error **errp)
  46{
  47    PCIHostState *pci = PCI_HOST_BRIDGE(dev);
  48    GPEXHost *s = GPEX_HOST(dev);
  49    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  50    PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
  51    int i;
  52
  53    pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
  54    memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX);
  55    memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024);
  56
  57    sysbus_init_mmio(sbd, &pex->mmio);
  58    sysbus_init_mmio(sbd, &s->io_mmio);
  59    sysbus_init_mmio(sbd, &s->io_ioport);
  60    for (i = 0; i < GPEX_NUM_IRQS; i++) {
  61        sysbus_init_irq(sbd, &s->irq[i]);
  62    }
  63
  64    pci->bus = pci_register_bus(dev, "pcie.0", gpex_set_irq,
  65                                pci_swizzle_map_irq_fn, s, &s->io_mmio,
  66                                &s->io_ioport, 0, 4, TYPE_PCIE_BUS);
  67
  68    qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
  69    qdev_init_nofail(DEVICE(&s->gpex_root));
  70}
  71
  72static const char *gpex_host_root_bus_path(PCIHostState *host_bridge,
  73                                          PCIBus *rootbus)
  74{
  75    return "0000:00";
  76}
  77
  78static void gpex_host_class_init(ObjectClass *klass, void *data)
  79{
  80    DeviceClass *dc = DEVICE_CLASS(klass);
  81    PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
  82
  83    hc->root_bus_path = gpex_host_root_bus_path;
  84    dc->realize = gpex_host_realize;
  85    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
  86    dc->fw_name = "pci";
  87}
  88
  89static void gpex_host_initfn(Object *obj)
  90{
  91    GPEXHost *s = GPEX_HOST(obj);
  92    GPEXRootState *root = &s->gpex_root;
  93
  94    object_initialize(root, sizeof(*root), TYPE_GPEX_ROOT_DEVICE);
  95    object_property_add_child(obj, "gpex_root", OBJECT(root), NULL);
  96    qdev_prop_set_uint32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
  97    qdev_prop_set_bit(DEVICE(root), "multifunction", false);
  98}
  99
 100static const TypeInfo gpex_host_info = {
 101    .name       = TYPE_GPEX_HOST,
 102    .parent     = TYPE_PCIE_HOST_BRIDGE,
 103    .instance_size = sizeof(GPEXHost),
 104    .instance_init = gpex_host_initfn,
 105    .class_init = gpex_host_class_init,
 106};
 107
 108/****************************************************************************
 109 * GPEX Root D0:F0
 110 */
 111
 112static const VMStateDescription vmstate_gpex_root = {
 113    .name = "gpex_root",
 114    .version_id = 1,
 115    .minimum_version_id = 1,
 116    .fields = (VMStateField[]) {
 117        VMSTATE_PCI_DEVICE(parent_obj, GPEXRootState),
 118        VMSTATE_END_OF_LIST()
 119    }
 120};
 121
 122static void gpex_root_class_init(ObjectClass *klass, void *data)
 123{
 124    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 125    DeviceClass *dc = DEVICE_CLASS(klass);
 126
 127    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 128    dc->desc = "QEMU generic PCIe host bridge";
 129    dc->vmsd = &vmstate_gpex_root;
 130    k->vendor_id = PCI_VENDOR_ID_REDHAT;
 131    k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_HOST;
 132    k->revision = 0;
 133    k->class_id = PCI_CLASS_BRIDGE_HOST;
 134    /*
 135     * PCI-facing part of the host bridge, not usable without the
 136     * host-facing part, which can't be device_add'ed, yet.
 137     */
 138    dc->cannot_instantiate_with_device_add_yet = true;
 139}
 140
 141static const TypeInfo gpex_root_info = {
 142    .name = TYPE_GPEX_ROOT_DEVICE,
 143    .parent = TYPE_PCI_DEVICE,
 144    .instance_size = sizeof(GPEXRootState),
 145    .class_init = gpex_root_class_init,
 146};
 147
 148static void gpex_register(void)
 149{
 150    type_register_static(&gpex_root_info);
 151    type_register_static(&gpex_host_info);
 152}
 153
 154type_init(gpex_register)
 155