LXR qemu/include/exec/cpu-all.h

   1/*
   2 * defines common to all virtual CPUs
   3 *
   4 *  Copyright (c) 2003 Fabrice Bellard
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19#ifndef CPU_ALL_H
  20#define CPU_ALL_H
  21
  22#include "qemu-common.h"
  23#include "exec/cpu-common.h"
  24#include "exec/memory.h"
  25#include "qemu/thread.h"
  26#include "qom/cpu.h"
  27#include "qemu/rcu.h"
  28
  29#define EXCP_INTERRUPT  0x10000 /* async interruption */
  30#define EXCP_HLT        0x10001 /* hlt instruction reached */
  31#define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
  32#define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
  33#define EXCP_YIELD      0x10004 /* cpu wants to yield timeslice to another */
  34
  35/* some important defines:
  36 *
  37 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
  38 * memory accesses.
  39 *
  40 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
  41 * otherwise little endian.
  42 *
  43 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
  44 *
  45 * TARGET_WORDS_BIGENDIAN : same for target cpu
  46 */
  47
  48#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
  49#define BSWAP_NEEDED
  50#endif
  51
  52#ifdef BSWAP_NEEDED
  53
  54static inline uint16_t tswap16(uint16_t s)
  55{
  56    return bswap16(s);
  57}
  58
  59static inline uint32_t tswap32(uint32_t s)
  60{
  61    return bswap32(s);
  62}
  63
  64static inline uint64_t tswap64(uint64_t s)
  65{
  66    return bswap64(s);
  67}
  68
  69static inline void tswap16s(uint16_t *s)
  70{
  71    *s = bswap16(*s);
  72}
  73
  74static inline void tswap32s(uint32_t *s)
  75{
  76    *s = bswap32(*s);
  77}
  78
  79static inline void tswap64s(uint64_t *s)
  80{
  81    *s = bswap64(*s);
  82}
  83
  84#else
  85
  86static inline uint16_t tswap16(uint16_t s)
  87{
  88    return s;
  89}
  90
  91static inline uint32_t tswap32(uint32_t s)
  92{
  93    return s;
  94}
  95
  96static inline uint64_t tswap64(uint64_t s)
  97{
  98    return s;
  99}
 100
 101static inline void tswap16s(uint16_t *s)
 102{
 103}
 104
 105static inline void tswap32s(uint32_t *s)
 106{
 107}
 108
 109static inline void tswap64s(uint64_t *s)
 110{
 111}
 112
 113#endif
 114
 115#if TARGET_LONG_SIZE == 4
 116#define tswapl(s) tswap32(s)
 117#define tswapls(s) tswap32s((uint32_t *)(s))
 118#define bswaptls(s) bswap32s(s)
 119#else
 120#define tswapl(s) tswap64(s)
 121#define tswapls(s) tswap64s((uint64_t *)(s))
 122#define bswaptls(s) bswap64s(s)
 123#endif
 124
 125/* Target-endianness CPU memory access functions. These fit into the
 126 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
 127 */
 128#if defined(TARGET_WORDS_BIGENDIAN)
 129#define lduw_p(p) lduw_be_p(p)
 130#define ldsw_p(p) ldsw_be_p(p)
 131#define ldl_p(p) ldl_be_p(p)
 132#define ldq_p(p) ldq_be_p(p)
 133#define ldfl_p(p) ldfl_be_p(p)
 134#define ldfq_p(p) ldfq_be_p(p)
 135#define stw_p(p, v) stw_be_p(p, v)
 136#define stl_p(p, v) stl_be_p(p, v)
 137#define stq_p(p, v) stq_be_p(p, v)
 138#define stfl_p(p, v) stfl_be_p(p, v)
 139#define stfq_p(p, v) stfq_be_p(p, v)
 140#else
 141#define lduw_p(p) lduw_le_p(p)
 142#define ldsw_p(p) ldsw_le_p(p)
 143#define ldl_p(p) ldl_le_p(p)
 144#define ldq_p(p) ldq_le_p(p)
 145#define ldfl_p(p) ldfl_le_p(p)
 146#define ldfq_p(p) ldfq_le_p(p)
 147#define stw_p(p, v) stw_le_p(p, v)
 148#define stl_p(p, v) stl_le_p(p, v)
 149#define stq_p(p, v) stq_le_p(p, v)
 150#define stfl_p(p, v) stfl_le_p(p, v)
 151#define stfq_p(p, v) stfq_le_p(p, v)
 152#endif
 153
 154/* MMU memory access macros */
 155
 156#if defined(CONFIG_USER_ONLY)
 157#include <assert.h>
 158#include "exec/user/abitypes.h"
 159
 160/* On some host systems the guest address space is reserved on the host.
 161 * This allows the guest address space to be offset to a convenient location.
 162 */
 163extern unsigned long guest_base;
 164extern int have_guest_base;
 165extern unsigned long reserved_va;
 166
 167#define GUEST_ADDR_MAX (reserved_va ? reserved_va : \
 168                                    (1ul << TARGET_VIRT_ADDR_SPACE_BITS) - 1)
 169#endif
 170
 171/* page related stuff */
 172
 173#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
 174#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
 175#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
 176
 177/* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
 178 * when intptr_t is 32-bit and we are aligning a long long.
 179 */
 180extern uintptr_t qemu_real_host_page_size;
 181extern intptr_t qemu_real_host_page_mask;
 182extern uintptr_t qemu_host_page_size;
 183extern intptr_t qemu_host_page_mask;
 184
 185#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
 186#define REAL_HOST_PAGE_ALIGN(addr) (((addr) + qemu_real_host_page_size - 1) & \
 187                                    qemu_real_host_page_mask)
 188
 189/* same as PROT_xxx */
 190#define PAGE_READ      0x0001
 191#define PAGE_WRITE     0x0002
 192#define PAGE_EXEC      0x0004
 193#define PAGE_BITS      (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
 194#define PAGE_VALID     0x0008
 195/* original state of the write flag (used when tracking self-modifying
 196   code */
 197#define PAGE_WRITE_ORG 0x0010
 198#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
 199/* FIXME: Code that sets/uses this is broken and needs to go away.  */
 200#define PAGE_RESERVED  0x0020
 201#endif
 202
 203#if defined(CONFIG_USER_ONLY)
 204void page_dump(FILE *f);
 205
 206typedef int (*walk_memory_regions_fn)(void *, target_ulong,
 207                                      target_ulong, unsigned long);
 208int walk_memory_regions(void *, walk_memory_regions_fn);
 209
 210int page_get_flags(target_ulong address);
 211void page_set_flags(target_ulong start, target_ulong end, int flags);
 212int page_check_range(target_ulong start, target_ulong len, int flags);
 213#endif
 214
 215CPUArchState *cpu_copy(CPUArchState *env);
 216
 217/* Flags for use in ENV->INTERRUPT_PENDING.
 218
 219   The numbers assigned here are non-sequential in order to preserve
 220   binary compatibility with the vmstate dump.  Bit 0 (0x0001) was
 221   previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
 222   the vmstate dump.  */
 223
 224/* External hardware interrupt pending.  This is typically used for
 225   interrupts from devices.  */
 226#define CPU_INTERRUPT_HARD        0x0002
 227
 228/* Exit the current TB.  This is typically used when some system-level device
 229   makes some change to the memory mapping.  E.g. the a20 line change.  */
 230#define CPU_INTERRUPT_EXITTB      0x0004
 231
 232/* Halt the CPU.  */
 233#define CPU_INTERRUPT_HALT        0x0020
 234
 235/* Debug event pending.  */
 236#define CPU_INTERRUPT_DEBUG       0x0080
 237
 238/* Reset signal.  */
 239#define CPU_INTERRUPT_RESET       0x0400
 240
 241/* Several target-specific external hardware interrupts.  Each target/cpu.h
 242   should define proper names based on these defines.  */
 243#define CPU_INTERRUPT_TGT_EXT_0   0x0008
 244#define CPU_INTERRUPT_TGT_EXT_1   0x0010
 245#define CPU_INTERRUPT_TGT_EXT_2   0x0040
 246#define CPU_INTERRUPT_TGT_EXT_3   0x0200
 247#define CPU_INTERRUPT_TGT_EXT_4   0x1000
 248
 249/* Several target-specific internal interrupts.  These differ from the
 250   preceding target-specific interrupts in that they are intended to
 251   originate from within the cpu itself, typically in response to some
 252   instruction being executed.  These, therefore, are not masked while
 253   single-stepping within the debugger.  */
 254#define CPU_INTERRUPT_TGT_INT_0   0x0100
 255#define CPU_INTERRUPT_TGT_INT_1   0x0800
 256#define CPU_INTERRUPT_TGT_INT_2   0x2000
 257
 258/* First unused bit: 0x4000.  */
 259
 260/* The set of all bits that should be masked when single-stepping.  */
 261#define CPU_INTERRUPT_SSTEP_MASK \
 262    (CPU_INTERRUPT_HARD          \
 263     | CPU_INTERRUPT_TGT_EXT_0   \
 264     | CPU_INTERRUPT_TGT_EXT_1   \
 265     | CPU_INTERRUPT_TGT_EXT_2   \
 266     | CPU_INTERRUPT_TGT_EXT_3   \
 267     | CPU_INTERRUPT_TGT_EXT_4)
 268
 269#if !defined(CONFIG_USER_ONLY)
 270
 271/* Flags stored in the low bits of the TLB virtual address.  These are
 272   defined so that fast path ram access is all zeros.  */
 273/* Zero if TLB entry is valid.  */
 274#define TLB_INVALID_MASK   (1 << 3)
 275/* Set if TLB entry references a clean RAM page.  The iotlb entry will
 276   contain the page physical address.  */
 277#define TLB_NOTDIRTY    (1 << 4)
 278/* Set if TLB entry is an IO callback.  */
 279#define TLB_MMIO        (1 << 5)
 280
 281void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
 282void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf);
 283#endif /* !CONFIG_USER_ONLY */
 284
 285int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
 286                        uint8_t *buf, int len, int is_write);
 287
 288#endif /* CPU_ALL_H */
 289