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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/mips/mips.h"
28#include "hw/mips/cpudevs.h"
29#include "hw/i386/pc.h"
30#include "hw/char/serial.h"
31#include "hw/isa/isa.h"
32#include "hw/block/fdc.h"
33#include "sysemu/sysemu.h"
34#include "sysemu/arch_init.h"
35#include "hw/boards.h"
36#include "net/net.h"
37#include "hw/scsi/esp.h"
38#include "hw/mips/bios.h"
39#include "hw/loader.h"
40#include "hw/timer/mc146818rtc.h"
41#include "hw/timer/i8254.h"
42#include "hw/audio/pcspk.h"
43#include "sysemu/block-backend.h"
44#include "hw/sysbus.h"
45#include "exec/address-spaces.h"
46#include "sysemu/qtest.h"
47#include "qemu/error-report.h"
48#include "qemu/help_option.h"
49
50enum jazz_model_e
51{
52 JAZZ_MAGNUM,
53 JAZZ_PICA61,
54};
55
56static void main_cpu_reset(void *opaque)
57{
58 MIPSCPU *cpu = opaque;
59
60 cpu_reset(CPU(cpu));
61}
62
63static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
64{
65 uint8_t val;
66 address_space_read(&address_space_memory, 0x90000071,
67 MEMTXATTRS_UNSPECIFIED, &val, 1);
68 return val;
69}
70
71static void rtc_write(void *opaque, hwaddr addr,
72 uint64_t val, unsigned size)
73{
74 uint8_t buf = val & 0xff;
75 address_space_write(&address_space_memory, 0x90000071,
76 MEMTXATTRS_UNSPECIFIED, &buf, 1);
77}
78
79static const MemoryRegionOps rtc_ops = {
80 .read = rtc_read,
81 .write = rtc_write,
82 .endianness = DEVICE_NATIVE_ENDIAN,
83};
84
85static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
86 unsigned size)
87{
88
89
90 return 0xff;
91}
92
93static void dma_dummy_write(void *opaque, hwaddr addr,
94 uint64_t val, unsigned size)
95{
96
97
98}
99
100static const MemoryRegionOps dma_dummy_ops = {
101 .read = dma_dummy_read,
102 .write = dma_dummy_write,
103 .endianness = DEVICE_NATIVE_ENDIAN,
104};
105
106#define MAGNUM_BIOS_SIZE_MAX 0x7e000
107#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
108
109static CPUUnassignedAccess real_do_unassigned_access;
110static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
111 bool is_write, bool is_exec,
112 int opaque, unsigned size)
113{
114 if (!is_exec) {
115
116 return;
117 }
118 (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
119}
120
121static void mips_jazz_init(MachineState *machine,
122 enum jazz_model_e jazz_model)
123{
124 MemoryRegion *address_space = get_system_memory();
125 const char *cpu_model = machine->cpu_model;
126 char *filename;
127 int bios_size, n;
128 MIPSCPU *cpu;
129 CPUClass *cc;
130 CPUMIPSState *env;
131 qemu_irq *i8259;
132 rc4030_dma *dmas;
133 MemoryRegion *rc4030_dma_mr;
134 MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
135 MemoryRegion *isa_io = g_new(MemoryRegion, 1);
136 MemoryRegion *rtc = g_new(MemoryRegion, 1);
137 MemoryRegion *i8042 = g_new(MemoryRegion, 1);
138 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
139 NICInfo *nd;
140 DeviceState *dev, *rc4030;
141 SysBusDevice *sysbus;
142 ISABus *isa_bus;
143 ISADevice *pit;
144 DriveInfo *fds[MAX_FD];
145 qemu_irq esp_reset, dma_enable;
146 MemoryRegion *ram = g_new(MemoryRegion, 1);
147 MemoryRegion *bios = g_new(MemoryRegion, 1);
148 MemoryRegion *bios2 = g_new(MemoryRegion, 1);
149
150
151 if (cpu_model == NULL) {
152 cpu_model = "R4000";
153 }
154 cpu = cpu_mips_init(cpu_model);
155 if (cpu == NULL) {
156 fprintf(stderr, "Unable to find CPU definition\n");
157 exit(1);
158 }
159 env = &cpu->env;
160 qemu_register_reset(main_cpu_reset, cpu);
161
162
163
164
165
166
167
168
169 cc = CPU_GET_CLASS(cpu);
170 real_do_unassigned_access = cc->do_unassigned_access;
171 cc->do_unassigned_access = mips_jazz_do_unassigned_access;
172
173
174 memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
175 machine->ram_size);
176 memory_region_add_subregion(address_space, 0, ram);
177
178 memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
179 &error_fatal);
180 vmstate_register_ram_global(bios);
181 memory_region_set_readonly(bios, true);
182 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
183 0, MAGNUM_BIOS_SIZE);
184 memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
185 memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
186
187
188 if (bios_name == NULL)
189 bios_name = BIOS_FILENAME;
190 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
191 if (filename) {
192 bios_size = load_image_targphys(filename, 0xfff00000LL,
193 MAGNUM_BIOS_SIZE);
194 g_free(filename);
195 } else {
196 bios_size = -1;
197 }
198 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
199 error_report("Could not load MIPS bios '%s'", bios_name);
200 exit(1);
201 }
202
203
204 cpu_mips_irq_init_cpu(env);
205 cpu_mips_clock_init(env);
206
207
208 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
209 sysbus = SYS_BUS_DEVICE(rc4030);
210 sysbus_connect_irq(sysbus, 0, env->irq[6]);
211 sysbus_connect_irq(sysbus, 1, env->irq[3]);
212 memory_region_add_subregion(address_space, 0x80000000,
213 sysbus_mmio_get_region(sysbus, 0));
214 memory_region_add_subregion(address_space, 0xf0000000,
215 sysbus_mmio_get_region(sysbus, 1));
216 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
217 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
218
219
220 memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
221 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
222 memory_region_add_subregion(address_space, 0x90000000, isa_io);
223 memory_region_add_subregion(address_space, 0x91000000, isa_mem);
224 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
225
226
227 i8259 = i8259_init(isa_bus, env->irq[4]);
228 isa_bus_irqs(isa_bus, i8259);
229 DMA_init(isa_bus, 0);
230 pit = pit_init(isa_bus, 0x40, 0, NULL);
231 pcspk_init(isa_bus, pit);
232
233
234 switch (jazz_model) {
235 case JAZZ_MAGNUM:
236 dev = qdev_create(NULL, "sysbus-g364");
237 qdev_init_nofail(dev);
238 sysbus = SYS_BUS_DEVICE(dev);
239 sysbus_mmio_map(sysbus, 0, 0x60080000);
240 sysbus_mmio_map(sysbus, 1, 0x40000000);
241 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
242 {
243
244 MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
245 memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
246 &error_fatal);
247 vmstate_register_ram_global(rom_mr);
248 memory_region_set_readonly(rom_mr, true);
249 uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
250 memory_region_add_subregion(address_space, 0x60000000, rom_mr);
251 rom[0] = 0x10;
252 }
253 break;
254 case JAZZ_PICA61:
255 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
256 break;
257 default:
258 break;
259 }
260
261
262 for (n = 0; n < nb_nics; n++) {
263 nd = &nd_table[n];
264 if (!nd->model)
265 nd->model = g_strdup("dp83932");
266 if (strcmp(nd->model, "dp83932") == 0) {
267 qemu_check_nic_model(nd, "dp83932");
268
269 dev = qdev_create(NULL, "dp8393x");
270 qdev_set_nic_properties(dev, nd);
271 qdev_prop_set_uint8(dev, "it_shift", 2);
272 qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
273 qdev_init_nofail(dev);
274 sysbus = SYS_BUS_DEVICE(dev);
275 sysbus_mmio_map(sysbus, 0, 0x80001000);
276 sysbus_mmio_map(sysbus, 1, 0x8000b000);
277 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
278 break;
279 } else if (is_help_option(nd->model)) {
280 fprintf(stderr, "qemu: Supported NICs: dp83932\n");
281 exit(1);
282 } else {
283 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
284 exit(1);
285 }
286 }
287
288
289 esp_init(0x80002000, 0,
290 rc4030_dma_read, rc4030_dma_write, dmas[0],
291 qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
292
293
294 if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
295 fprintf(stderr, "qemu: too many floppy drives\n");
296 exit(1);
297 }
298 for (n = 0; n < MAX_FD; n++) {
299 fds[n] = drive_get(IF_FLOPPY, 0, n);
300 }
301
302 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
303
304
305 rtc_init(isa_bus, 1980, NULL);
306 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
307 memory_region_add_subregion(address_space, 0x80004000, rtc);
308
309
310 i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
311 i8042, 0x1000, 0x1);
312 memory_region_add_subregion(address_space, 0x80005000, i8042);
313
314
315 if (serial_hds[0]) {
316 serial_mm_init(address_space, 0x80006000, 0,
317 qdev_get_gpio_in(rc4030, 8), 8000000/16,
318 serial_hds[0], DEVICE_NATIVE_ENDIAN);
319 }
320 if (serial_hds[1]) {
321 serial_mm_init(address_space, 0x80007000, 0,
322 qdev_get_gpio_in(rc4030, 9), 8000000/16,
323 serial_hds[1], DEVICE_NATIVE_ENDIAN);
324 }
325
326
327 if (parallel_hds[0])
328 parallel_mm_init(address_space, 0x80008000, 0,
329 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
330
331
332
333
334 dev = qdev_create(NULL, "ds1225y");
335 qdev_init_nofail(dev);
336 sysbus = SYS_BUS_DEVICE(dev);
337 sysbus_mmio_map(sysbus, 0, 0x80009000);
338
339
340 sysbus_create_simple("jazz-led", 0x8000f000, NULL);
341}
342
343static
344void mips_magnum_init(MachineState *machine)
345{
346 mips_jazz_init(machine, JAZZ_MAGNUM);
347}
348
349static
350void mips_pica61_init(MachineState *machine)
351{
352 mips_jazz_init(machine, JAZZ_PICA61);
353}
354
355static void mips_magnum_class_init(ObjectClass *oc, void *data)
356{
357 MachineClass *mc = MACHINE_CLASS(oc);
358
359 mc->desc = "MIPS Magnum";
360 mc->init = mips_magnum_init;
361 mc->block_default_type = IF_SCSI;
362}
363
364static const TypeInfo mips_magnum_type = {
365 .name = MACHINE_TYPE_NAME("magnum"),
366 .parent = TYPE_MACHINE,
367 .class_init = mips_magnum_class_init,
368};
369
370static void mips_pica61_class_init(ObjectClass *oc, void *data)
371{
372 MachineClass *mc = MACHINE_CLASS(oc);
373
374 mc->desc = "Acer Pica 61";
375 mc->init = mips_pica61_init;
376 mc->block_default_type = IF_SCSI;
377}
378
379static const TypeInfo mips_pica61_type = {
380 .name = MACHINE_TYPE_NAME("pica61"),
381 .parent = TYPE_MACHINE,
382 .class_init = mips_pica61_class_init,
383};
384
385static void mips_jazz_machine_init(void)
386{
387 type_register_static(&mips_magnum_type);
388 type_register_static(&mips_pica61_type);
389}
390
391type_init(mips_jazz_machine_init)
392
