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22#include "qemu/osdep.h"
23#include "qapi/error.h"
24#include "cpu.h"
25#include "qemu-common.h"
26#include "migration/vmstate.h"
27
28
29static void superh_cpu_set_pc(CPUState *cs, vaddr value)
30{
31 SuperHCPU *cpu = SUPERH_CPU(cs);
32
33 cpu->env.pc = value;
34}
35
36static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
37{
38 SuperHCPU *cpu = SUPERH_CPU(cs);
39
40 cpu->env.pc = tb->pc;
41 cpu->env.flags = tb->flags;
42}
43
44static bool superh_cpu_has_work(CPUState *cs)
45{
46 return cs->interrupt_request & CPU_INTERRUPT_HARD;
47}
48
49
50static void superh_cpu_reset(CPUState *s)
51{
52 SuperHCPU *cpu = SUPERH_CPU(s);
53 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
54 CPUSH4State *env = &cpu->env;
55
56 scc->parent_reset(s);
57
58 memset(env, 0, offsetof(CPUSH4State, id));
59 tlb_flush(s, 1);
60
61 env->pc = 0xA0000000;
62#if defined(CONFIG_USER_ONLY)
63 env->fpscr = FPSCR_PR;
64 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
65#else
66 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
67 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
68 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO;
69 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
70 set_flush_to_zero(1, &env->fp_status);
71#endif
72 set_default_nan_mode(1, &env->fp_status);
73}
74
75static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
76{
77 info->mach = bfd_mach_sh4;
78 info->print_insn = print_insn_sh;
79}
80
81typedef struct SuperHCPUListState {
82 fprintf_function cpu_fprintf;
83 FILE *file;
84} SuperHCPUListState;
85
86
87static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
88{
89 ObjectClass *class_a = (ObjectClass *)a;
90 ObjectClass *class_b = (ObjectClass *)b;
91 const char *name_a, *name_b;
92
93 name_a = object_class_get_name(class_a);
94 name_b = object_class_get_name(class_b);
95 return strcmp(name_a, name_b);
96}
97
98static void superh_cpu_list_entry(gpointer data, gpointer user_data)
99{
100 ObjectClass *oc = data;
101 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
102 SuperHCPUListState *s = user_data;
103
104 (*s->cpu_fprintf)(s->file, "%s\n",
105 scc->name);
106}
107
108void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
109{
110 SuperHCPUListState s = {
111 .cpu_fprintf = cpu_fprintf,
112 .file = f,
113 };
114 GSList *list;
115
116 list = object_class_get_list(TYPE_SUPERH_CPU, false);
117 list = g_slist_sort(list, superh_cpu_list_compare);
118 g_slist_foreach(list, superh_cpu_list_entry, &s);
119 g_slist_free(list);
120}
121
122static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
123{
124 const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
125 const char *name = b;
126
127 return strcasecmp(scc->name, name);
128}
129
130static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
131{
132 ObjectClass *oc;
133 GSList *list, *item;
134
135 if (cpu_model == NULL) {
136 return NULL;
137 }
138 if (strcasecmp(cpu_model, "any") == 0) {
139 return object_class_by_name(TYPE_SH7750R_CPU);
140 }
141
142 oc = object_class_by_name(cpu_model);
143 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
144 && !object_class_is_abstract(oc)) {
145 return oc;
146 }
147
148 oc = NULL;
149 list = object_class_get_list(TYPE_SUPERH_CPU, false);
150 item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
151 if (item != NULL) {
152 oc = item->data;
153 }
154 g_slist_free(list);
155 return oc;
156}
157
158SuperHCPU *cpu_sh4_init(const char *cpu_model)
159{
160 return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
161}
162
163static void sh7750r_cpu_initfn(Object *obj)
164{
165 SuperHCPU *cpu = SUPERH_CPU(obj);
166 CPUSH4State *env = &cpu->env;
167
168 env->id = SH_CPU_SH7750R;
169 env->features = SH_FEATURE_BCR3_AND_BCR4;
170}
171
172static void sh7750r_class_init(ObjectClass *oc, void *data)
173{
174 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
175
176 scc->name = "SH7750R";
177 scc->pvr = 0x00050000;
178 scc->prr = 0x00000100;
179 scc->cvr = 0x00110000;
180}
181
182static const TypeInfo sh7750r_type_info = {
183 .name = TYPE_SH7750R_CPU,
184 .parent = TYPE_SUPERH_CPU,
185 .class_init = sh7750r_class_init,
186 .instance_init = sh7750r_cpu_initfn,
187};
188
189static void sh7751r_cpu_initfn(Object *obj)
190{
191 SuperHCPU *cpu = SUPERH_CPU(obj);
192 CPUSH4State *env = &cpu->env;
193
194 env->id = SH_CPU_SH7751R;
195 env->features = SH_FEATURE_BCR3_AND_BCR4;
196}
197
198static void sh7751r_class_init(ObjectClass *oc, void *data)
199{
200 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
201
202 scc->name = "SH7751R";
203 scc->pvr = 0x04050005;
204 scc->prr = 0x00000113;
205 scc->cvr = 0x00110000;
206}
207
208static const TypeInfo sh7751r_type_info = {
209 .name = TYPE_SH7751R_CPU,
210 .parent = TYPE_SUPERH_CPU,
211 .class_init = sh7751r_class_init,
212 .instance_init = sh7751r_cpu_initfn,
213};
214
215static void sh7785_cpu_initfn(Object *obj)
216{
217 SuperHCPU *cpu = SUPERH_CPU(obj);
218 CPUSH4State *env = &cpu->env;
219
220 env->id = SH_CPU_SH7785;
221 env->features = SH_FEATURE_SH4A;
222}
223
224static void sh7785_class_init(ObjectClass *oc, void *data)
225{
226 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
227
228 scc->name = "SH7785";
229 scc->pvr = 0x10300700;
230 scc->prr = 0x00000200;
231 scc->cvr = 0x71440211;
232}
233
234static const TypeInfo sh7785_type_info = {
235 .name = TYPE_SH7785_CPU,
236 .parent = TYPE_SUPERH_CPU,
237 .class_init = sh7785_class_init,
238 .instance_init = sh7785_cpu_initfn,
239};
240
241static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
242{
243 CPUState *cs = CPU(dev);
244 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
245
246 cpu_reset(cs);
247 qemu_init_vcpu(cs);
248
249 scc->parent_realize(dev, errp);
250}
251
252static void superh_cpu_initfn(Object *obj)
253{
254 CPUState *cs = CPU(obj);
255 SuperHCPU *cpu = SUPERH_CPU(obj);
256 CPUSH4State *env = &cpu->env;
257
258 cs->env_ptr = env;
259 cpu_exec_init(cs, &error_abort);
260
261 env->movcal_backup_tail = &(env->movcal_backup);
262
263 if (tcg_enabled()) {
264 sh4_translate_init();
265 }
266}
267
268static const VMStateDescription vmstate_sh_cpu = {
269 .name = "cpu",
270 .unmigratable = 1,
271};
272
273static void superh_cpu_class_init(ObjectClass *oc, void *data)
274{
275 DeviceClass *dc = DEVICE_CLASS(oc);
276 CPUClass *cc = CPU_CLASS(oc);
277 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
278
279 scc->parent_realize = dc->realize;
280 dc->realize = superh_cpu_realizefn;
281
282 scc->parent_reset = cc->reset;
283 cc->reset = superh_cpu_reset;
284
285 cc->class_by_name = superh_cpu_class_by_name;
286 cc->has_work = superh_cpu_has_work;
287 cc->do_interrupt = superh_cpu_do_interrupt;
288 cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
289 cc->dump_state = superh_cpu_dump_state;
290 cc->set_pc = superh_cpu_set_pc;
291 cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
292 cc->gdb_read_register = superh_cpu_gdb_read_register;
293 cc->gdb_write_register = superh_cpu_gdb_write_register;
294#ifdef CONFIG_USER_ONLY
295 cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
296#else
297 cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
298#endif
299 cc->disas_set_info = superh_cpu_disas_set_info;
300
301 cc->gdb_num_core_regs = 59;
302
303 dc->vmsd = &vmstate_sh_cpu;
304
305
306
307
308
309
310 dc->cannot_destroy_with_object_finalize_yet = true;
311}
312
313static const TypeInfo superh_cpu_type_info = {
314 .name = TYPE_SUPERH_CPU,
315 .parent = TYPE_CPU,
316 .instance_size = sizeof(SuperHCPU),
317 .instance_init = superh_cpu_initfn,
318 .abstract = true,
319 .class_size = sizeof(SuperHCPUClass),
320 .class_init = superh_cpu_class_init,
321};
322
323static void superh_cpu_register_types(void)
324{
325 type_register_static(&superh_cpu_type_info);
326 type_register_static(&sh7750r_type_info);
327 type_register_static(&sh7751r_type_info);
328 type_register_static(&sh7785_type_info);
329}
330
331type_init(superh_cpu_register_types)
332
