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21#include "qemu/osdep.h"
22#include "disas/bfd.h"
23#define BFD_DEFAULT_TARGET_SIZE 64
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47
48struct powerpc_opcode
49{
50
51 const char *name;
52
53
54
55 unsigned long opcode;
56
57
58
59
60
61 unsigned long mask;
62
63
64
65
66 unsigned long flags;
67
68
69
70
71 unsigned char operands[8];
72};
73
74
75
76
77extern const struct powerpc_opcode powerpc_opcodes[];
78extern const int powerpc_num_opcodes;
79
80
81
82
83#define PPC_OPCODE_PPC 1
84
85
86#define PPC_OPCODE_POWER 2
87
88
89#define PPC_OPCODE_POWER2 4
90
91
92#define PPC_OPCODE_32 8
93
94
95#define PPC_OPCODE_64 0x10
96
97
98
99
100#define PPC_OPCODE_601 0x20
101
102
103
104#define PPC_OPCODE_COMMON 0x40
105
106
107
108#define PPC_OPCODE_ANY 0x80
109
110
111#define PPC_OPCODE_64_BRIDGE 0x100
112
113
114#define PPC_OPCODE_ALTIVEC 0x200
115
116
117#define PPC_OPCODE_403 0x400
118
119
120#define PPC_OPCODE_BOOKE 0x800
121
122
123#define PPC_OPCODE_BOOKE64 0x1000
124
125
126#define PPC_OPCODE_440 0x2000
127
128
129#define PPC_OPCODE_POWER4 0x4000
130
131
132#define PPC_OPCODE_NOPOWER4 0x8000
133
134
135#define PPC_OPCODE_CLASSIC 0x10000
136
137
138#define PPC_OPCODE_SPE 0x20000
139
140
141#define PPC_OPCODE_ISEL 0x40000
142
143
144#define PPC_OPCODE_EFS 0x80000
145
146
147#define PPC_OPCODE_BRLOCK 0x100000
148
149
150#define PPC_OPCODE_PMR 0x200000
151
152
153#define PPC_OPCODE_CACHELCK 0x400000
154
155
156#define PPC_OPCODE_RFMCI 0x800000
157
158
159#define PPC_OPCODE_POWER5 0x1000000
160
161
162#define PPC_OPCODE_E300 0x2000000
163
164
165#define PPC_OPCODE_POWER6 0x4000000
166
167
168#define PPC_OPCODE_CELL 0x8000000
169
170
171#define PPC_OP(i) (((i) >> 26) & 0x3f)
172
173
174
175struct powerpc_operand
176{
177
178 unsigned int bitm;
179
180
181
182
183 int shift;
184
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197
198
199
200 unsigned long (*insert)
201 (unsigned long instruction, long op, int dialect, const char **errmsg);
202
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209
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216
217
218
219 long (*extract) (unsigned long instruction, int dialect, int *invalid);
220
221
222 unsigned long flags;
223};
224
225
226
227
228extern const struct powerpc_operand powerpc_operands[];
229extern const unsigned int num_powerpc_operands;
230
231
232
233
234#define PPC_OPERAND_SIGNED (0x1)
235
236
237
238
239
240#define PPC_OPERAND_SIGNOPT (0x2)
241
242
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245
246
247
248#define PPC_OPERAND_FAKE (0x4)
249
250
251
252
253
254
255#define PPC_OPERAND_PARENS (0x8)
256
257
258
259
260
261
262
263
264#define PPC_OPERAND_CR (0x10)
265
266
267
268#define PPC_OPERAND_GPR (0x20)
269
270
271#define PPC_OPERAND_GPR_0 (0x40)
272
273
274
275#define PPC_OPERAND_FPR (0x80)
276
277
278
279#define PPC_OPERAND_RELATIVE (0x100)
280
281
282
283#define PPC_OPERAND_ABSOLUTE (0x200)
284
285
286
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288
289
290
291#define PPC_OPERAND_OPTIONAL (0x400)
292
293
294
295
296
297
298
299#define PPC_OPERAND_NEXT (0x800)
300
301
302
303
304
305
306#define PPC_OPERAND_NEGATIVE (0x1000)
307
308
309
310#define PPC_OPERAND_VR (0x2000)
311
312
313#define PPC_OPERAND_DS (0x4000)
314
315
316#define PPC_OPERAND_DQ (0x8000)
317
318
319#define PPC_OPERAND_PLUS1 (0x10000)
320
321
322
323
324
325struct powerpc_macro
326{
327
328 const char *name;
329
330
331 unsigned int operands;
332
333
334
335
336 unsigned long flags;
337
338
339
340
341 const char *format;
342};
343
344extern const struct powerpc_macro powerpc_macros[];
345extern const int powerpc_num_macros;
346
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380
381static unsigned long insert_bat (unsigned long, long, int, const char **);
382static long extract_bat (unsigned long, int, int *);
383static unsigned long insert_bba (unsigned long, long, int, const char **);
384static long extract_bba (unsigned long, int, int *);
385static unsigned long insert_bdm (unsigned long, long, int, const char **);
386static long extract_bdm (unsigned long, int, int *);
387static unsigned long insert_bdp (unsigned long, long, int, const char **);
388static long extract_bdp (unsigned long, int, int *);
389static unsigned long insert_bo (unsigned long, long, int, const char **);
390static long extract_bo (unsigned long, int, int *);
391static unsigned long insert_boe (unsigned long, long, int, const char **);
392static long extract_boe (unsigned long, int, int *);
393static unsigned long insert_fxm (unsigned long, long, int, const char **);
394static long extract_fxm (unsigned long, int, int *);
395static unsigned long insert_mbe (unsigned long, long, int, const char **);
396static long extract_mbe (unsigned long, int, int *);
397static unsigned long insert_mb6 (unsigned long, long, int, const char **);
398static long extract_mb6 (unsigned long, int, int *);
399static long extract_nb (unsigned long, int, int *);
400static unsigned long insert_nsi (unsigned long, long, int, const char **);
401static long extract_nsi (unsigned long, int, int *);
402static unsigned long insert_ral (unsigned long, long, int, const char **);
403static unsigned long insert_ram (unsigned long, long, int, const char **);
404static unsigned long insert_raq (unsigned long, long, int, const char **);
405static unsigned long insert_ras (unsigned long, long, int, const char **);
406static unsigned long insert_rbs (unsigned long, long, int, const char **);
407static long extract_rbs (unsigned long, int, int *);
408static unsigned long insert_sh6 (unsigned long, long, int, const char **);
409static long extract_sh6 (unsigned long, int, int *);
410static unsigned long insert_spr (unsigned long, long, int, const char **);
411static long extract_spr (unsigned long, int, int *);
412static unsigned long insert_sprg (unsigned long, long, int, const char **);
413static long extract_sprg (unsigned long, int, int *);
414static unsigned long insert_tbr (unsigned long, long, int, const char **);
415static long extract_tbr (unsigned long, int, int *);
416
417
418
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425
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427
428const struct powerpc_operand powerpc_operands[] =
429{
430
431
432#define UNUSED 0
433 { 0, 0, NULL, NULL, 0 },
434
435
436#define BA UNUSED + 1
437
438#define BI BA
439#define BI_MASK (0x1f << 16)
440 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
441
442
443
444#define BAT BA + 1
445 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
446
447
448#define BB BAT + 1
449#define BB_MASK (0x1f << 11)
450 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
451
452
453
454#define BBA BB + 1
455 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
456
457
458
459#define BD BBA + 1
460 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
461
462
463
464#define BDA BD + 1
465 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
466
467
468
469#define BDM BDA + 1
470 { 0xfffc, 0, insert_bdm, extract_bdm,
471 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
472
473
474
475#define BDMA BDM + 1
476 { 0xfffc, 0, insert_bdm, extract_bdm,
477 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
478
479
480
481#define BDP BDMA + 1
482 { 0xfffc, 0, insert_bdp, extract_bdp,
483 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
484
485
486
487#define BDPA BDP + 1
488 { 0xfffc, 0, insert_bdp, extract_bdp,
489 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
490
491
492#define BF BDPA + 1
493
494#define CRFD BF
495 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
496
497
498#define BFF BF + 1
499 { 0x7, 23, NULL, NULL, 0 },
500
501
502
503#define OBF BFF + 1
504 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
505
506
507#define BFA OBF + 1
508 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
509
510
511
512#define BO BFA + 1
513#define BO_MASK (0x1f << 21)
514 { 0x1f, 21, insert_bo, extract_bo, 0 },
515
516
517
518#define BOE BO + 1
519 { 0x1e, 21, insert_boe, extract_boe, 0 },
520
521#define BH BOE + 1
522 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
523
524
525#define BT BH + 1
526 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
527
528
529
530
531
532#define CR BT + 1
533 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
534
535
536#define CRB CR + 1
537
538#define MB CRB
539#define MB_MASK (0x1f << 6)
540 { 0x1f, 6, NULL, NULL, 0 },
541
542
543#define CRFS CRB + 1
544 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
545
546
547#define CT CRFS + 1
548
549#define MO CT
550 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
551
552
553
554
555#define D CT + 1
556 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
557
558
559
560#define DE D + 1
561 { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
562
563
564
565#define DES DE + 1
566 { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
567
568
569
570#define DQ DES + 1
571 { 0xfff0, 0, NULL, NULL,
572 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
573
574
575
576#undef DS
577#define DS DQ + 1
578 { 0xfffc, 0, NULL, NULL,
579 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
580
581
582#define E DS + 1
583 { 0x1, 15, NULL, NULL, 0 },
584
585
586#define FL1 E + 1
587
588#define U FL1
589 { 0xf, 12, NULL, NULL, 0 },
590
591
592#define FL2 FL1 + 1
593 { 0x7, 2, NULL, NULL, 0 },
594
595
596#define FLM FL2 + 1
597 { 0xff, 17, NULL, NULL, 0 },
598
599
600#define FRA FLM + 1
601#define FRA_MASK (0x1f << 16)
602 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
603
604
605#define FRB FRA + 1
606#define FRB_MASK (0x1f << 11)
607 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
608
609
610#define FRC FRB + 1
611#define FRC_MASK (0x1f << 6)
612 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
613
614
615
616#define FRS FRC + 1
617#define FRT FRS
618 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
619
620
621#define FXM FRS + 1
622 { 0xff, 12, insert_fxm, extract_fxm, 0 },
623
624
625#define FXM4 FXM + 1
626 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
627
628
629#define L FXM4 + 1
630 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
631
632
633#define SVC_LEV L + 1
634 { 0x7f, 5, NULL, NULL, 0 },
635
636
637#define LEV SVC_LEV + 1
638 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
639
640
641
642#define LI LEV + 1
643 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
644
645
646
647#define LIA LI + 1
648 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
649
650
651#define LS LIA + 1
652 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
653
654
655#define ME LS + 1
656#define ME_MASK (0x1f << 1)
657 { 0x1f, 1, NULL, NULL, 0 },
658
659
660
661
662
663#define MBE ME + 1
664 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
665 { -1, 0, insert_mbe, extract_mbe, 0 },
666
667
668
669#define MB6 MBE + 2
670#define ME6 MB6
671#define MB6_MASK (0x3f << 5)
672 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
673
674
675
676#define NB MB6 + 1
677 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
678
679
680
681#define NSI NB + 1
682 { 0xffff, 0, insert_nsi, extract_nsi,
683 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
684
685
686#define RA NSI + 1
687#define RA_MASK (0x1f << 16)
688 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
689
690
691#define RA0 RA + 1
692 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
693
694
695
696#define RAQ RA0 + 1
697 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
698
699
700
701
702#define RAL RAQ + 1
703 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
704
705
706
707#define RAM RAL + 1
708 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
709
710
711
712
713#define RAS RAM + 1
714 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
715
716
717#define RAOPT RAS + 1
718 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
719
720
721#define RB RAOPT + 1
722#define RB_MASK (0x1f << 11)
723 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
724
725
726
727
728#define RBS RB + 1
729 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
730
731
732
733
734#define RS RBS + 1
735#define RT RS
736#define RT_MASK (0x1f << 21)
737 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
738
739
740
741#define RSQ RS + 1
742#define RTQ RSQ
743 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
744
745
746#define RSO RSQ + 1
747#define RTO RSO
748 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
749
750
751#define SH RSO + 1
752#define SH_MASK (0x1f << 11)
753
754#define EVUIMM SH
755 { 0x1f, 11, NULL, NULL, 0 },
756
757
758#define SH6 SH + 1
759#define SH6_MASK ((0x1f << 11) | (1 << 1))
760 { 0x3f, -1, insert_sh6, extract_sh6, 0 },
761
762
763#define SHO SH6 + 1
764 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
765
766
767#define SI SHO + 1
768 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
769
770
771
772#define SISIGNOPT SI + 1
773 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
774
775
776
777#define SPR SISIGNOPT + 1
778#define PMR SPR
779#define SPR_MASK (0x3ff << 11)
780 { 0x3ff, 11, insert_spr, extract_spr, 0 },
781
782
783#define SPRBAT SPR + 1
784#define SPRBAT_MASK (0x3 << 17)
785 { 0x3, 17, NULL, NULL, 0 },
786
787
788#define SPRG SPRBAT + 1
789 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
790
791
792#define SR SPRG + 1
793 { 0xf, 16, NULL, NULL, 0 },
794
795
796#define STRM SR + 1
797 { 0x3, 21, NULL, NULL, 0 },
798
799
800#define SV STRM + 1
801 { 0x3fff, 2, NULL, NULL, 0 },
802
803
804
805#define TBR SV + 1
806 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
807
808
809#define TO TBR + 1
810#define TO_MASK (0x1f << 21)
811 { 0x1f, 21, NULL, NULL, 0 },
812
813
814#define UI TO + 1
815 { 0xffff, 0, NULL, NULL, 0 },
816
817
818#define VA UI + 1
819 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
820
821
822#define VB VA + 1
823 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
824
825
826#define VC VB + 1
827 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
828
829
830#define VD VC + 1
831#define VS VD
832 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
833
834
835#define SIMM VD + 1
836 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
837
838
839#define UIMM SIMM + 1
840#define TE UIMM
841 { 0x1f, 16, NULL, NULL, 0 },
842
843
844#define SHB UIMM + 1
845 { 0xf, 6, NULL, NULL, 0 },
846
847
848#define EVUIMM_2 SHB + 1
849 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
850
851
852#define EVUIMM_4 EVUIMM_2 + 1
853 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
854
855
856#define EVUIMM_8 EVUIMM_4 + 1
857 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
858
859
860#define WS EVUIMM_8 + 1
861 { 0x7, 11, NULL, NULL, 0 },
862
863
864#define A_L WS + 1
865#define W A_L
866 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
867
868#define RMC A_L + 1
869 { 0x3, 9, NULL, NULL, 0 },
870
871#define R RMC + 1
872 { 0x1, 16, NULL, NULL, 0 },
873
874#define SP R + 1
875 { 0x3, 19, NULL, NULL, 0 },
876
877#define S SP + 1
878 { 0x1, 20, NULL, NULL, 0 },
879
880
881#define SH16 S + 1
882
883#define DCM SH16
884#define DGM DCM
885 { 0x3f, 10, NULL, NULL, 0 },
886
887
888#define EH SH16 + 1
889 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
890
891
892#define XFL_L EH + 1
893 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
894};
895
896const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
897 / sizeof (powerpc_operands[0]));
898
899
900
901
902
903
904
905
906
907static unsigned long
908insert_bat (unsigned long insn,
909 long value ATTRIBUTE_UNUSED,
910 int dialect ATTRIBUTE_UNUSED,
911 const char **errmsg ATTRIBUTE_UNUSED)
912{
913 return insn | (((insn >> 21) & 0x1f) << 16);
914}
915
916static long
917extract_bat (unsigned long insn,
918 int dialect ATTRIBUTE_UNUSED,
919 int *invalid)
920{
921 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
922 *invalid = 1;
923 return 0;
924}
925
926
927
928
929
930
931
932static unsigned long
933insert_bba (unsigned long insn,
934 long value ATTRIBUTE_UNUSED,
935 int dialect ATTRIBUTE_UNUSED,
936 const char **errmsg ATTRIBUTE_UNUSED)
937{
938 return insn | (((insn >> 16) & 0x1f) << 11);
939}
940
941static long
942extract_bba (unsigned long insn,
943 int dialect ATTRIBUTE_UNUSED,
944 int *invalid)
945{
946 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
947 *invalid = 1;
948 return 0;
949}
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968static unsigned long
969insert_bdm (unsigned long insn,
970 long value,
971 int dialect,
972 const char **errmsg ATTRIBUTE_UNUSED)
973{
974 if ((dialect & PPC_OPCODE_POWER4) == 0)
975 {
976 if ((value & 0x8000) != 0)
977 insn |= 1 << 21;
978 }
979 else
980 {
981 if ((insn & (0x14 << 21)) == (0x04 << 21))
982 insn |= 0x02 << 21;
983 else if ((insn & (0x14 << 21)) == (0x10 << 21))
984 insn |= 0x08 << 21;
985 }
986 return insn | (value & 0xfffc);
987}
988
989static long
990extract_bdm (unsigned long insn,
991 int dialect,
992 int *invalid)
993{
994 if ((dialect & PPC_OPCODE_POWER4) == 0)
995 {
996 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
997 *invalid = 1;
998 }
999 else
1000 {
1001 if ((insn & (0x17 << 21)) != (0x06 << 21)
1002 && (insn & (0x1d << 21)) != (0x18 << 21))
1003 *invalid = 1;
1004 }
1005
1006 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1007}
1008
1009
1010
1011
1012
1013static unsigned long
1014insert_bdp (unsigned long insn,
1015 long value,
1016 int dialect,
1017 const char **errmsg ATTRIBUTE_UNUSED)
1018{
1019 if ((dialect & PPC_OPCODE_POWER4) == 0)
1020 {
1021 if ((value & 0x8000) == 0)
1022 insn |= 1 << 21;
1023 }
1024 else
1025 {
1026 if ((insn & (0x14 << 21)) == (0x04 << 21))
1027 insn |= 0x03 << 21;
1028 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1029 insn |= 0x09 << 21;
1030 }
1031 return insn | (value & 0xfffc);
1032}
1033
1034static long
1035extract_bdp (unsigned long insn,
1036 int dialect,
1037 int *invalid)
1038{
1039 if ((dialect & PPC_OPCODE_POWER4) == 0)
1040 {
1041 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1042 *invalid = 1;
1043 }
1044 else
1045 {
1046 if ((insn & (0x17 << 21)) != (0x07 << 21)
1047 && (insn & (0x1d << 21)) != (0x19 << 21))
1048 *invalid = 1;
1049 }
1050
1051 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1052}
1053
1054
1055
1056static int
1057valid_bo (long value, int dialect, int extract)
1058{
1059 if ((dialect & PPC_OPCODE_POWER4) == 0)
1060 {
1061 int valid;
1062
1063
1064
1065
1066
1067
1068
1069
1070 switch (value & 0x14)
1071 {
1072 default:
1073 case 0:
1074 valid = 1;
1075 break;
1076 case 0x4:
1077 valid = (value & 0x2) == 0;
1078 break;
1079 case 0x10:
1080 valid = (value & 0x8) == 0;
1081 break;
1082 case 0x14:
1083 valid = value == 0x14;
1084 break;
1085 }
1086
1087 if (valid
1088 || (dialect & PPC_OPCODE_ANY) == 0
1089 || !extract)
1090 return valid;
1091 }
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105 if ((value & 0x14) == 0)
1106 return (value & 0x1) == 0;
1107 else if ((value & 0x14) == 0x14)
1108 return value == 0x14;
1109 else
1110 return 1;
1111}
1112
1113
1114
1115
1116static unsigned long
1117insert_bo (unsigned long insn,
1118 long value,
1119 int dialect,
1120 const char **errmsg)
1121{
1122 if (!valid_bo (value, dialect, 0))
1123 *errmsg = _("invalid conditional option");
1124 return insn | ((value & 0x1f) << 21);
1125}
1126
1127static long
1128extract_bo (unsigned long insn,
1129 int dialect,
1130 int *invalid)
1131{
1132 long value;
1133
1134 value = (insn >> 21) & 0x1f;
1135 if (!valid_bo (value, dialect, 1))
1136 *invalid = 1;
1137 return value;
1138}
1139
1140
1141
1142
1143
1144static unsigned long
1145insert_boe (unsigned long insn,
1146 long value,
1147 int dialect,
1148 const char **errmsg)
1149{
1150 if (!valid_bo (value, dialect, 0))
1151 *errmsg = _("invalid conditional option");
1152 else if ((value & 1) != 0)
1153 *errmsg = _("attempt to set y bit when using + or - modifier");
1154
1155 return insn | ((value & 0x1f) << 21);
1156}
1157
1158static long
1159extract_boe (unsigned long insn,
1160 int dialect,
1161 int *invalid)
1162{
1163 long value;
1164
1165 value = (insn >> 21) & 0x1f;
1166 if (!valid_bo (value, dialect, 1))
1167 *invalid = 1;
1168 return value & 0x1e;
1169}
1170
1171
1172
1173static unsigned long
1174insert_fxm (unsigned long insn,
1175 long value,
1176 int dialect,
1177 const char **errmsg)
1178{
1179
1180
1181 if ((insn & (1 << 20)) != 0)
1182 {
1183 if (value == 0 || (value & -value) != value)
1184 {
1185 *errmsg = _("invalid mask field");
1186 value = 0;
1187 }
1188 }
1189
1190
1191
1192
1193
1194 else if (value == 0)
1195 ;
1196
1197
1198
1199
1200
1201
1202 else if ((value & -value) == value
1203 && ((dialect & PPC_OPCODE_POWER4) != 0
1204 || ((dialect & PPC_OPCODE_ANY) != 0
1205 && (insn & (0x3ff << 1)) == 19 << 1)))
1206 insn |= 1 << 20;
1207
1208
1209 else if ((insn & (0x3ff << 1)) == 19 << 1)
1210 {
1211 *errmsg = _("ignoring invalid mfcr mask");
1212 value = 0;
1213 }
1214
1215 return insn | ((value & 0xff) << 12);
1216}
1217
1218static long
1219extract_fxm (unsigned long insn,
1220 int dialect ATTRIBUTE_UNUSED,
1221 int *invalid)
1222{
1223 long mask = (insn >> 12) & 0xff;
1224
1225
1226 if ((insn & (1 << 20)) != 0)
1227 {
1228
1229 if (mask == 0 || (mask & -mask) != mask)
1230 *invalid = 1;
1231 }
1232
1233
1234 else if ((insn & (0x3ff << 1)) == 19 << 1)
1235 {
1236 if (mask != 0)
1237 *invalid = 1;
1238 }
1239
1240 return mask;
1241}
1242
1243
1244
1245
1246
1247
1248static unsigned long
1249insert_mbe (unsigned long insn,
1250 long value,
1251 int dialect ATTRIBUTE_UNUSED,
1252 const char **errmsg)
1253{
1254 unsigned long uval, mask;
1255 int mb, me, mx, count, last;
1256
1257 uval = value;
1258
1259 if (uval == 0)
1260 {
1261 *errmsg = _("illegal bitmask");
1262 return insn;
1263 }
1264
1265 mb = 0;
1266 me = 32;
1267 if ((uval & 1) != 0)
1268 last = 1;
1269 else
1270 last = 0;
1271 count = 0;
1272
1273
1274
1275
1276
1277 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1278 {
1279 if ((uval & mask) && !last)
1280 {
1281 ++count;
1282 mb = mx;
1283 last = 1;
1284 }
1285 else if (!(uval & mask) && last)
1286 {
1287 ++count;
1288 me = mx;
1289 last = 0;
1290 }
1291 }
1292 if (me == 0)
1293 me = 32;
1294
1295 if (count != 2 && (count != 0 || ! last))
1296 *errmsg = _("illegal bitmask");
1297
1298 return insn | (mb << 6) | ((me - 1) << 1);
1299}
1300
1301static long
1302extract_mbe (unsigned long insn,
1303 int dialect ATTRIBUTE_UNUSED,
1304 int *invalid)
1305{
1306 long ret;
1307 int mb, me;
1308 int i;
1309
1310 *invalid = 1;
1311
1312 mb = (insn >> 6) & 0x1f;
1313 me = (insn >> 1) & 0x1f;
1314 if (mb < me + 1)
1315 {
1316 ret = 0;
1317 for (i = mb; i <= me; i++)
1318 ret |= 1L << (31 - i);
1319 }
1320 else if (mb == me + 1)
1321 ret = ~0;
1322 else
1323 {
1324 ret = ~0;
1325 for (i = me + 1; i < mb; i++)
1326 ret &= ~(1L << (31 - i));
1327 }
1328 return ret;
1329}
1330
1331
1332
1333
1334static unsigned long
1335insert_mb6 (unsigned long insn,
1336 long value,
1337 int dialect ATTRIBUTE_UNUSED,
1338 const char **errmsg ATTRIBUTE_UNUSED)
1339{
1340 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1341}
1342
1343static long
1344extract_mb6 (unsigned long insn,
1345 int dialect ATTRIBUTE_UNUSED,
1346 int *invalid ATTRIBUTE_UNUSED)
1347{
1348 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1349}
1350
1351
1352
1353
1354static long
1355extract_nb (unsigned long insn,
1356 int dialect ATTRIBUTE_UNUSED,
1357 int *invalid ATTRIBUTE_UNUSED)
1358{
1359 long ret;
1360
1361 ret = (insn >> 11) & 0x1f;
1362 if (ret == 0)
1363 ret = 32;
1364 return ret;
1365}
1366
1367
1368
1369
1370
1371
1372static unsigned long
1373insert_nsi (unsigned long insn,
1374 long value,
1375 int dialect ATTRIBUTE_UNUSED,
1376 const char **errmsg ATTRIBUTE_UNUSED)
1377{
1378 return insn | (-value & 0xffff);
1379}
1380
1381static long
1382extract_nsi (unsigned long insn,
1383 int dialect ATTRIBUTE_UNUSED,
1384 int *invalid)
1385{
1386 *invalid = 1;
1387 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1388}
1389
1390
1391
1392
1393
1394static unsigned long
1395insert_ral (unsigned long insn,
1396 long value,
1397 int dialect ATTRIBUTE_UNUSED,
1398 const char **errmsg)
1399{
1400 if (value == 0
1401 || (unsigned long) value == ((insn >> 21) & 0x1f))
1402 *errmsg = "invalid register operand when updating";
1403 return insn | ((value & 0x1f) << 16);
1404}
1405
1406
1407
1408
1409static unsigned long
1410insert_ram (unsigned long insn,
1411 long value,
1412 int dialect ATTRIBUTE_UNUSED,
1413 const char **errmsg)
1414{
1415 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1416 *errmsg = _("index register in load range");
1417 return insn | ((value & 0x1f) << 16);
1418}
1419
1420
1421
1422
1423static unsigned long
1424insert_raq (unsigned long insn,
1425 long value,
1426 int dialect ATTRIBUTE_UNUSED,
1427 const char **errmsg)
1428{
1429 long rtvalue = (insn & RT_MASK) >> 21;
1430
1431 if (value == rtvalue)
1432 *errmsg = _("source and target register operands must be different");
1433 return insn | ((value & 0x1f) << 16);
1434}
1435
1436
1437
1438
1439
1440static unsigned long
1441insert_ras (unsigned long insn,
1442 long value,
1443 int dialect ATTRIBUTE_UNUSED,
1444 const char **errmsg)
1445{
1446 if (value == 0)
1447 *errmsg = _("invalid register operand when updating");
1448 return insn | ((value & 0x1f) << 16);
1449}
1450
1451
1452
1453
1454
1455
1456
1457static unsigned long
1458insert_rbs (unsigned long insn,
1459 long value ATTRIBUTE_UNUSED,
1460 int dialect ATTRIBUTE_UNUSED,
1461 const char **errmsg ATTRIBUTE_UNUSED)
1462{
1463 return insn | (((insn >> 21) & 0x1f) << 11);
1464}
1465
1466static long
1467extract_rbs (unsigned long insn,
1468 int dialect ATTRIBUTE_UNUSED,
1469 int *invalid)
1470{
1471 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1472 *invalid = 1;
1473 return 0;
1474}
1475
1476
1477
1478static unsigned long
1479insert_sh6 (unsigned long insn,
1480 long value,
1481 int dialect ATTRIBUTE_UNUSED,
1482 const char **errmsg ATTRIBUTE_UNUSED)
1483{
1484 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1485}
1486
1487static long
1488extract_sh6 (unsigned long insn,
1489 int dialect ATTRIBUTE_UNUSED,
1490 int *invalid ATTRIBUTE_UNUSED)
1491{
1492 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1493}
1494
1495
1496
1497
1498static unsigned long
1499insert_spr (unsigned long insn,
1500 long value,
1501 int dialect ATTRIBUTE_UNUSED,
1502 const char **errmsg ATTRIBUTE_UNUSED)
1503{
1504 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1505}
1506
1507static long
1508extract_spr (unsigned long insn,
1509 int dialect ATTRIBUTE_UNUSED,
1510 int *invalid ATTRIBUTE_UNUSED)
1511{
1512 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1513}
1514
1515
1516
1517static unsigned long
1518insert_sprg (unsigned long insn,
1519 long value,
1520 int dialect,
1521 const char **errmsg)
1522{
1523
1524
1525
1526 if (value > 7
1527 || (value > 3
1528 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1529 *errmsg = _("invalid sprg number");
1530
1531
1532
1533 if (value <= 3 || (insn & 0x100) != 0)
1534 value |= 0x10;
1535
1536 return insn | ((value & 0x17) << 16);
1537}
1538
1539static long
1540extract_sprg (unsigned long insn,
1541 int dialect,
1542 int *invalid)
1543{
1544 unsigned long val = (insn >> 16) & 0x1f;
1545
1546
1547
1548 if (val <= 3
1549 || (val < 0x10 && (insn & 0x100) != 0)
1550 || (val - 0x10 > 3
1551 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1552 *invalid = 1;
1553 return val & 7;
1554}
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564#define TB (268)
1565
1566static unsigned long
1567insert_tbr (unsigned long insn,
1568 long value,
1569 int dialect ATTRIBUTE_UNUSED,
1570 const char **errmsg ATTRIBUTE_UNUSED)
1571{
1572 if (value == 0)
1573 value = TB;
1574 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1575}
1576
1577static long
1578extract_tbr (unsigned long insn,
1579 int dialect ATTRIBUTE_UNUSED,
1580 int *invalid ATTRIBUTE_UNUSED)
1581{
1582 long ret;
1583
1584 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1585 if (ret == TB)
1586 ret = 0;
1587 return ret;
1588}
1589
1590
1591
1592
1593#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1594#define OP_MASK OP (0x3f)
1595
1596
1597
1598
1599#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1600#define OPTO_MASK (OP_MASK | TO_MASK)
1601
1602
1603
1604
1605#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1606#define OPL_MASK OPL (0x3f,1)
1607
1608
1609#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1610#define A_MASK A (0x3f, 0x1f, 1)
1611
1612
1613#define AFRB_MASK (A_MASK | FRB_MASK)
1614
1615
1616#define AFRC_MASK (A_MASK | FRC_MASK)
1617
1618
1619#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1620
1621
1622#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1623
1624
1625#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1626#define B_MASK B (0x3f, 1, 1)
1627
1628
1629#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1630#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1631
1632
1633
1634
1635#define Y_MASK (((unsigned long) 1) << 21)
1636#define AT1_MASK (((unsigned long) 3) << 21)
1637#define AT2_MASK (((unsigned long) 9) << 21)
1638#define BBOY_MASK (BBO_MASK &~ Y_MASK)
1639#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1640
1641
1642
1643#define BBOCB(op, bo, cb, aa, lk) \
1644 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1645#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1646
1647
1648#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1649#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1650#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1651
1652
1653#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1654#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1655
1656
1657#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1658#define CTX_MASK CTX(0x3f, 0x7)
1659
1660
1661#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1662#define UCTX_MASK UCTX(0x3f, 0x1f)
1663
1664
1665#define DRA_MASK (OP_MASK | RA_MASK)
1666
1667
1668#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1669#define DS_MASK DSO (0x3f, 3)
1670
1671
1672#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1673#define DE_MASK DEO (0x3e, 0xf)
1674
1675
1676#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1677#define EVSEL_MASK EVSEL(0x3f, 0xff)
1678
1679
1680#define M(op, rc) (OP (op) | ((rc) & 1))
1681#define M_MASK M (0x3f, 1)
1682
1683
1684#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1685
1686
1687#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1688
1689
1690#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1691
1692
1693#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1694#define MD_MASK MD (0x3f, 0x7, 1)
1695
1696
1697#define MDMB_MASK (MD_MASK | MB6_MASK)
1698
1699
1700#define MDSH_MASK (MD_MASK | SH6_MASK)
1701
1702
1703#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1704#define MDS_MASK MDS (0x3f, 0xf, 1)
1705
1706
1707#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1708
1709
1710#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1711#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1712
1713
1714#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1715
1716
1717#define VX_MASK VX(0x3f, 0x7ff)
1718
1719
1720#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1721
1722
1723#define VXA_MASK VXA(0x3f, 0x3f)
1724
1725
1726#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1727
1728
1729#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1730
1731
1732#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1733
1734
1735#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1736
1737
1738#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1739
1740
1741#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1742
1743
1744#define X_MASK XRC (0x3f, 0x3ff, 1)
1745
1746
1747#define Z_MASK ZRC (0x3f, 0x1ff, 1)
1748#define Z2_MASK ZRC (0x3f, 0xff, 1)
1749
1750
1751#define XRA_MASK (X_MASK | RA_MASK)
1752
1753
1754#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1755
1756
1757#define XRB_MASK (X_MASK | RB_MASK)
1758
1759
1760#define XRT_MASK (X_MASK | RT_MASK)
1761
1762
1763#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1764
1765
1766#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1767
1768
1769#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1770
1771
1772#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1773
1774
1775#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1776
1777
1778#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1779
1780
1781#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1782
1783
1784
1785#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1786
1787
1788#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1789#define XTO_MASK (X_MASK | TO_MASK)
1790
1791
1792#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1793#define XTLB_MASK (X_MASK | SH_MASK)
1794
1795
1796#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1797
1798
1799#define XSYNC_MASK (0xff9fffff)
1800
1801
1802#define XEH_MASK (X_MASK & ~((unsigned long )1))
1803
1804
1805#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1806#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1807
1808
1809#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1810#define XFL_MASK XFL (0x3f, 0x3ff, 1)
1811
1812
1813#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1814#define XISEL_MASK XISEL(0x3f, 0x1f)
1815
1816
1817#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1818
1819
1820#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1821
1822
1823#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1824
1825
1826#define XLO(op, bo, xop, lk) \
1827 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1828#define XLO_MASK (XL_MASK | BO_MASK)
1829
1830
1831
1832#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1833#define XLYLK_MASK (XL_MASK | Y_MASK)
1834
1835
1836
1837#define XLOCB(op, bo, cb, xop, lk) \
1838 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1839#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1840
1841
1842#define XLBB_MASK (XL_MASK | BB_MASK)
1843#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1844#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1845
1846
1847#define XLBH_MASK (XL_MASK | (0x1c << 11))
1848
1849
1850#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1851
1852
1853#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1854
1855
1856#define XO(op, xop, oe, rc) \
1857 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1858#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1859
1860
1861#define XORB_MASK (XO_MASK | RB_MASK)
1862
1863
1864#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1865#define XS_MASK XS (0x3f, 0x1ff, 1)
1866
1867
1868#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1869
1870
1871#define XFXM(op, xop, fxm, p4) \
1872 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1873 | ((unsigned long)(p4) << 20))
1874
1875
1876#define XSPR(op, xop, spr) \
1877 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1878#define XSPR_MASK (X_MASK | SPR_MASK)
1879
1880
1881
1882#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1883
1884
1885
1886#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1887
1888
1889#define XE_MASK (0xffff7fff)
1890
1891
1892#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1893#define XUC_MASK XUC(0x3f, 0x1f)
1894
1895
1896#define BODNZF (0x0)
1897#define BODNZFP (0x1)
1898#define BODZF (0x2)
1899#define BODZFP (0x3)
1900#define BODNZT (0x8)
1901#define BODNZTP (0x9)
1902#define BODZT (0xa)
1903#define BODZTP (0xb)
1904
1905#define BOF (0x4)
1906#define BOFP (0x5)
1907#define BOFM4 (0x6)
1908#define BOFP4 (0x7)
1909#define BOT (0xc)
1910#define BOTP (0xd)
1911#define BOTM4 (0xe)
1912#define BOTP4 (0xf)
1913
1914#define BODNZ (0x10)
1915#define BODNZP (0x11)
1916#define BODZ (0x12)
1917#define BODZP (0x13)
1918#define BODNZM4 (0x18)
1919#define BODNZP4 (0x19)
1920#define BODZM4 (0x1a)
1921#define BODZP4 (0x1b)
1922
1923#define BOU (0x14)
1924
1925
1926
1927#define CBLT (0)
1928#define CBGT (1)
1929#define CBEQ (2)
1930#define CBSO (3)
1931
1932
1933#define TOLGT (0x1)
1934#define TOLLT (0x2)
1935#define TOEQ (0x4)
1936#define TOLGE (0x5)
1937#define TOLNL (0x5)
1938#define TOLLE (0x6)
1939#define TOLNG (0x6)
1940#define TOGT (0x8)
1941#define TOGE (0xc)
1942#define TONL (0xc)
1943#define TOLT (0x10)
1944#define TOLE (0x14)
1945#define TONG (0x14)
1946#define TONE (0x18)
1947#define TOU (0x1f)
1948
1949
1950
1951#undef PPC
1952#define PPC PPC_OPCODE_PPC
1953#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1954#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1955#define POWER4 PPC_OPCODE_POWER4
1956#define POWER5 PPC_OPCODE_POWER5
1957#define POWER6 PPC_OPCODE_POWER6
1958#define CELL PPC_OPCODE_CELL
1959#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1960#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1961#define PPC403 PPC_OPCODE_403
1962#define PPC405 PPC403
1963#define PPC440 PPC_OPCODE_440
1964#define PPC750 PPC
1965#define PPC860 PPC
1966#define PPCVEC PPC_OPCODE_ALTIVEC
1967#define POWER PPC_OPCODE_POWER
1968#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1969#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1970#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1971#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1972#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1973#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1974#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1975#define MFDEC1 PPC_OPCODE_POWER
1976#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1977#define BOOKE PPC_OPCODE_BOOKE
1978#define BOOKE64 PPC_OPCODE_BOOKE64
1979#define CLASSIC PPC_OPCODE_CLASSIC
1980#define PPCE300 PPC_OPCODE_E300
1981#define PPCSPE PPC_OPCODE_SPE
1982#define PPCISEL PPC_OPCODE_ISEL
1983#define PPCEFS PPC_OPCODE_EFS
1984#define PPCBRLK PPC_OPCODE_BRLOCK
1985#define PPCPMR PPC_OPCODE_PMR
1986#define PPCCHLK PPC_OPCODE_CACHELCK
1987#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1988#define PPCRFMCI PPC_OPCODE_RFMCI
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008const struct powerpc_opcode powerpc_opcodes[] = {
2009{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
2010{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
2011{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
2012{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
2013{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
2014{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
2015{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
2016{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
2017{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
2018{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
2019{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
2020{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
2021{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
2022{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
2023{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
2024{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
2025
2026{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
2027{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
2028{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
2029{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
2030{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
2031{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
2032{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
2033{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
2034{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
2035{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
2036{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
2037{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
2038{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
2039{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
2040{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
2041{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
2042{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
2043{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
2044{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
2045{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
2046{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
2047{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
2048{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
2049{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
2050{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
2051{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
2052{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
2053{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
2054{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
2055{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2056
2057{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2058{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2059{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2060{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2061{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2062{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2063{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2064{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2065{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2066{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2067{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2068{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2069{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2070{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2071{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2072{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2073{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2074{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2075{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2076{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2077{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2078{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2079{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2080{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2081{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2082{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2083{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2084{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2085{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2086{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2087{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2088{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2089{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2090{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2091{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2092{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2093{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2094{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2095{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2096{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2097{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2098{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2099{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2100{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2101{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2102{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2103{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2104{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2105{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2106{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2107{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2108{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2109{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2110{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2111{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2112{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2113{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2114{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2115{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2116{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2117{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2118{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2119{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2120{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2121{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2122{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2123{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2124{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2125{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2126{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2127{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2128{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2129{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2130{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2131{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2132{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2133{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2134{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2135{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2136{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2137{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2138{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2139{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2140{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2141{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
2142{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
2143
2144
2145
2146
2147{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
2148{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2149{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2150{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2151{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2152{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2153{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2154{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2155{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2156{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2157{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2158{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2159{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2160{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2161{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2162{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2163{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2164{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2165{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2166{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2167{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2168{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2169{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2170{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2171{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2172{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2173{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2174{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2175{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2176
2177
2178{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2179{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2180{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2181{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2182{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2183{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2184{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2185{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2186{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2187{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2188{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2189{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2190{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2191{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2192{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2193{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2194{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2195{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2196{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2197{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2198{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2199{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2200{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2201{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2202{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2203{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2204{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2205{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2206{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2207{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2208{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2209{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2210{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2211{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2212{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2213{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2214{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2215{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2216{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2217{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2218{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2219{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2220{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2221{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2222{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2223{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2224{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2225{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2226{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2227{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2228{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2229{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2230{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2231{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2232{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2233{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2234{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2235{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2236{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2237{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2238{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2239{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2240{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2241{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2242{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2243{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2244{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2245{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2246{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2247{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2248{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2249{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2250{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2251{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2252{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2253{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2254{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2255{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2256{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2257{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2258{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2259{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2260{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2261{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2262{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2263{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2264{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2265{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2266{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2267{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2268{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2269{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2270{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2271{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2272{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2273{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2274{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2275{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2276{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2277{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2278{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2279{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2280{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2281{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2282{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2283{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2284{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2285{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2286{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2287{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2288{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2289{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2290{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2291{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2292{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2293{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2294{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2295{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2296{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2297{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2298{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2299{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2300{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2301{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2302{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2303{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2304{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2305{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2306{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2307{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2308{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2309{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2310{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2311{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2312{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2313{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2314{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2315{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2316{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2317{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2318{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2319{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2320{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2321{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2322{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2323{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2324{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2325{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2326{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2327{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2328{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2329{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2330{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2331{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2332{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2333
2334{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2335{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2336{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2337{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2338{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2339{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2340{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2341{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2342{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2343{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2344{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2345{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2346{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2347
2348{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2349
2350{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2351{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2352{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2353{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2354{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2355{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2356{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2357{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2358{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2359{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2360
2361{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2362{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2363{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2364{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2365{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2366{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2367{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2368{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2369{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2370{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2371{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2372{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2373{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2374{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2375
2376{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2377{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2378{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2379{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2380{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2381{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2382
2383{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2384{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2385{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2386{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2387{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2388{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2389{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2390{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2391{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2392{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2393{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2394{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2395{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2396{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2397{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2398{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2399{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2400{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2401{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2402{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2403{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2404{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2405
2406{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2407{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2408{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2409{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2410{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2411{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2412{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2413{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2414{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2415{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2416{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2417{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2418{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2419{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2420
2421{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2422{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2423{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2424{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2425{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2426{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2427{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2428{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2429{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2430{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2431{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2432{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2433{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2434{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2435{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2436{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2437{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2438{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2439{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2440{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2441{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2442{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2443{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2444
2445{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2446{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2447{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2448{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2449{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2450{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2451{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2452{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2453{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2454{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2455{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2456{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2457{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2458{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2459{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2460{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2461{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2462{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2463{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2464{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2465{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2466{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2467{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2468
2469{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2470{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2471{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2472{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2473{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2474{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2475{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2476{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2477{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2478{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2479{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2480{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2481{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2482{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2483{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2484{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2485
2486{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2487{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2488{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2489{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2490{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2491{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2492{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2493{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2494{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2495{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2496{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2497{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2498
2499{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2500{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2501{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2502{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2503{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2504{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2505{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2506{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2507{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2508{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2509{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2510{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2511
2512{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2513{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2514{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2515{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2516{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2517{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2518
2519{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2520{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2521{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2522{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2523{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2524{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2525
2526{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2527{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2528{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2529{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2530{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2531{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2532{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2533{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2534
2535{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2536{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2537
2538{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2539{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2540{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2541{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2542
2543{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2544{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2545{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2546{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2547
2548{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2549{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2550{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2551{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2552{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2553{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2554{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2555{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2556
2557{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2558{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2559{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2560{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2561
2562{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2563{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2564{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2565{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2566
2567{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2568{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2569{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2570{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2571
2572{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2573{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2574{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2575{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2576
2577{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2578
2579{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2580{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2581
2582{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2583{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2584
2585{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2586{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2587
2588{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2589
2590{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2591{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2592{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2593{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2594
2595{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2596{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2597{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2598{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2599
2600{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2601{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2602{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2603{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2604
2605{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2606{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2607{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2608
2609{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2610{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2611{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2612
2613{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2614{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2615{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2616{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2617{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2618{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2619
2620{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2621{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2622{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2623{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2624{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2625
2626{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2627{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2628{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2629{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2630{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2631{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2632{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2633{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2634{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2635{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2636{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2637{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2638{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2639{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2640{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2641{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2642{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2643{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2644{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2645{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2646{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2647{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2648{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2649{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2650{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2651{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2652{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2653{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2654{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2655{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2656{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2657{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2658{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2659{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2660{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2661{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2662{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2663{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2664{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2665{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2666{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2667{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2668{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2669{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2670{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2671{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2672{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2673{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2674{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2675{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2676{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2677{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2678{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2679{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2680{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2681{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2682{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2683{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2684{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2685{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2686{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2687{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2688{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2689{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2690{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2691{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2692{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2693{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2694{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2695{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2696{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2697{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2698{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2699{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2700{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2701{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2702{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2703{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2704{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2705{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2706{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2707{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2708{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2709{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2710{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2711{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2712{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2713{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2714{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2715{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2716{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2717{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2718{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2719{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2720{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2721{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2722{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2723{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2724{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2725{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2726{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2727{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2728{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2729{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2730{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2731{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2732{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2733{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2734{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2735{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2736{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2737{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2738{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2739{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2740{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2741{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2742{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2743{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2744{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2745{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2746{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2747{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2748{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2749{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2750{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2751{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2752{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2753{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2754{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2755{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2756{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2757{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2758{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2759{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2760{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2761{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2762{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2763{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2764{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2765{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2766{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2767{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2768{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2769{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2770{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2771{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2772{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2773{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2774{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2775{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2776{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2777{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2778{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2779{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2780{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2781{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2782{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2783{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2784{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2785{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2786{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2787{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2788{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2789{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2790{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2791{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2792{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2793{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2794{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2795{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2796{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2797{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2798{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2799{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2800{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2801{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2802{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2803{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2804{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2805{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2806{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2807{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2808{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2809{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2810{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2811{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2812{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2813{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2814{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2815{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2816{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2817{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2818{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2819{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2820{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2821{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2822{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2823{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2824{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2825{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2826{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2827{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2828{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2829{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2830{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2831{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2832{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2833{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2834{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2835{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2836{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2837{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2838{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2839{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2840{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2841{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2842{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2843{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2844{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2845{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2846{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2847{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2848{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2849{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2850{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2851{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2852{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2853{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2854{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2855{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2856{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2857{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2858{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2859{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2860{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2861{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2862{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2863{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2864{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2865{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2866{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2867{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2868{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2869{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2870{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2871{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2872{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2873{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2874{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2875{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2876{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2877{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2878{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2879{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2880{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2881{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2882{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2883{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2884{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2885{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2886{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2887{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2888{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2889{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2890
2891{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
2892{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2893{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2894{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2895{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2896
2897{ "b", B(18,0,0), B_MASK, COM, { LI } },
2898{ "bl", B(18,0,1), B_MASK, COM, { LI } },
2899{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
2900{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
2901
2902{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2903
2904{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2905{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2906{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2907{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2908{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2909{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2910{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2911{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2912{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2913{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2914{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2915{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2916{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2917{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2918{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2919{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2920{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2921{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2922{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2923{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2924{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2925{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2926{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2927{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2928{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2929{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2930{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2931{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2932{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2933{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2934{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2935{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2936{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2937{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2938{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2939{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2940{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2941{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2942{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2943{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2944{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2945{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2946{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2947{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2948{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2949{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2950{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2951{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2952{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2953{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2954{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2955{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2956{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2957{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2958{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2959{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2960{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2961{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2962{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2963{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2964{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2965{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2966{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2967{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2968{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2969{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2970{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2971{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2972{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2973{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2974{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2975{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2976{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2977{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2978{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2979{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2980{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2981{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2982{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2983{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2984{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2985{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2986{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2987{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2988{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2989{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2990{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2991{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2992{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2993{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2994{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2995{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2996{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2997{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2998{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2999{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3000{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3001{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3002{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3003{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3004{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3005{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3006{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3007{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3008{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3009{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3010{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3011{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3012{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3013{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3014{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3015{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3016{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3017{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3018{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3019{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3020{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3021{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3022{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3023{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3024{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3025{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3026{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3027{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3028{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3029{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3030{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3031{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3032{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3033{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3034{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3035{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3036{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3037{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3038{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3039{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3040{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3041{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3042{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3043{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3044{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3045{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3046{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3047{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3048{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3049{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3050{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3051{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3052{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3053{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3054{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3055{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3056{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3057{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3058{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3059{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3060{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3061{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3062{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3063{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3064{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3065{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3066{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3067{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3068{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3069{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3070{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3071{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3072{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3073{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
3074{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3075{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3076{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3077{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3078{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3079{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
3080{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3081{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3082{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
3083{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3084{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
3085{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
3086{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3087{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3088{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
3089{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3090{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
3091{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
3092{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3093{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3094{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3095{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3096{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3097{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3098{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3099{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3100{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3101{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3102{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3103{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3104{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3105{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3106{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3107{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3108{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3109{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3110{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
3111{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3112{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3113{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
3114{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3115{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3116{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3117{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3118{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3119{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3120{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3121{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3122{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
3123{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
3124{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
3125{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
3126
3127{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
3128
3129{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
3130{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
3131{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
3132
3133{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
3134{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
3135
3136{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
3137
3138{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
3139
3140{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
3141{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
3142
3143{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3144{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
3145
3146{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
3147
3148{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
3149
3150{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } },
3151
3152{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
3153{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
3154
3155{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } },
3156
3157{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
3158
3159{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } },
3160
3161{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
3162{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
3163
3164{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } },
3165{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } },
3166
3167{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
3168{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
3169{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3170{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3171{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3172{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3173{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3174{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3175{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3176{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3177{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3178{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3179{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3180{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3181{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3182{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3183{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3184{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3185{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3186{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3187{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3188{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3189{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3190{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3191{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3192{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3193{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3194{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3195{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3196{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3197{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3198{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3199{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3200{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3201{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3202{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3203{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3204{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3205{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3206{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3207{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3208{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3209{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3210{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3211{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3212{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3213{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3214{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3215{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3216{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3217{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3218{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3219{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3220{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3221{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3222{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3223{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3224{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3225{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3226{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3227{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3228{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3229{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3230{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3231{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3232{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3233{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3234{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3235{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3236{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3237{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3238{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3239{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3240{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3241{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3242{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3243{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3244{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3245{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3246{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3247{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3248{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3249{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3250{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3251{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3252{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3253{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3254{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3255{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3256{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3257{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3258{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3259{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3260{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3261{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3262{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3263{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3264{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3265{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3266{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3267{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3268{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3269{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3270{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3271{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3272{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3273{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3274{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3275{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3276{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3277{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3278{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3279{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3280{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3281{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3282{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3283{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3284{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3285{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3286{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3287{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3288{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3289{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3290{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3291{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3292{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3293{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3294{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3295{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3296{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3297{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3298{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3299{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3300{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3301{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3302{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3303{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3304{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3305{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3306{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3307{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3308{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3309{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3310{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3311{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3312{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3313{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3314{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
3315{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3316{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3317{ "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } },
3318{ "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } },
3319
3320{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3321{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3322
3323{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3324{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3325
3326{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3327{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3328{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3329{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3330{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3331{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3332{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3333{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3334
3335{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3336{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3337
3338{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3339{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3340{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3341{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3342
3343{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3344{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3345{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3346{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3347{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3348{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3349
3350{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3351{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3352{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3353
3354{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3355{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3356
3357{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3358{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3359
3360{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3361{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3362
3363{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3364{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3365
3366{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3367{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3368
3369{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3370{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3371{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3372{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3373{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3374{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3375
3376{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3377{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3378
3379{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3380{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3381
3382{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3383{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3384
3385{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3386{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3387{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3388{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3389
3390{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3391{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3392
3393{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3394{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3395{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3396{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3397
3398{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3399{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3400{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3401{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3402{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3403{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3404{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3405{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3406{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3407{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3408{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3409{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3410{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3411{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3412{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3413{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3414{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3415{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3416{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3417{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3418{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3419{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3420{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3421{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3422{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3423{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3424{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3425{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3426{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3427{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3428{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3429
3430{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3431{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3432{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3433{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3434{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3435{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3436{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3437{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3438{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3439{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3440{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3441{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3442
3443{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3444{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3445
3446{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3447{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3448{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3449{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3450{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3451{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3452{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3453{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3454
3455{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3456{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3457
3458{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3459{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3460{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3461{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3462
3463{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3464{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
3465{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3466
3467{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3468
3469{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3470
3471{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
3472{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3473
3474{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3475{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3476
3477{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3478{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3479{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3480{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3481
3482{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3483{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3484{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3485{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3486
3487{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3488{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3489
3490{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3491{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3492
3493{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3494{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3495
3496{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3497
3498{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3499
3500{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3501{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3502{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3503{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3504
3505{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3506{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3507{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3508{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3509{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3510{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3511{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3512{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3513
3514{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3515
3516{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3517
3518{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3519{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3520
3521{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3522
3523{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3524
3525{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3526{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3527
3528{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3529{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3530
3531{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3532{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3533{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3534{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3535{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3536{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3537{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3538{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3539{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3540{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3541{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3542{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3543{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3544{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3545{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3546
3547{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3548{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3549
3550{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3551{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3552
3553{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3554{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3555
3556{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3557
3558{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3559
3560{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3561
3562{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
3563{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } },
3564
3565{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3566
3567{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3568
3569{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3570
3571{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3572{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3573{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3574{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3575
3576{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3577{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3578{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3579{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3580
3581{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3582
3583{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3584
3585{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3586
3587{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3588
3589{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3590{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3591{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3592{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3593
3594{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3595
3596{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3597
3598{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3599
3600{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3601
3602{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3603{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3604{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3605{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3606{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3607{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3608{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3609{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3610
3611{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3612{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3613{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3614{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3615{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3616{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3617{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3618{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3619
3620{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3621
3622{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3623{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
3624{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3625
3626{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3627
3628{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3629
3630{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3631
3632{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3633{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3634
3635{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3636
3637{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3638
3639{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3640{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3641
3642{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3643{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3644
3645{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
3646
3647{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3648
3649{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3650{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3651
3652{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
3653
3654{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3655
3656{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3657{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3658
3659{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3660{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3661
3662{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
3663
3664{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3665
3666{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3667{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3668{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3669{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3670{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3671{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3672{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3673{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3674
3675{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3676{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3677{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3678{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3679{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3680{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3681{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3682{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3683
3684{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3685
3686{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3687
3688{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3689
3690{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3691{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3692
3693{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3694{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3695
3696{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3697
3698{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3699
3700{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3701{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3702{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3703{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3704{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3705{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3706{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3707{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3708
3709{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3710{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3711{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3712{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3713
3714{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3715{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3716{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3717{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3718{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3719{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3720{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3721{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3722
3723{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3724{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3725{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3726{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3727{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3728{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3729{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3730{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3731
3732{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3733{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3734{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3735
3736{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3737
3738{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3739
3740{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3741{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3742
3743{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3744
3745{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3746
3747{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3748
3749{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3750{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3751{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3752{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3753
3754{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3755{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3756{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3757{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3758{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3759{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3760{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3761{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3762
3763{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3764
3765{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3766
3767{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3768{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3769
3770{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3771
3772{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3773
3774{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3775{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3776
3777{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3778
3779{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3780
3781{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3782{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3783
3784{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3785
3786{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3787
3788{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3789{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3790
3791{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3792
3793{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3794{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3795{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3796{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3797{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3798{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3799{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3800{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3801{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3802{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3803{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3804{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3805{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3806{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3807{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3808{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3809{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3810{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3811{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3812{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3813{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3814{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3815{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3816{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3817{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3818{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3819{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3820{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3821{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3822{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3823{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3824{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3825{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3826{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3827{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3828
3829{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3830{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3831{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3832{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3833
3834{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3835
3836{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3837{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3838{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3839{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3840{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3841{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3842{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3843{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3844{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3845{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3846{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3847{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3848{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3849{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3850{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3851{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
3852{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3853{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3854{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3855{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3856{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3857{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3858{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3859{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3860{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3861{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3862{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3863{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3864{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3865{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3866{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3867{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3868{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3869{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3870{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3871{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3872{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3873{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3874{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3875{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3876{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3877{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3878{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3879{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3880{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3881{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3882{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3883{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3884{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3885{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
3886{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3887{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3888{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3889{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3890{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3891{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3892{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3893{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
3894{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3895{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3896{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3897{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3898{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3899{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3900{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3901{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3902{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3903{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3904{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3905{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3906{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3907{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3908{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3909{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3910{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3911{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3912{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3913{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3914{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3915{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3916{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3917{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3918{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3919{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3920{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3921{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3922{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3923{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3924{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3925{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3926{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3927{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3928{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3929{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3930{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3931{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3932{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3933{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3934{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3935{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3936{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3937{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3938{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3939{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3940{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3941{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3942{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3943{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3944{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3945{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3946{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3947{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3948{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3949{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3950{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3951{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3952{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3953{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3954{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3955{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3956{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3957{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3958{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3959{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3960{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3961{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3962{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3963{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3964{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3965{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3966{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3967{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3968{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3969{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3970{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3971{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3972{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3973{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3974{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3975{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3976{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3977{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3978{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3979{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3980{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3981{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3982{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3983{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3984{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3985{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3986{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3987{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3988{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3989{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3990{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3991{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3992{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3993{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3994{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3995{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3996{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3997{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3998{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3999{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
4000{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
4001{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
4002{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
4003{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
4004{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
4005{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
4006{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
4007{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
4008{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
4009{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
4010{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
4011{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
4012{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
4013{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
4014{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
4015{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
4016{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
4017{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
4018{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
4019{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
4020{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
4021{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
4022{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
4023{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
4024
4025{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
4026
4027{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4028{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4029
4030{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
4031
4032{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
4033
4034{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4035{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
4036
4037{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
4038
4039{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
4040{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
4041{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
4042{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
4043
4044{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
4045{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
4046{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
4047{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
4048
4049{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
4050
4051{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
4052
4053{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
4054
4055{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
4056
4057{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
4058
4059{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
4060
4061{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4062{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4063
4064{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4065{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4066
4067{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
4068
4069{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
4070
4071{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
4072
4073{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
4074
4075{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
4076
4077{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
4078
4079{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
4080
4081{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
4082
4083{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
4084
4085{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
4086
4087{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
4088{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
4089
4090{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
4091{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
4092
4093{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
4094
4095{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
4096
4097{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
4098
4099{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
4100
4101{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
4102
4103{ "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }},
4104{ "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }},
4105{ "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }},
4106{ "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }},
4107{ "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }},
4108{ "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }},
4109{ "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }},
4110{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
4111{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
4112{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
4113{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
4114
4115{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
4116{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
4117{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
4118{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
4119{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
4120{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
4121{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
4122{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
4123{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
4124{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
4125{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
4126{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
4127{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
4128{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
4129{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
4130{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
4131{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
4132{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
4133{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
4134{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
4135{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
4136{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
4137{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
4138{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
4139{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
4140{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
4141{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
4142{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
4143{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
4144{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
4145{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
4146{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
4147{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
4148{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
4149{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
4150
4151{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4152{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4153
4154{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4155{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4156{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4157{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4158
4159{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4160{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4161
4162{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4163{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4164{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4165{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4166
4167{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
4168{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
4169{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
4170{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
4171{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
4172{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
4173{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
4174{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
4175{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
4176{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
4177{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
4178{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
4179{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
4180{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
4181{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
4182{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
4183{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
4184{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
4185{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
4186{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
4187{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
4188{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
4189{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
4190{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
4191{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
4192{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
4193{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
4194{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
4195{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
4196{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
4197{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
4198{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
4199{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
4200{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
4201{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
4202{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
4203{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
4204{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
4205{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
4206{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
4207{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
4208{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
4209{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
4210{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
4211{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
4212{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
4213{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
4214{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
4215{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
4216{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
4217{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
4218{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
4219{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
4220{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
4221{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
4222{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
4223{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
4224{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
4225{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
4226{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
4227{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
4228{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
4229{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
4230{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
4231{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
4232{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
4233{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
4234{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
4235{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
4236{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
4237{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
4238{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
4239{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
4240{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
4241{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
4242{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
4243{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
4244{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
4245{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
4246{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
4247{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
4248{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
4249{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
4250{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
4251{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
4252{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
4253{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
4254{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
4255{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
4256{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
4257{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
4258{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
4259{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
4260{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
4261{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4262{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4263{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4264{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4265{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4266{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4267{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4268{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4269{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4270{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4271{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
4272{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
4273{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4274{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4275{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4276{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4277{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4278{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4279{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4280{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4281{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4282{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4283{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4284{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4285{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4286{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4287{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4288{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4289{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4290{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4291{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4292{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4293{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4294{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4295{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4296{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4297{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4298{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4299{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4300{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4301{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4302{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4303{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4304{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4305{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4306{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4307{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4308{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4309{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4310{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4311{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4312{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4313{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4314{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4315{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4316{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4317{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4318{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4319{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4320
4321{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4322
4323{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4324{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4325
4326{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4327
4328{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4329
4330{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4331
4332{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4333
4334{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4335{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4336{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4337{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4338{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4339{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4340
4341{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4342{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4343{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4344{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4345
4346{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4347{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4348
4349{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4350{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4351{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4352{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4353
4354{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4355
4356{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4357
4358{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4359
4360{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4361
4362{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4363
4364{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4365{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4366
4367{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4368
4369{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4370
4371{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4372{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4373
4374{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4375{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4376
4377{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4378
4379{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4380{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4381{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4382{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4383
4384{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4385{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4386
4387{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4388{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4389
4390{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4391{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4392
4393{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4394
4395{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4396
4397{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4398
4399{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4400
4401{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4402
4403{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4404
4405{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4406
4407{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4408{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4409
4410{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4411{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4412{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4413{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4414{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4415
4416{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4417
4418{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4419
4420{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
4421
4422{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4423
4424{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4425
4426{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4427
4428{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4429
4430{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4431
4432{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4433
4434{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4435{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4436
4437{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4438{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4439
4440{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4441
4442{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4443{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4444
4445{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4446{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4447
4448{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4449
4450{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4451
4452{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4453
4454{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4455{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4456
4457{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4458
4459{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4460{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4461
4462{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4463
4464{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4465{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4466
4467{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4468{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4469
4470{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4471
4472{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
4473
4474{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4475
4476{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4477
4478{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4479{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4480
4481{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4482
4483{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4484
4485{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4486{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4487
4488{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4489
4490{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4491
4492{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4493{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4494{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4495{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4496
4497{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4498{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4499
4500{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4501
4502{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4503{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4504
4505{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4506
4507{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4508
4509{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4510{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4511
4512{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4513{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4514{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4515{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4516
4517{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4518
4519{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4520
4521{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4522{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4523
4524{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4525
4526{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4527
4528{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4529{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4530{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } },
4531{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } },
4532
4533{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4534
4535{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4536
4537{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4538
4539{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4540{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4541
4542{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4543{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4544
4545{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4546{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4547{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4548{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4549
4550{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4551
4552{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4553
4554{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4555{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4556{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4557
4558{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4559
4560{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4561{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4562
4563{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4564{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4565
4566{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4567
4568{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4569
4570{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4571{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4572{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4573{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4574
4575{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4576
4577{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4578
4579{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4580
4581{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4582{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4583
4584{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4585
4586{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4587{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4588
4589{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4590
4591{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4592
4593{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4594{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4595{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4596
4597{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4598
4599{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4600{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4601{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4602{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4603{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4604{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4605{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4606{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4607{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4608{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4609{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4610{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4611
4612
4613{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4614{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4615{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4616{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4617{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4618{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4619{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4620{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4621
4622{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4623{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4624
4625{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4626{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4627
4628{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4629
4630{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4631
4632{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4633{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4634
4635{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4636{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4637
4638{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4639
4640{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4641
4642{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4643
4644{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4645
4646{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4647
4648{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4649
4650{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4651
4652{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4653
4654{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4655{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4656
4657{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4658{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4659
4660{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4661
4662{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4663
4664{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4665
4666{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4667
4668{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4669
4670{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4671
4672{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4673
4674{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4675
4676{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4677
4678{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4679
4680{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4681
4682{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4683
4684{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4685{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4686{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4687{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4688{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4689{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4690{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4691{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4692{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4693{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4694{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4695{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4696{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4697{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4698
4699{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4700
4701{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4702
4703{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4704
4705{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4706{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4707
4708{ "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4709{ "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4710
4711{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4712{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4713
4714{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4715{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4716
4717{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4718{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4719
4720{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4721{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4722
4723{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4724{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4725
4726{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4727{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4728
4729{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4730{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4731
4732{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4733{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4734
4735{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4736{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4737
4738{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4739{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4740
4741{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4742{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4743
4744{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4745{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4746
4747{ "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4748{ "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4749
4750{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4751{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4752
4753{ "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4754{ "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4755
4756{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4757{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4758
4759{ "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4760{ "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4761
4762{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
4763
4764{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
4765{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4766{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4767
4768{ "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4769{ "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4770
4771{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
4772{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
4773
4774{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
4775{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
4776
4777{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4778{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4779
4780{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
4781{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
4782
4783{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4784{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4785
4786{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4787{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4788
4789{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
4790
4791{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
4792
4793{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
4794{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
4795
4796{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
4797{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
4798
4799{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4800{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4801
4802{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4803{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4804
4805{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4806
4807{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4808
4809{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
4810
4811{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4812{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4813{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4814{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4815{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4816{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4817{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4818{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4819{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4820{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4821{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4822{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4823
4824{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4825
4826{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4827
4828{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
4829
4830{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4831
4832{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4833{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4834
4835{ "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4836{ "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4837
4838{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4839{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4840
4841{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4842{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4843
4844{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4845{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4846{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4847{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4848
4849{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4850{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4851{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4852{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4853
4854{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4855{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4856{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4857{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4858
4859{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4860{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4861{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4862{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4863
4864{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4865{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4866{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4867{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4868
4869{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4870{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4871
4872{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4873{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4874
4875{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4876{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4877
4878{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4879{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4880{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4881{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4882
4883{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4884{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4885
4886{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4887{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4888{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4889{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4890
4891{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4892{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4893{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4894{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4895
4896{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4897{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4898{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4899{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4900
4901{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4902{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4903{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4904{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4905
4906{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4907
4908{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4909{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4910
4911{ "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4912{ "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4913
4914{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4915{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4916
4917{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4918{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4919
4920{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4921
4922{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4923{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4924
4925{ "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4926{ "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4927
4928{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4929{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4930
4931{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4932{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4933
4934{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4935{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4936
4937{ "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4938{ "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4939
4940{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
4941
4942{ "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
4943{ "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
4944
4945{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4946{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4947
4948{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
4949{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4950{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4951
4952{ "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4953{ "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4954
4955{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
4956{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
4957
4958{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4959{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4960
4961{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
4962{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
4963
4964{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4965{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4966
4967{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
4968{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
4969
4970{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
4971{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
4972{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
4973{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
4974{ "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
4975{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
4976{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
4977{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
4978
4979{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4980{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4981
4982{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4983{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4984
4985{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4986{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4987
4988{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
4989
4990{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
4991
4992{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
4993{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
4994
4995{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
4996{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
4997
4998{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
4999{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
5000
5001{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
5002{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
5003
5004{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
5005{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
5006
5007{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
5008{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
5009
5010{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
5011{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
5012
5013{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
5014{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
5015
5016};
5017
5018const int powerpc_num_opcodes =
5019 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
5030
5031
5032
5033const struct powerpc_macro powerpc_macros[] = {
5034{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
5035{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
5036{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
5037{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
5038{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
5039{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
5040{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
5041{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
5042{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
5043{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
5044{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
5045{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
5046{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
5047{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
5048{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
5049{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
5050
5051{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
5052{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
5053{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
5054{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
5055{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
5056{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
5057{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
5058{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
5059{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
5060{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
5061{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
5062{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
5063{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
5064{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
5065{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5066{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5067{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5068{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
5069{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
5070{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
5071{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
5072{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
5073};
5074
5075const int powerpc_num_macros =
5076 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
5077
5078
5079
5080
5081
5082
5083
5084
5085static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int);
5086
5087
5088
5089
5090
5091static int
5092powerpc_dialect (struct disassemble_info *info)
5093{
5094 int dialect = PPC_OPCODE_PPC;
5095
5096 if (BFD_DEFAULT_TARGET_SIZE == 64)
5097 dialect |= PPC_OPCODE_64;
5098
5099 if (info->disassembler_options
5100 && strstr (info->disassembler_options, "booke") != NULL)
5101 dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
5102 else if ((info->mach == bfd_mach_ppc_e500)
5103 || (info->disassembler_options
5104 && strstr (info->disassembler_options, "e500") != NULL))
5105 dialect |= (PPC_OPCODE_BOOKE
5106 | PPC_OPCODE_SPE | PPC_OPCODE_ISEL
5107 | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
5108 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
5109 | PPC_OPCODE_RFMCI);
5110 else if (info->disassembler_options
5111 && strstr (info->disassembler_options, "efs") != NULL)
5112 dialect |= PPC_OPCODE_EFS;
5113 else if (info->disassembler_options
5114 && strstr (info->disassembler_options, "e300") != NULL)
5115 dialect |= PPC_OPCODE_E300 | PPC_OPCODE_CLASSIC | PPC_OPCODE_COMMON;
5116 else if (info->disassembler_options
5117 && strstr (info->disassembler_options, "440") != NULL)
5118 dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_32
5119 | PPC_OPCODE_440 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI;
5120 else
5121 dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
5122 | PPC_OPCODE_COMMON | PPC_OPCODE_ALTIVEC);
5123
5124 if (info->disassembler_options
5125 && strstr (info->disassembler_options, "power4") != NULL)
5126 dialect |= PPC_OPCODE_POWER4;
5127
5128 if (info->disassembler_options
5129 && strstr (info->disassembler_options, "power5") != NULL)
5130 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
5131
5132 if (info->disassembler_options
5133 && strstr (info->disassembler_options, "cell") != NULL)
5134 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC;
5135
5136 if (info->disassembler_options
5137 && strstr (info->disassembler_options, "power6") != NULL)
5138 dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC;
5139
5140 if (info->disassembler_options
5141 && strstr (info->disassembler_options, "any") != NULL)
5142 dialect |= PPC_OPCODE_ANY;
5143
5144 if (info->disassembler_options)
5145 {
5146 if (strstr (info->disassembler_options, "32") != NULL)
5147 dialect &= ~PPC_OPCODE_64;
5148 else if (strstr (info->disassembler_options, "64") != NULL)
5149 dialect |= PPC_OPCODE_64;
5150 }
5151
5152 info->private_data = (char *) 0 + dialect;
5153 return dialect;
5154}
5155
5156
5157int
5158print_insn_ppc (bfd_vma memaddr, struct disassemble_info *info)
5159{
5160 int dialect = (char *) info->private_data - (char *) 0;
5161 return print_insn_powerpc (memaddr, info, info->endian == BFD_ENDIAN_BIG,
5162 dialect);
5163}
5164
5165
5166
5167int
5168print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
5169{
5170 int dialect = (char *) info->private_data - (char *) 0;
5171 return print_insn_powerpc (memaddr, info, 1, dialect);
5172}
5173
5174
5175
5176int
5177print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
5178{
5179 int dialect = (char *) info->private_data - (char *) 0;
5180 return print_insn_powerpc (memaddr, info, 0, dialect);
5181}
5182
5183
5184
5185int
5186print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
5187{
5188 return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
5189}
5190
5191
5192
5193static long
5194operand_value_powerpc (const struct powerpc_operand *operand,
5195 unsigned long insn, int dialect)
5196{
5197 long value;
5198 int invalid;
5199
5200 if (operand->extract)
5201 value = (*operand->extract) (insn, dialect, &invalid);
5202 else
5203 {
5204 value = (insn >> operand->shift) & operand->bitm;
5205 if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
5206 {
5207
5208
5209 unsigned long top = operand->bitm;
5210
5211
5212 top |= (top & -top) - 1;
5213 top &= ~(top >> 1);
5214 value = (value ^ top) - top;
5215 }
5216 }
5217
5218 return value;
5219}
5220
5221
5222
5223static int
5224skip_optional_operands (const unsigned char *opindex,
5225 unsigned long insn, int dialect)
5226{
5227 const struct powerpc_operand *operand;
5228
5229 for (; *opindex != 0; opindex++)
5230 {
5231 operand = &powerpc_operands[*opindex];
5232 if ((operand->flags & PPC_OPERAND_NEXT) != 0
5233 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
5234 && operand_value_powerpc (operand, insn, dialect) != 0))
5235 return 0;
5236 }
5237
5238 return 1;
5239}
5240
5241
5242
5243static int
5244print_insn_powerpc (bfd_vma memaddr,
5245 struct disassemble_info *info,
5246 int bigendian,
5247 int dialect)
5248{
5249 bfd_byte buffer[4];
5250 int status;
5251 unsigned long insn;
5252 const struct powerpc_opcode *opcode;
5253 const struct powerpc_opcode *opcode_end;
5254 unsigned long op;
5255
5256 if (dialect == 0)
5257 dialect = powerpc_dialect (info);
5258
5259 status = (*info->read_memory_func) (memaddr, buffer, 4, info);
5260 if (status != 0)
5261 {
5262 (*info->memory_error_func) (status, memaddr, info);
5263 return -1;
5264 }
5265
5266 if (bigendian)
5267 insn = bfd_getb32 (buffer);
5268 else
5269 insn = bfd_getl32 (buffer);
5270
5271
5272 op = PPC_OP (insn);
5273
5274
5275
5276 opcode_end = powerpc_opcodes + powerpc_num_opcodes;
5277 again:
5278 for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
5279 {
5280 unsigned long table_op;
5281 const unsigned char *opindex;
5282 const struct powerpc_operand *operand;
5283 int invalid;
5284 int need_comma;
5285 int need_paren;
5286 int skip_optional;
5287
5288 table_op = PPC_OP (opcode->opcode);
5289 if (op < table_op)
5290 break;
5291 if (op > table_op)
5292 continue;
5293
5294 if ((insn & opcode->mask) != opcode->opcode
5295 || (opcode->flags & dialect) == 0)
5296 continue;
5297
5298
5299
5300
5301 invalid = 0;
5302 for (opindex = opcode->operands; *opindex != 0; opindex++)
5303 {
5304 operand = powerpc_operands + *opindex;
5305 if (operand->extract)
5306 (*operand->extract) (insn, dialect, &invalid);
5307 }
5308 if (invalid)
5309 continue;
5310
5311
5312 if (opcode->operands[0] != 0)
5313 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name);
5314 else
5315 (*info->fprintf_func) (info->stream, "%s", opcode->name);
5316
5317
5318 need_comma = 0;
5319 need_paren = 0;
5320 skip_optional = -1;
5321 for (opindex = opcode->operands; *opindex != 0; opindex++)
5322 {
5323 long value;
5324
5325 operand = powerpc_operands + *opindex;
5326
5327
5328
5329
5330 if ((operand->flags & PPC_OPERAND_FAKE) != 0)
5331 continue;
5332
5333
5334
5335 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
5336 {
5337 if (skip_optional < 0)
5338 skip_optional = skip_optional_operands (opindex, insn,
5339 dialect);
5340 if (skip_optional)
5341 continue;
5342 }
5343
5344 value = operand_value_powerpc (operand, insn, dialect);
5345
5346 if (need_comma)
5347 {
5348 (*info->fprintf_func) (info->stream, ",");
5349 need_comma = 0;
5350 }
5351
5352
5353 if ((operand->flags & PPC_OPERAND_GPR) != 0
5354 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
5355 (*info->fprintf_func) (info->stream, "r%ld", value);
5356 else if ((operand->flags & PPC_OPERAND_FPR) != 0)
5357 (*info->fprintf_func) (info->stream, "f%ld", value);
5358 else if ((operand->flags & PPC_OPERAND_VR) != 0)
5359 (*info->fprintf_func) (info->stream, "v%ld", value);
5360 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
5361 (*info->print_address_func) (memaddr + value, info);
5362 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
5363 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
5364 else if ((operand->flags & PPC_OPERAND_CR) == 0
5365 || (dialect & PPC_OPCODE_PPC) == 0)
5366 (*info->fprintf_func) (info->stream, "%ld", value);
5367 else
5368 {
5369 if (operand->bitm == 7)
5370 (*info->fprintf_func) (info->stream, "cr%ld", value);
5371 else
5372 {
5373 static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
5374 int cr;
5375 int cc;
5376
5377 cr = value >> 2;
5378 if (cr != 0)
5379 (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
5380 cc = value & 3;
5381 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
5382 }
5383 }
5384
5385 if (need_paren)
5386 {
5387 (*info->fprintf_func) (info->stream, ")");
5388 need_paren = 0;
5389 }
5390
5391 if ((operand->flags & PPC_OPERAND_PARENS) == 0)
5392 need_comma = 1;
5393 else
5394 {
5395 (*info->fprintf_func) (info->stream, "(");
5396 need_paren = 1;
5397 }
5398 }
5399
5400
5401 return 4;
5402 }
5403
5404 if ((dialect & PPC_OPCODE_ANY) != 0)
5405 {
5406 dialect = ~PPC_OPCODE_ANY;
5407 goto again;
5408 }
5409
5410
5411 (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
5412
5413 return 4;
5414}
5415