LXR qemu/hw/alpha/pci.c

   1/*
   2 * QEMU Alpha PCI support functions.
   3 *
   4 * Some of this isn't very Alpha specific at all.
   5 *
   6 * ??? Sparse memory access not implemented.
   7 */
   8
   9#include "qemu/osdep.h"
  10#include "qemu-common.h"
  11#include "cpu.h"
  12#include "alpha_sys.h"
  13#include "qemu/log.h"
  14#include "sysemu/sysemu.h"
  15#include "trace.h"
  16
  17
  18/* Fallback for unassigned PCI I/O operations.  Avoids MCHK.  */
  19
  20static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size)
  21{
  22    return 0;
  23}
  24
  25static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size)
  26{
  27}
  28
  29const MemoryRegionOps alpha_pci_ignore_ops = {
  30    .read = ignore_read,
  31    .write = ignore_write,
  32    .endianness = DEVICE_LITTLE_ENDIAN,
  33    .valid = {
  34        .min_access_size = 1,
  35        .max_access_size = 8,
  36    },
  37    .impl = {
  38        .min_access_size = 1,
  39        .max_access_size = 8,
  40    },
  41};
  42
  43
  44/* PCI config space reads/writes, to byte-word addressable memory.  */
  45static uint64_t bw_conf1_read(void *opaque, hwaddr addr,
  46                              unsigned size)
  47{
  48    PCIBus *b = opaque;
  49    return pci_data_read(b, addr, size);
  50}
  51
  52static void bw_conf1_write(void *opaque, hwaddr addr,
  53                           uint64_t val, unsigned size)
  54{
  55    PCIBus *b = opaque;
  56    pci_data_write(b, addr, val, size);
  57}
  58
  59const MemoryRegionOps alpha_pci_conf1_ops = {
  60    .read = bw_conf1_read,
  61    .write = bw_conf1_write,
  62    .endianness = DEVICE_LITTLE_ENDIAN,
  63    .impl = {
  64        .min_access_size = 1,
  65        .max_access_size = 4,
  66    },
  67};
  68
  69/* PCI/EISA Interrupt Acknowledge Cycle.  */
  70
  71static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size)
  72{
  73    return pic_read_irq(isa_pic);
  74}
  75
  76static void special_write(void *opaque, hwaddr addr,
  77                          uint64_t val, unsigned size)
  78{
  79    trace_alpha_pci_iack_write();
  80}
  81
  82const MemoryRegionOps alpha_pci_iack_ops = {
  83    .read = iack_read,
  84    .write = special_write,
  85    .endianness = DEVICE_LITTLE_ENDIAN,
  86    .valid = {
  87        .min_access_size = 4,
  88        .max_access_size = 4,
  89    },
  90    .impl = {
  91        .min_access_size = 4,
  92        .max_access_size = 4,
  93    },
  94};
  95