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13#include "qemu/osdep.h"
14#include "qapi/error.h"
15#include "hw/hw.h"
16#include "hw/arm/pxa.h"
17#include "hw/arm/arm.h"
18#include "sysemu/sysemu.h"
19#include "hw/pcmcia.h"
20#include "hw/i2c/i2c.h"
21#include "hw/ssi/ssi.h"
22#include "hw/block/flash.h"
23#include "qemu/timer.h"
24#include "hw/devices.h"
25#include "hw/arm/sharpsl.h"
26#include "ui/console.h"
27#include "audio/audio.h"
28#include "hw/boards.h"
29#include "sysemu/block-backend.h"
30#include "hw/sysbus.h"
31#include "exec/address-spaces.h"
32
33#undef REG_FMT
34#define REG_FMT "0x%02lx"
35
36
37#define FLASH_BASE 0x0c000000
38#define FLASH_ECCLPLB 0x00
39#define FLASH_ECCLPUB 0x04
40#define FLASH_ECCCP 0x08
41#define FLASH_ECCCNTR 0x0c
42#define FLASH_ECCCLRR 0x10
43#define FLASH_FLASHIO 0x14
44#define FLASH_FLASHCTL 0x18
45
46#define FLASHCTL_CE0 (1 << 0)
47#define FLASHCTL_CLE (1 << 1)
48#define FLASHCTL_ALE (1 << 2)
49#define FLASHCTL_WP (1 << 3)
50#define FLASHCTL_CE1 (1 << 4)
51#define FLASHCTL_RYBY (1 << 5)
52#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
53
54#define TYPE_SL_NAND "sl-nand"
55#define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND)
56
57typedef struct {
58 SysBusDevice parent_obj;
59
60 MemoryRegion iomem;
61 DeviceState *nand;
62 uint8_t ctl;
63 uint8_t manf_id;
64 uint8_t chip_id;
65 ECCState ecc;
66} SLNANDState;
67
68static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
69{
70 SLNANDState *s = (SLNANDState *) opaque;
71 int ryby;
72
73 switch (addr) {
74#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
75 case FLASH_ECCLPLB:
76 return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
77 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
78
79#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
80 case FLASH_ECCLPUB:
81 return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
82 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
83
84 case FLASH_ECCCP:
85 return s->ecc.cp;
86
87 case FLASH_ECCCNTR:
88 return s->ecc.count & 0xff;
89
90 case FLASH_FLASHCTL:
91 nand_getpins(s->nand, &ryby);
92 if (ryby)
93 return s->ctl | FLASHCTL_RYBY;
94 else
95 return s->ctl;
96
97 case FLASH_FLASHIO:
98 if (size == 4) {
99 return ecc_digest(&s->ecc, nand_getio(s->nand)) |
100 (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
101 }
102 return ecc_digest(&s->ecc, nand_getio(s->nand));
103
104 default:
105 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
106 }
107 return 0;
108}
109
110static void sl_write(void *opaque, hwaddr addr,
111 uint64_t value, unsigned size)
112{
113 SLNANDState *s = (SLNANDState *) opaque;
114
115 switch (addr) {
116 case FLASH_ECCCLRR:
117
118 ecc_reset(&s->ecc);
119 break;
120
121 case FLASH_FLASHCTL:
122 s->ctl = value & 0xff & ~FLASHCTL_RYBY;
123 nand_setpins(s->nand,
124 s->ctl & FLASHCTL_CLE,
125 s->ctl & FLASHCTL_ALE,
126 s->ctl & FLASHCTL_NCE,
127 s->ctl & FLASHCTL_WP,
128 0);
129 break;
130
131 case FLASH_FLASHIO:
132 nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
133 break;
134
135 default:
136 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
137 }
138}
139
140enum {
141 FLASH_128M,
142 FLASH_1024M,
143};
144
145static const MemoryRegionOps sl_ops = {
146 .read = sl_read,
147 .write = sl_write,
148 .endianness = DEVICE_NATIVE_ENDIAN,
149};
150
151static void sl_flash_register(PXA2xxState *cpu, int size)
152{
153 DeviceState *dev;
154
155 dev = qdev_create(NULL, TYPE_SL_NAND);
156
157 qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
158 if (size == FLASH_128M)
159 qdev_prop_set_uint8(dev, "chip_id", 0x73);
160 else if (size == FLASH_1024M)
161 qdev_prop_set_uint8(dev, "chip_id", 0xf1);
162
163 qdev_init_nofail(dev);
164 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASE);
165}
166
167static int sl_nand_init(SysBusDevice *dev)
168{
169 SLNANDState *s = SL_NAND(dev);
170 DriveInfo *nand;
171
172 s->ctl = 0;
173
174 nand = drive_get(IF_MTD, 0, 0);
175 s->nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
176 s->manf_id, s->chip_id);
177
178 memory_region_init_io(&s->iomem, OBJECT(s), &sl_ops, s, "sl", 0x40);
179 sysbus_init_mmio(dev, &s->iomem);
180
181 return 0;
182}
183
184
185
186#define SPITZ_KEY_STROBE_NUM 11
187#define SPITZ_KEY_SENSE_NUM 7
188
189static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
190 12, 17, 91, 34, 36, 38, 39
191};
192
193static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
194 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
195};
196
197
198static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
199 { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
200 { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
201 { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
202 { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
203 { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
204 { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
205 { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
206 { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
207};
208
209#define SPITZ_GPIO_AK_INT 13
210#define SPITZ_GPIO_SYNC 16
211#define SPITZ_GPIO_ON_KEY 95
212#define SPITZ_GPIO_SWA 97
213#define SPITZ_GPIO_SWB 96
214
215
216static const int spitz_gpiomap[5] = {
217 SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
218 SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
219};
220
221#define TYPE_SPITZ_KEYBOARD "spitz-keyboard"
222#define SPITZ_KEYBOARD(obj) \
223 OBJECT_CHECK(SpitzKeyboardState, (obj), TYPE_SPITZ_KEYBOARD)
224
225typedef struct {
226 SysBusDevice parent_obj;
227
228 qemu_irq sense[SPITZ_KEY_SENSE_NUM];
229 qemu_irq gpiomap[5];
230 int keymap[0x80];
231 uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
232 uint16_t strobe_state;
233 uint16_t sense_state;
234
235 uint16_t pre_map[0x100];
236 uint16_t modifiers;
237 uint16_t imodifiers;
238 uint8_t fifo[16];
239 int fifopos, fifolen;
240 QEMUTimer *kbdtimer;
241} SpitzKeyboardState;
242
243static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
244{
245 int i;
246 uint16_t strobe, sense = 0;
247 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
248 strobe = s->keyrow[i] & s->strobe_state;
249 if (strobe) {
250 sense |= 1 << i;
251 if (!(s->sense_state & (1 << i)))
252 qemu_irq_raise(s->sense[i]);
253 } else if (s->sense_state & (1 << i))
254 qemu_irq_lower(s->sense[i]);
255 }
256
257 s->sense_state = sense;
258}
259
260static void spitz_keyboard_strobe(void *opaque, int line, int level)
261{
262 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
263
264 if (level)
265 s->strobe_state |= 1 << line;
266 else
267 s->strobe_state &= ~(1 << line);
268 spitz_keyboard_sense_update(s);
269}
270
271static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
272{
273 int spitz_keycode = s->keymap[keycode & 0x7f];
274 if (spitz_keycode == -1)
275 return;
276
277
278 if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
279 qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80));
280 return;
281 }
282
283 if (keycode & 0x80)
284 s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
285 else
286 s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
287
288 spitz_keyboard_sense_update(s);
289}
290
291#define SPITZ_MOD_SHIFT (1 << 7)
292#define SPITZ_MOD_CTRL (1 << 8)
293#define SPITZ_MOD_FN (1 << 9)
294
295#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
296
297static void spitz_keyboard_handler(void *opaque, int keycode)
298{
299 SpitzKeyboardState *s = opaque;
300 uint16_t code;
301 int mapcode;
302 switch (keycode) {
303 case 0x2a:
304 s->modifiers |= 1;
305 break;
306 case 0xaa:
307 s->modifiers &= ~1;
308 break;
309 case 0x36:
310 s->modifiers |= 2;
311 break;
312 case 0xb6:
313 s->modifiers &= ~2;
314 break;
315 case 0x1d:
316 s->modifiers |= 4;
317 break;
318 case 0x9d:
319 s->modifiers &= ~4;
320 break;
321 case 0x38:
322 s->modifiers |= 8;
323 break;
324 case 0xb8:
325 s->modifiers &= ~8;
326 break;
327 }
328
329 code = s->pre_map[mapcode = ((s->modifiers & 3) ?
330 (keycode | SPITZ_MOD_SHIFT) :
331 (keycode & ~SPITZ_MOD_SHIFT))];
332
333 if (code != mapcode) {
334#if 0
335 if ((code & SPITZ_MOD_SHIFT) && !(s->modifiers & 1)) {
336 QUEUE_KEY(0x2a | (keycode & 0x80));
337 }
338 if ((code & SPITZ_MOD_CTRL) && !(s->modifiers & 4)) {
339 QUEUE_KEY(0x1d | (keycode & 0x80));
340 }
341 if ((code & SPITZ_MOD_FN) && !(s->modifiers & 8)) {
342 QUEUE_KEY(0x38 | (keycode & 0x80));
343 }
344 if ((code & SPITZ_MOD_FN) && (s->modifiers & 1)) {
345 QUEUE_KEY(0x2a | (~keycode & 0x80));
346 }
347 if ((code & SPITZ_MOD_FN) && (s->modifiers & 2)) {
348 QUEUE_KEY(0x36 | (~keycode & 0x80));
349 }
350#else
351 if (keycode & 0x80) {
352 if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
353 QUEUE_KEY(0x2a | 0x80);
354 if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
355 QUEUE_KEY(0x1d | 0x80);
356 if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
357 QUEUE_KEY(0x38 | 0x80);
358 if ((s->imodifiers & 0x10) && (s->modifiers & 1))
359 QUEUE_KEY(0x2a);
360 if ((s->imodifiers & 0x20) && (s->modifiers & 2))
361 QUEUE_KEY(0x36);
362 s->imodifiers = 0;
363 } else {
364 if ((code & SPITZ_MOD_SHIFT) &&
365 !((s->modifiers | s->imodifiers) & 1)) {
366 QUEUE_KEY(0x2a);
367 s->imodifiers |= 1;
368 }
369 if ((code & SPITZ_MOD_CTRL) &&
370 !((s->modifiers | s->imodifiers) & 4)) {
371 QUEUE_KEY(0x1d);
372 s->imodifiers |= 4;
373 }
374 if ((code & SPITZ_MOD_FN) &&
375 !((s->modifiers | s->imodifiers) & 8)) {
376 QUEUE_KEY(0x38);
377 s->imodifiers |= 8;
378 }
379 if ((code & SPITZ_MOD_FN) && (s->modifiers & 1) &&
380 !(s->imodifiers & 0x10)) {
381 QUEUE_KEY(0x2a | 0x80);
382 s->imodifiers |= 0x10;
383 }
384 if ((code & SPITZ_MOD_FN) && (s->modifiers & 2) &&
385 !(s->imodifiers & 0x20)) {
386 QUEUE_KEY(0x36 | 0x80);
387 s->imodifiers |= 0x20;
388 }
389 }
390#endif
391 }
392
393 QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
394}
395
396static void spitz_keyboard_tick(void *opaque)
397{
398 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
399
400 if (s->fifolen) {
401 spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
402 s->fifolen --;
403 if (s->fifopos >= 16)
404 s->fifopos = 0;
405 }
406
407 timer_mod(s->kbdtimer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
408 NANOSECONDS_PER_SECOND / 32);
409}
410
411static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
412{
413 int i;
414 for (i = 0; i < 0x100; i ++)
415 s->pre_map[i] = i;
416 s->pre_map[0x02 | SPITZ_MOD_SHIFT] = 0x02 | SPITZ_MOD_SHIFT;
417 s->pre_map[0x28 | SPITZ_MOD_SHIFT] = 0x03 | SPITZ_MOD_SHIFT;
418 s->pre_map[0x04 | SPITZ_MOD_SHIFT] = 0x04 | SPITZ_MOD_SHIFT;
419 s->pre_map[0x05 | SPITZ_MOD_SHIFT] = 0x05 | SPITZ_MOD_SHIFT;
420 s->pre_map[0x06 | SPITZ_MOD_SHIFT] = 0x06 | SPITZ_MOD_SHIFT;
421 s->pre_map[0x08 | SPITZ_MOD_SHIFT] = 0x07 | SPITZ_MOD_SHIFT;
422 s->pre_map[0x28] = 0x08 | SPITZ_MOD_SHIFT;
423 s->pre_map[0x0a | SPITZ_MOD_SHIFT] = 0x09 | SPITZ_MOD_SHIFT;
424 s->pre_map[0x0b | SPITZ_MOD_SHIFT] = 0x0a | SPITZ_MOD_SHIFT;
425 s->pre_map[0x29 | SPITZ_MOD_SHIFT] = 0x0b | SPITZ_MOD_SHIFT;
426 s->pre_map[0x03 | SPITZ_MOD_SHIFT] = 0x0c | SPITZ_MOD_SHIFT;
427 s->pre_map[0xd3] = 0x0e | SPITZ_MOD_FN;
428 s->pre_map[0x3a] = 0x0f | SPITZ_MOD_FN;
429 s->pre_map[0x07 | SPITZ_MOD_SHIFT] = 0x11 | SPITZ_MOD_FN;
430 s->pre_map[0x0d] = 0x12 | SPITZ_MOD_FN;
431 s->pre_map[0x0d | SPITZ_MOD_SHIFT] = 0x13 | SPITZ_MOD_FN;
432 s->pre_map[0x1a] = 0x14 | SPITZ_MOD_FN;
433 s->pre_map[0x1b] = 0x15 | SPITZ_MOD_FN;
434 s->pre_map[0x1a | SPITZ_MOD_SHIFT] = 0x16 | SPITZ_MOD_FN;
435 s->pre_map[0x1b | SPITZ_MOD_SHIFT] = 0x17 | SPITZ_MOD_FN;
436 s->pre_map[0x27] = 0x22 | SPITZ_MOD_FN;
437 s->pre_map[0x27 | SPITZ_MOD_SHIFT] = 0x23 | SPITZ_MOD_FN;
438 s->pre_map[0x09 | SPITZ_MOD_SHIFT] = 0x24 | SPITZ_MOD_FN;
439 s->pre_map[0x2b] = 0x25 | SPITZ_MOD_FN;
440 s->pre_map[0x2b | SPITZ_MOD_SHIFT] = 0x26 | SPITZ_MOD_FN;
441 s->pre_map[0x0c | SPITZ_MOD_SHIFT] = 0x30 | SPITZ_MOD_FN;
442 s->pre_map[0x33 | SPITZ_MOD_SHIFT] = 0x33 | SPITZ_MOD_FN;
443 s->pre_map[0x35] = 0x33 | SPITZ_MOD_SHIFT;
444 s->pre_map[0x34 | SPITZ_MOD_SHIFT] = 0x34 | SPITZ_MOD_FN;
445 s->pre_map[0x35 | SPITZ_MOD_SHIFT] = 0x34 | SPITZ_MOD_SHIFT;
446 s->pre_map[0x49] = 0x48 | SPITZ_MOD_FN;
447 s->pre_map[0x51] = 0x50 | SPITZ_MOD_FN;
448
449 s->modifiers = 0;
450 s->imodifiers = 0;
451 s->fifopos = 0;
452 s->fifolen = 0;
453}
454
455#undef SPITZ_MOD_SHIFT
456#undef SPITZ_MOD_CTRL
457#undef SPITZ_MOD_FN
458
459static int spitz_keyboard_post_load(void *opaque, int version_id)
460{
461 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
462
463
464 memset(s->keyrow, 0, sizeof(s->keyrow));
465 spitz_keyboard_sense_update(s);
466 s->modifiers = 0;
467 s->imodifiers = 0;
468 s->fifopos = 0;
469 s->fifolen = 0;
470
471 return 0;
472}
473
474static void spitz_keyboard_register(PXA2xxState *cpu)
475{
476 int i;
477 DeviceState *dev;
478 SpitzKeyboardState *s;
479
480 dev = sysbus_create_simple(TYPE_SPITZ_KEYBOARD, -1, NULL);
481 s = SPITZ_KEYBOARD(dev);
482
483 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
484 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(cpu->gpio, spitz_gpio_key_sense[i]));
485
486 for (i = 0; i < 5; i ++)
487 s->gpiomap[i] = qdev_get_gpio_in(cpu->gpio, spitz_gpiomap[i]);
488
489 if (!graphic_rotate)
490 s->gpiomap[4] = qemu_irq_invert(s->gpiomap[4]);
491
492 for (i = 0; i < 5; i++)
493 qemu_set_irq(s->gpiomap[i], 0);
494
495 for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
496 qdev_connect_gpio_out(cpu->gpio, spitz_gpio_key_strobe[i],
497 qdev_get_gpio_in(dev, i));
498
499 timer_mod(s->kbdtimer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
500
501 qemu_add_kbd_event_handler(spitz_keyboard_handler, s);
502}
503
504static int spitz_keyboard_init(SysBusDevice *sbd)
505{
506 DeviceState *dev = DEVICE(sbd);
507 SpitzKeyboardState *s = SPITZ_KEYBOARD(dev);
508 int i, j;
509
510 for (i = 0; i < 0x80; i ++)
511 s->keymap[i] = -1;
512 for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
513 for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
514 if (spitz_keymap[i][j] != -1)
515 s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
516
517 spitz_keyboard_pre_map(s);
518
519 s->kbdtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, spitz_keyboard_tick, s);
520 qdev_init_gpio_in(dev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
521 qdev_init_gpio_out(dev, s->sense, SPITZ_KEY_SENSE_NUM);
522
523 return 0;
524}
525
526
527
528#define LCDTG_RESCTL 0x00
529#define LCDTG_PHACTRL 0x01
530#define LCDTG_DUTYCTRL 0x02
531#define LCDTG_POWERREG0 0x03
532#define LCDTG_POWERREG1 0x04
533#define LCDTG_GPOR3 0x05
534#define LCDTG_PICTRL 0x06
535#define LCDTG_POLCTRL 0x07
536
537typedef struct {
538 SSISlave ssidev;
539 uint32_t bl_intensity;
540 uint32_t bl_power;
541} SpitzLCDTG;
542
543static void spitz_bl_update(SpitzLCDTG *s)
544{
545 if (s->bl_power && s->bl_intensity)
546 zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity);
547 else
548 zaurus_printf("LCD Backlight now off\n");
549}
550
551
552static SpitzLCDTG *spitz_lcdtg;
553
554static inline void spitz_bl_bit5(void *opaque, int line, int level)
555{
556 SpitzLCDTG *s = spitz_lcdtg;
557 int prev = s->bl_intensity;
558
559 if (level)
560 s->bl_intensity &= ~0x20;
561 else
562 s->bl_intensity |= 0x20;
563
564 if (s->bl_power && prev != s->bl_intensity)
565 spitz_bl_update(s);
566}
567
568static inline void spitz_bl_power(void *opaque, int line, int level)
569{
570 SpitzLCDTG *s = spitz_lcdtg;
571 s->bl_power = !!level;
572 spitz_bl_update(s);
573}
574
575static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
576{
577 SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
578 int addr;
579 addr = value >> 5;
580 value &= 0x1f;
581
582 switch (addr) {
583 case LCDTG_RESCTL:
584 if (value)
585 zaurus_printf("LCD in QVGA mode\n");
586 else
587 zaurus_printf("LCD in VGA mode\n");
588 break;
589
590 case LCDTG_DUTYCTRL:
591 s->bl_intensity &= ~0x1f;
592 s->bl_intensity |= value;
593 if (s->bl_power)
594 spitz_bl_update(s);
595 break;
596
597 case LCDTG_POWERREG0:
598
599 break;
600 }
601 return 0;
602}
603
604static int spitz_lcdtg_init(SSISlave *dev)
605{
606 SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
607
608 spitz_lcdtg = s;
609 s->bl_power = 0;
610 s->bl_intensity = 0x20;
611
612 return 0;
613}
614
615
616
617#define CORGI_SSP_PORT 2
618
619#define SPITZ_GPIO_LCDCON_CS 53
620#define SPITZ_GPIO_ADS7846_CS 14
621#define SPITZ_GPIO_MAX1111_CS 20
622#define SPITZ_GPIO_TP_INT 11
623
624static DeviceState *max1111;
625
626
627typedef struct {
628 SSISlave ssidev;
629 SSIBus *bus[3];
630 uint32_t enable[3];
631} CorgiSSPState;
632
633static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
634{
635 CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
636 int i;
637
638 for (i = 0; i < 3; i++) {
639 if (s->enable[i]) {
640 return ssi_transfer(s->bus[i], value);
641 }
642 }
643 return 0;
644}
645
646static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
647{
648 CorgiSSPState *s = (CorgiSSPState *)opaque;
649 assert(line >= 0 && line < 3);
650 s->enable[line] = !level;
651}
652
653#define MAX1111_BATT_VOLT 1
654#define MAX1111_BATT_TEMP 2
655#define MAX1111_ACIN_VOLT 3
656
657#define SPITZ_BATTERY_TEMP 0xe0
658#define SPITZ_BATTERY_VOLT 0xd0
659#define SPITZ_CHARGEON_ACIN 0x80
660
661static void spitz_adc_temp_on(void *opaque, int line, int level)
662{
663 if (!max1111)
664 return;
665
666 if (level)
667 max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
668 else
669 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
670}
671
672static int corgi_ssp_init(SSISlave *d)
673{
674 DeviceState *dev = DEVICE(d);
675 CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, d);
676
677 qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3);
678 s->bus[0] = ssi_create_bus(dev, "ssi0");
679 s->bus[1] = ssi_create_bus(dev, "ssi1");
680 s->bus[2] = ssi_create_bus(dev, "ssi2");
681
682 return 0;
683}
684
685static void spitz_ssp_attach(PXA2xxState *cpu)
686{
687 DeviceState *mux;
688 DeviceState *dev;
689 void *bus;
690
691 mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
692
693 bus = qdev_get_child_bus(mux, "ssi0");
694 ssi_create_slave(bus, "spitz-lcdtg");
695
696 bus = qdev_get_child_bus(mux, "ssi1");
697 dev = ssi_create_slave(bus, "ads7846");
698 qdev_connect_gpio_out(dev, 0,
699 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
700
701 bus = qdev_get_child_bus(mux, "ssi2");
702 max1111 = ssi_create_slave(bus, "max1111");
703 max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
704 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
705 max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
706
707 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
708 qdev_get_gpio_in(mux, 0));
709 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
710 qdev_get_gpio_in(mux, 1));
711 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
712 qdev_get_gpio_in(mux, 2));
713}
714
715
716
717static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
718{
719 PCMCIACardState *md;
720 DriveInfo *dinfo;
721
722 dinfo = drive_get(IF_IDE, 0, 0);
723 if (!dinfo || dinfo->media_cd)
724 return;
725 md = dscm1xxxx_init(dinfo);
726 pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
727}
728
729
730
731#define AKITA_MAX_ADDR 0x18
732#define SPITZ_WM_ADDRL 0x1b
733#define SPITZ_WM_ADDRH 0x1a
734
735#define SPITZ_GPIO_WM 5
736
737static void spitz_wm8750_addr(void *opaque, int line, int level)
738{
739 I2CSlave *wm = (I2CSlave *) opaque;
740 if (level)
741 i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
742 else
743 i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
744}
745
746static void spitz_i2c_setup(PXA2xxState *cpu)
747{
748
749 I2CBus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
750
751 DeviceState *wm;
752
753
754 wm = i2c_create_slave(bus, "wm8750", 0);
755
756 spitz_wm8750_addr(wm, 0, 0);
757 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_WM,
758 qemu_allocate_irq(spitz_wm8750_addr, wm, 0));
759
760 cpu->i2s->opaque = wm;
761 cpu->i2s->codec_out = wm8750_dac_dat;
762 cpu->i2s->codec_in = wm8750_adc_dat;
763 wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
764}
765
766static void spitz_akita_i2c_setup(PXA2xxState *cpu)
767{
768
769 i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310",
770 AKITA_MAX_ADDR);
771}
772
773
774
775static void spitz_out_switch(void *opaque, int line, int level)
776{
777 switch (line) {
778 case 0:
779 zaurus_printf("Charging %s.\n", level ? "off" : "on");
780 break;
781 case 1:
782 zaurus_printf("Discharging %s.\n", level ? "on" : "off");
783 break;
784 case 2:
785 zaurus_printf("Green LED %s.\n", level ? "on" : "off");
786 break;
787 case 3:
788 zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
789 break;
790 case 4:
791 spitz_bl_bit5(opaque, line, level);
792 break;
793 case 5:
794 spitz_bl_power(opaque, line, level);
795 break;
796 case 6:
797 spitz_adc_temp_on(opaque, line, level);
798 break;
799 }
800}
801
802#define SPITZ_SCP_LED_GREEN 1
803#define SPITZ_SCP_JK_B 2
804#define SPITZ_SCP_CHRG_ON 3
805#define SPITZ_SCP_MUTE_L 4
806#define SPITZ_SCP_MUTE_R 5
807#define SPITZ_SCP_CF_POWER 6
808#define SPITZ_SCP_LED_ORANGE 7
809#define SPITZ_SCP_JK_A 8
810#define SPITZ_SCP_ADC_TEMP_ON 9
811#define SPITZ_SCP2_IR_ON 1
812#define SPITZ_SCP2_AKIN_PULLUP 2
813#define SPITZ_SCP2_BACKLIGHT_CONT 7
814#define SPITZ_SCP2_BACKLIGHT_ON 8
815#define SPITZ_SCP2_MIC_BIAS 9
816
817static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
818 DeviceState *scp0, DeviceState *scp1)
819{
820 qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
821
822 qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
823 qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
824 qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
825 qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
826
827 if (scp1) {
828 qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
829 qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
830 }
831
832 qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
833}
834
835#define SPITZ_GPIO_HSYNC 22
836#define SPITZ_GPIO_SD_DETECT 9
837#define SPITZ_GPIO_SD_WP 81
838#define SPITZ_GPIO_ON_RESET 89
839#define SPITZ_GPIO_BAT_COVER 90
840#define SPITZ_GPIO_CF1_IRQ 105
841#define SPITZ_GPIO_CF1_CD 94
842#define SPITZ_GPIO_CF2_IRQ 106
843#define SPITZ_GPIO_CF2_CD 93
844
845static int spitz_hsync;
846
847static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
848{
849 PXA2xxState *cpu = (PXA2xxState *) opaque;
850 qemu_set_irq(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_HSYNC), spitz_hsync);
851 spitz_hsync ^= 1;
852}
853
854static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
855{
856 qemu_irq lcd_hsync;
857
858
859
860
861
862
863 spitz_hsync = 0;
864 lcd_hsync = qemu_allocate_irq(spitz_lcd_hsync_handler, cpu, 0);
865 pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
866 pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
867
868
869 pxa2xx_mmci_handlers(cpu->mmc,
870 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_WP),
871 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_DETECT));
872
873
874 qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_BAT_COVER));
875
876
877 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
878
879
880 if (slots >= 1)
881 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
882 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_IRQ),
883 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_CD));
884 if (slots >= 2)
885 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
886 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_IRQ),
887 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_CD));
888}
889
890
891enum spitz_model_e { spitz, akita, borzoi, terrier };
892
893#define SPITZ_RAM 0x04000000
894#define SPITZ_ROM 0x00800000
895
896static struct arm_boot_info spitz_binfo = {
897 .loader_start = PXA2XX_SDRAM_BASE,
898 .ram_size = 0x04000000,
899};
900
901static void spitz_common_init(MachineState *machine,
902 enum spitz_model_e model, int arm_id)
903{
904 PXA2xxState *mpu;
905 DeviceState *scp0, *scp1 = NULL;
906 MemoryRegion *address_space_mem = get_system_memory();
907 MemoryRegion *rom = g_new(MemoryRegion, 1);
908 const char *cpu_model = machine->cpu_model;
909
910 if (!cpu_model)
911 cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
912
913
914 mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);
915
916 sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
917
918 memory_region_init_ram(rom, NULL, "spitz.rom", SPITZ_ROM, &error_fatal);
919 vmstate_register_ram_global(rom);
920 memory_region_set_readonly(rom, true);
921 memory_region_add_subregion(address_space_mem, 0, rom);
922
923
924 spitz_keyboard_register(mpu);
925
926 spitz_ssp_attach(mpu);
927
928 scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
929 if (model != akita) {
930 scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
931 }
932
933 spitz_scoop_gpio_setup(mpu, scp0, scp1);
934
935 spitz_gpio_setup(mpu, (model == akita) ? 1 : 2);
936
937 spitz_i2c_setup(mpu);
938
939 if (model == akita)
940 spitz_akita_i2c_setup(mpu);
941
942 if (model == terrier)
943
944 spitz_microdrive_attach(mpu, 1);
945 else if (model != akita)
946
947 spitz_microdrive_attach(mpu, 0);
948
949 spitz_binfo.kernel_filename = machine->kernel_filename;
950 spitz_binfo.kernel_cmdline = machine->kernel_cmdline;
951 spitz_binfo.initrd_filename = machine->initrd_filename;
952 spitz_binfo.board_id = arm_id;
953 arm_load_kernel(mpu->cpu, &spitz_binfo);
954 sl_bootparam_write(SL_PXA_PARAM_BASE);
955}
956
957static void spitz_init(MachineState *machine)
958{
959 spitz_common_init(machine, spitz, 0x2c9);
960}
961
962static void borzoi_init(MachineState *machine)
963{
964 spitz_common_init(machine, borzoi, 0x33f);
965}
966
967static void akita_init(MachineState *machine)
968{
969 spitz_common_init(machine, akita, 0x2e8);
970}
971
972static void terrier_init(MachineState *machine)
973{
974 spitz_common_init(machine, terrier, 0x33f);
975}
976
977static void akitapda_class_init(ObjectClass *oc, void *data)
978{
979 MachineClass *mc = MACHINE_CLASS(oc);
980
981 mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
982 mc->init = akita_init;
983}
984
985static const TypeInfo akitapda_type = {
986 .name = MACHINE_TYPE_NAME("akita"),
987 .parent = TYPE_MACHINE,
988 .class_init = akitapda_class_init,
989};
990
991static void spitzpda_class_init(ObjectClass *oc, void *data)
992{
993 MachineClass *mc = MACHINE_CLASS(oc);
994
995 mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)";
996 mc->init = spitz_init;
997}
998
999static const TypeInfo spitzpda_type = {
1000 .name = MACHINE_TYPE_NAME("spitz"),
1001 .parent = TYPE_MACHINE,
1002 .class_init = spitzpda_class_init,
1003};
1004
1005static void borzoipda_class_init(ObjectClass *oc, void *data)
1006{
1007 MachineClass *mc = MACHINE_CLASS(oc);
1008
1009 mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)";
1010 mc->init = borzoi_init;
1011}
1012
1013static const TypeInfo borzoipda_type = {
1014 .name = MACHINE_TYPE_NAME("borzoi"),
1015 .parent = TYPE_MACHINE,
1016 .class_init = borzoipda_class_init,
1017};
1018
1019static void terrierpda_class_init(ObjectClass *oc, void *data)
1020{
1021 MachineClass *mc = MACHINE_CLASS(oc);
1022
1023 mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)";
1024 mc->init = terrier_init;
1025}
1026
1027static const TypeInfo terrierpda_type = {
1028 .name = MACHINE_TYPE_NAME("terrier"),
1029 .parent = TYPE_MACHINE,
1030 .class_init = terrierpda_class_init,
1031};
1032
1033static void spitz_machine_init(void)
1034{
1035 type_register_static(&akitapda_type);
1036 type_register_static(&spitzpda_type);
1037 type_register_static(&borzoipda_type);
1038 type_register_static(&terrierpda_type);
1039}
1040
1041type_init(spitz_machine_init)
1042
1043static bool is_version_0(void *opaque, int version_id)
1044{
1045 return version_id == 0;
1046}
1047
1048static VMStateDescription vmstate_sl_nand_info = {
1049 .name = "sl-nand",
1050 .version_id = 0,
1051 .minimum_version_id = 0,
1052 .fields = (VMStateField[]) {
1053 VMSTATE_UINT8(ctl, SLNANDState),
1054 VMSTATE_STRUCT(ecc, SLNANDState, 0, vmstate_ecc_state, ECCState),
1055 VMSTATE_END_OF_LIST(),
1056 },
1057};
1058
1059static Property sl_nand_properties[] = {
1060 DEFINE_PROP_UINT8("manf_id", SLNANDState, manf_id, NAND_MFR_SAMSUNG),
1061 DEFINE_PROP_UINT8("chip_id", SLNANDState, chip_id, 0xf1),
1062 DEFINE_PROP_END_OF_LIST(),
1063};
1064
1065static void sl_nand_class_init(ObjectClass *klass, void *data)
1066{
1067 DeviceClass *dc = DEVICE_CLASS(klass);
1068 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1069
1070 k->init = sl_nand_init;
1071 dc->vmsd = &vmstate_sl_nand_info;
1072 dc->props = sl_nand_properties;
1073
1074 dc->cannot_instantiate_with_device_add_yet = true;
1075}
1076
1077static const TypeInfo sl_nand_info = {
1078 .name = TYPE_SL_NAND,
1079 .parent = TYPE_SYS_BUS_DEVICE,
1080 .instance_size = sizeof(SLNANDState),
1081 .class_init = sl_nand_class_init,
1082};
1083
1084static VMStateDescription vmstate_spitz_kbd = {
1085 .name = "spitz-keyboard",
1086 .version_id = 1,
1087 .minimum_version_id = 0,
1088 .post_load = spitz_keyboard_post_load,
1089 .fields = (VMStateField[]) {
1090 VMSTATE_UINT16(sense_state, SpitzKeyboardState),
1091 VMSTATE_UINT16(strobe_state, SpitzKeyboardState),
1092 VMSTATE_UNUSED_TEST(is_version_0, 5),
1093 VMSTATE_END_OF_LIST(),
1094 },
1095};
1096
1097static void spitz_keyboard_class_init(ObjectClass *klass, void *data)
1098{
1099 DeviceClass *dc = DEVICE_CLASS(klass);
1100 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1101
1102 k->init = spitz_keyboard_init;
1103 dc->vmsd = &vmstate_spitz_kbd;
1104}
1105
1106static const TypeInfo spitz_keyboard_info = {
1107 .name = TYPE_SPITZ_KEYBOARD,
1108 .parent = TYPE_SYS_BUS_DEVICE,
1109 .instance_size = sizeof(SpitzKeyboardState),
1110 .class_init = spitz_keyboard_class_init,
1111};
1112
1113static const VMStateDescription vmstate_corgi_ssp_regs = {
1114 .name = "corgi-ssp",
1115 .version_id = 2,
1116 .minimum_version_id = 2,
1117 .fields = (VMStateField[]) {
1118 VMSTATE_SSI_SLAVE(ssidev, CorgiSSPState),
1119 VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
1120 VMSTATE_END_OF_LIST(),
1121 }
1122};
1123
1124static void corgi_ssp_class_init(ObjectClass *klass, void *data)
1125{
1126 DeviceClass *dc = DEVICE_CLASS(klass);
1127 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
1128
1129 k->init = corgi_ssp_init;
1130 k->transfer = corgi_ssp_transfer;
1131 dc->vmsd = &vmstate_corgi_ssp_regs;
1132}
1133
1134static const TypeInfo corgi_ssp_info = {
1135 .name = "corgi-ssp",
1136 .parent = TYPE_SSI_SLAVE,
1137 .instance_size = sizeof(CorgiSSPState),
1138 .class_init = corgi_ssp_class_init,
1139};
1140
1141static const VMStateDescription vmstate_spitz_lcdtg_regs = {
1142 .name = "spitz-lcdtg",
1143 .version_id = 1,
1144 .minimum_version_id = 1,
1145 .fields = (VMStateField[]) {
1146 VMSTATE_SSI_SLAVE(ssidev, SpitzLCDTG),
1147 VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
1148 VMSTATE_UINT32(bl_power, SpitzLCDTG),
1149 VMSTATE_END_OF_LIST(),
1150 }
1151};
1152
1153static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
1154{
1155 DeviceClass *dc = DEVICE_CLASS(klass);
1156 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
1157
1158 k->init = spitz_lcdtg_init;
1159 k->transfer = spitz_lcdtg_transfer;
1160 dc->vmsd = &vmstate_spitz_lcdtg_regs;
1161}
1162
1163static const TypeInfo spitz_lcdtg_info = {
1164 .name = "spitz-lcdtg",
1165 .parent = TYPE_SSI_SLAVE,
1166 .instance_size = sizeof(SpitzLCDTG),
1167 .class_init = spitz_lcdtg_class_init,
1168};
1169
1170static void spitz_register_types(void)
1171{
1172 type_register_static(&corgi_ssp_info);
1173 type_register_static(&spitz_lcdtg_info);
1174 type_register_static(&spitz_keyboard_info);
1175 type_register_static(&sl_nand_info);
1176}
1177
1178type_init(spitz_register_types)
1179
