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24#ifndef HW_IDE_AHCI_H
25#define HW_IDE_AHCI_H
26
27#include <hw/sysbus.h>
28
29#define AHCI_MEM_BAR_SIZE 0x1000
30#define AHCI_MAX_PORTS 32
31#define AHCI_MAX_SG 168
32#define AHCI_DMA_BOUNDARY 0xffffffff
33#define AHCI_USE_CLUSTERING 0
34#define AHCI_MAX_CMDS 32
35#define AHCI_CMD_SZ 32
36#define AHCI_CMD_SLOT_SZ (AHCI_MAX_CMDS * AHCI_CMD_SZ)
37#define AHCI_RX_FIS_SZ 256
38#define AHCI_CMD_TBL_CDB 0x40
39#define AHCI_CMD_TBL_HDR_SZ 0x80
40#define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16))
41#define AHCI_CMD_TBL_AR_SZ (AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS)
42#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + \
43 AHCI_RX_FIS_SZ)
44
45#define AHCI_IRQ_ON_SG (1U << 31)
46#define AHCI_CMD_ATAPI (1 << 5)
47#define AHCI_CMD_WRITE (1 << 6)
48#define AHCI_CMD_PREFETCH (1 << 7)
49#define AHCI_CMD_RESET (1 << 8)
50#define AHCI_CMD_CLR_BUSY (1 << 10)
51
52#define RX_FIS_D2H_REG 0x40
53#define RX_FIS_SDB 0x58
54#define RX_FIS_UNK 0x60
55
56
57#define HOST_CAP 0x00
58#define HOST_CTL 0x04
59#define HOST_IRQ_STAT 0x08
60#define HOST_PORTS_IMPL 0x0c
61#define HOST_VERSION 0x10
62
63
64#define HOST_CTL_RESET (1 << 0)
65#define HOST_CTL_IRQ_EN (1 << 1)
66#define HOST_CTL_AHCI_EN (1U << 31)
67
68
69#define HOST_CAP_SSC (1 << 14)
70#define HOST_CAP_AHCI (1 << 18)
71#define HOST_CAP_CLO (1 << 24)
72#define HOST_CAP_SSS (1 << 27)
73#define HOST_CAP_NCQ (1 << 30)
74#define HOST_CAP_64 (1U << 31)
75
76
77#define PORT_LST_ADDR 0x00
78#define PORT_LST_ADDR_HI 0x04
79#define PORT_FIS_ADDR 0x08
80#define PORT_FIS_ADDR_HI 0x0c
81#define PORT_IRQ_STAT 0x10
82#define PORT_IRQ_MASK 0x14
83#define PORT_CMD 0x18
84#define PORT_TFDATA 0x20
85#define PORT_SIG 0x24
86#define PORT_SCR_STAT 0x28
87#define PORT_SCR_CTL 0x2c
88#define PORT_SCR_ERR 0x30
89#define PORT_SCR_ACT 0x34
90#define PORT_CMD_ISSUE 0x38
91#define PORT_RESERVED 0x3c
92
93
94#define PORT_IRQ_COLD_PRES (1U << 31)
95#define PORT_IRQ_TF_ERR (1 << 30)
96#define PORT_IRQ_HBUS_ERR (1 << 29)
97#define PORT_IRQ_HBUS_DATA_ERR (1 << 28)
98#define PORT_IRQ_IF_ERR (1 << 27)
99#define PORT_IRQ_IF_NONFATAL (1 << 26)
100#define PORT_IRQ_OVERFLOW (1 << 24)
101#define PORT_IRQ_BAD_PMP (1 << 23)
102
103#define PORT_IRQ_PHYRDY (1 << 22)
104#define PORT_IRQ_DEV_ILCK (1 << 7)
105#define PORT_IRQ_CONNECT (1 << 6)
106#define PORT_IRQ_SG_DONE (1 << 5)
107#define PORT_IRQ_UNK_FIS (1 << 4)
108#define PORT_IRQ_SDB_FIS (1 << 3)
109#define PORT_IRQ_DMAS_FIS (1 << 2)
110#define PORT_IRQ_PIOS_FIS (1 << 1)
111#define PORT_IRQ_D2H_REG_FIS (1 << 0)
112
113#define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \
114 PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \
115 PORT_IRQ_UNK_FIS)
116#define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \
117 PORT_IRQ_HBUS_DATA_ERR)
118#define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \
119 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \
120 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
121
122
123#define PORT_CMD_ATAPI (1 << 24)
124#define PORT_CMD_LIST_ON (1 << 15)
125#define PORT_CMD_FIS_ON (1 << 14)
126#define PORT_CMD_FIS_RX (1 << 4)
127#define PORT_CMD_CLO (1 << 3)
128#define PORT_CMD_POWER_ON (1 << 2)
129#define PORT_CMD_SPIN_UP (1 << 1)
130#define PORT_CMD_START (1 << 0)
131
132#define PORT_CMD_ICC_MASK (0xfU << 28)
133#define PORT_CMD_ICC_ACTIVE (0x1 << 28)
134#define PORT_CMD_ICC_PARTIAL (0x2 << 28)
135#define PORT_CMD_ICC_SLUMBER (0x6 << 28)
136
137#define PORT_CMD_RO_MASK 0x007dffe0
138
139
140#define AHCI_FLAG_NO_NCQ (1 << 24)
141#define AHCI_FLAG_IGN_IRQ_IF_ERR (1 << 25)
142#define AHCI_FLAG_HONOR_PI (1 << 26)
143#define AHCI_FLAG_IGN_SERR_INTERNAL (1 << 27)
144#define AHCI_FLAG_32BIT_ONLY (1 << 28)
145
146#define ATA_SRST (1 << 2)
147
148#define STATE_RUN 0
149#define STATE_RESET 1
150
151#define SATA_SCR_SSTATUS_DET_NODEV 0x0
152#define SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP 0x3
153
154#define SATA_SCR_SSTATUS_SPD_NODEV 0x00
155#define SATA_SCR_SSTATUS_SPD_GEN1 0x10
156
157#define SATA_SCR_SSTATUS_IPM_NODEV 0x000
158#define SATA_SCR_SSTATUS_IPM_ACTIVE 0X100
159
160#define AHCI_SCR_SCTL_DET 0xf
161
162#define SATA_FIS_TYPE_REGISTER_H2D 0x27
163#define SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER 0x80
164#define SATA_FIS_TYPE_REGISTER_D2H 0x34
165#define SATA_FIS_TYPE_PIO_SETUP 0x5f
166#define SATA_FIS_TYPE_SDB 0xA1
167
168#define AHCI_CMD_HDR_CMD_FIS_LEN 0x1f
169#define AHCI_CMD_HDR_PRDT_LEN 16
170
171#define SATA_SIGNATURE_CDROM 0xeb140101
172#define SATA_SIGNATURE_DISK 0x00000101
173
174#define AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR 0x20
175
176
177#define AHCI_PORT_REGS_START_ADDR 0x100
178#define AHCI_PORT_ADDR_OFFSET_MASK 0x7f
179#define AHCI_PORT_ADDR_OFFSET_LEN 0x80
180
181#define AHCI_NUM_COMMAND_SLOTS 31
182#define AHCI_SUPPORTED_SPEED 20
183#define AHCI_SUPPORTED_SPEED_GEN1 1
184#define AHCI_VERSION_1_0 0x10000
185
186#define AHCI_PROGMODE_MAJOR_REV_1 1
187
188#define AHCI_COMMAND_TABLE_ACMD 0x40
189
190#define AHCI_PRDT_SIZE_MASK 0x3fffff
191
192#define IDE_FEATURE_DMA 1
193
194#define READ_FPDMA_QUEUED 0x60
195#define WRITE_FPDMA_QUEUED 0x61
196#define NCQ_NON_DATA 0x63
197#define RECEIVE_FPDMA_QUEUED 0x65
198#define SEND_FPDMA_QUEUED 0x64
199
200#define NCQ_FIS_FUA_MASK 0x80
201#define NCQ_FIS_RARC_MASK 0x01
202
203#define RES_FIS_DSFIS 0x00
204#define RES_FIS_PSFIS 0x20
205#define RES_FIS_RFIS 0x40
206#define RES_FIS_SDBFIS 0x58
207#define RES_FIS_UFIS 0x60
208
209#define SATA_CAP_SIZE 0x8
210#define SATA_CAP_REV 0x2
211#define SATA_CAP_BAR 0x4
212
213typedef struct AHCIControlRegs {
214 uint32_t cap;
215 uint32_t ghc;
216 uint32_t irqstatus;
217 uint32_t impl;
218 uint32_t version;
219} AHCIControlRegs;
220
221typedef struct AHCIPortRegs {
222 uint32_t lst_addr;
223 uint32_t lst_addr_hi;
224 uint32_t fis_addr;
225 uint32_t fis_addr_hi;
226 uint32_t irq_stat;
227 uint32_t irq_mask;
228 uint32_t cmd;
229 uint32_t unused0;
230 uint32_t tfdata;
231 uint32_t sig;
232 uint32_t scr_stat;
233 uint32_t scr_ctl;
234 uint32_t scr_err;
235 uint32_t scr_act;
236 uint32_t cmd_issue;
237 uint32_t reserved;
238} AHCIPortRegs;
239
240typedef struct AHCICmdHdr {
241 uint16_t opts;
242 uint16_t prdtl;
243 uint32_t status;
244 uint64_t tbl_addr;
245 uint32_t reserved[4];
246} QEMU_PACKED AHCICmdHdr;
247
248typedef struct AHCI_SG {
249 uint64_t addr;
250 uint32_t reserved;
251 uint32_t flags_size;
252} QEMU_PACKED AHCI_SG;
253
254typedef struct AHCIDevice AHCIDevice;
255
256typedef struct NCQTransferState {
257 AHCIDevice *drive;
258 BlockAIOCB *aiocb;
259 AHCICmdHdr *cmdh;
260 QEMUSGList sglist;
261 BlockAcctCookie acct;
262 uint32_t sector_count;
263 uint64_t lba;
264 uint8_t tag;
265 uint8_t cmd;
266 uint8_t slot;
267 bool used;
268 bool halt;
269} NCQTransferState;
270
271struct AHCIDevice {
272 IDEDMA dma;
273 IDEBus port;
274 int port_no;
275 uint32_t port_state;
276 uint32_t finished;
277 AHCIPortRegs port_regs;
278 struct AHCIState *hba;
279 QEMUBH *check_bh;
280 uint8_t *lst;
281 uint8_t *res_fis;
282 bool done_atapi_packet;
283 int32_t busy_slot;
284 bool init_d2h_sent;
285 AHCICmdHdr *cur_cmd;
286 NCQTransferState ncq_tfs[AHCI_MAX_CMDS];
287};
288
289typedef struct AHCIState {
290 DeviceState *container;
291
292 AHCIDevice *dev;
293 AHCIControlRegs control_regs;
294 MemoryRegion mem;
295 MemoryRegion idp;
296 unsigned idp_offset;
297 uint32_t idp_index;
298 int32_t ports;
299 qemu_irq irq;
300 AddressSpace *as;
301} AHCIState;
302
303typedef struct AHCIPCIState {
304
305 PCIDevice parent_obj;
306
307
308 AHCIState ahci;
309} AHCIPCIState;
310
311#define TYPE_ICH9_AHCI "ich9-ahci"
312
313#define ICH_AHCI(obj) \
314 OBJECT_CHECK(AHCIPCIState, (obj), TYPE_ICH9_AHCI)
315
316extern const VMStateDescription vmstate_ahci;
317
318#define VMSTATE_AHCI(_field, _state) { \
319 .name = (stringify(_field)), \
320 .size = sizeof(AHCIState), \
321 .vmsd = &vmstate_ahci, \
322 .flags = VMS_STRUCT, \
323 .offset = vmstate_offset_value(_state, _field, AHCIState), \
324}
325
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335
336
337
338typedef struct NCQFrame {
339 uint8_t fis_type;
340 uint8_t c;
341 uint8_t command;
342 uint8_t sector_count_low;
343 uint8_t lba0;
344 uint8_t lba1;
345 uint8_t lba2;
346 uint8_t fua;
347 uint8_t lba3;
348 uint8_t lba4;
349 uint8_t lba5;
350 uint8_t sector_count_high;
351 uint8_t tag;
352 uint8_t prio;
353 uint8_t icc;
354 uint8_t control;
355 uint8_t aux0;
356 uint8_t aux1;
357 uint8_t aux2;
358 uint8_t aux3;
359} QEMU_PACKED NCQFrame;
360
361typedef struct SDBFIS {
362 uint8_t type;
363 uint8_t flags;
364 uint8_t status;
365 uint8_t error;
366 uint32_t payload;
367} QEMU_PACKED SDBFIS;
368
369void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);
370void ahci_init(AHCIState *s, DeviceState *qdev);
371void ahci_uninit(AHCIState *s);
372
373void ahci_reset(AHCIState *s);
374
375void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
376
377#define TYPE_SYSBUS_AHCI "sysbus-ahci"
378#define SYSBUS_AHCI(obj) OBJECT_CHECK(SysbusAHCIState, (obj), TYPE_SYSBUS_AHCI)
379
380typedef struct SysbusAHCIState {
381
382 SysBusDevice parent_obj;
383
384
385 AHCIState ahci;
386 uint32_t num_ports;
387} SysbusAHCIState;
388
389#define TYPE_ALLWINNER_AHCI "allwinner-ahci"
390#define ALLWINNER_AHCI(obj) OBJECT_CHECK(AllwinnerAHCIState, (obj), \
391 TYPE_ALLWINNER_AHCI)
392
393#define ALLWINNER_AHCI_MMIO_OFF 0x80
394#define ALLWINNER_AHCI_MMIO_SIZE 0x80
395
396struct AllwinnerAHCIState {
397
398 SysbusAHCIState parent_obj;
399
400
401 MemoryRegion mmio;
402 uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE/4];
403};
404
405#endif
406