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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "gic_internal.h"
24#include "hw/arm/linux-boot-if.h"
25
26static void gic_pre_save(void *opaque)
27{
28 GICState *s = (GICState *)opaque;
29 ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
30
31 if (c->pre_save) {
32 c->pre_save(s);
33 }
34}
35
36static int gic_post_load(void *opaque, int version_id)
37{
38 GICState *s = (GICState *)opaque;
39 ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
40
41 if (c->post_load) {
42 c->post_load(s);
43 }
44 return 0;
45}
46
47static const VMStateDescription vmstate_gic_irq_state = {
48 .name = "arm_gic_irq_state",
49 .version_id = 1,
50 .minimum_version_id = 1,
51 .fields = (VMStateField[]) {
52 VMSTATE_UINT8(enabled, gic_irq_state),
53 VMSTATE_UINT8(pending, gic_irq_state),
54 VMSTATE_UINT8(active, gic_irq_state),
55 VMSTATE_UINT8(level, gic_irq_state),
56 VMSTATE_BOOL(model, gic_irq_state),
57 VMSTATE_BOOL(edge_trigger, gic_irq_state),
58 VMSTATE_UINT8(group, gic_irq_state),
59 VMSTATE_END_OF_LIST()
60 }
61};
62
63static const VMStateDescription vmstate_gic = {
64 .name = "arm_gic",
65 .version_id = 12,
66 .minimum_version_id = 12,
67 .pre_save = gic_pre_save,
68 .post_load = gic_post_load,
69 .fields = (VMStateField[]) {
70 VMSTATE_UINT32(ctlr, GICState),
71 VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU),
72 VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
73 vmstate_gic_irq_state, gic_irq_state),
74 VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
75 VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
76 VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
77 VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
78 VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU),
79 VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU),
80 VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
81 VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
82 VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU),
83 VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
84 VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
85 VMSTATE_END_OF_LIST()
86 }
87};
88
89void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
90 const MemoryRegionOps *ops)
91{
92 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
93 int i = s->num_irq - GIC_INTERNAL;
94
95
96
97
98
99
100
101
102 if (s->revision != REV_NVIC) {
103 i += (GIC_INTERNAL * s->num_cpu);
104 }
105 qdev_init_gpio_in(DEVICE(s), handler, i);
106
107 for (i = 0; i < s->num_cpu; i++) {
108 sysbus_init_irq(sbd, &s->parent_irq[i]);
109 }
110 for (i = 0; i < s->num_cpu; i++) {
111 sysbus_init_irq(sbd, &s->parent_fiq[i]);
112 }
113
114
115 memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
116 sysbus_init_mmio(sbd, &s->iomem);
117
118 if (s->revision != REV_NVIC) {
119
120
121
122
123
124 memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,
125 s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100);
126 sysbus_init_mmio(sbd, &s->cpuiomem[0]);
127 }
128}
129
130static void arm_gic_common_realize(DeviceState *dev, Error **errp)
131{
132 GICState *s = ARM_GIC_COMMON(dev);
133 int num_irq = s->num_irq;
134
135 if (s->num_cpu > GIC_NCPU) {
136 error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
137 s->num_cpu, GIC_NCPU);
138 return;
139 }
140 s->num_irq += GIC_BASE_IRQ;
141 if (s->num_irq > GIC_MAXIRQ) {
142 error_setg(errp,
143 "requested %u interrupt lines exceeds GIC maximum %d",
144 num_irq, GIC_MAXIRQ);
145 return;
146 }
147
148
149
150
151 if (s->num_irq < 32 || (s->num_irq % 32)) {
152 error_setg(errp,
153 "%d interrupt lines unsupported: not divisible by 32",
154 num_irq);
155 return;
156 }
157
158 if (s->security_extn &&
159 (s->revision == REV_11MPCORE || s->revision == REV_NVIC)) {
160 error_setg(errp, "this GIC revision does not implement "
161 "the security extensions");
162 return;
163 }
164}
165
166static void arm_gic_common_reset(DeviceState *dev)
167{
168 GICState *s = ARM_GIC_COMMON(dev);
169 int i, j;
170 int resetprio;
171
172
173
174
175
176
177
178
179 if (s->security_extn && s->irq_reset_nonsecure) {
180 resetprio = 0x80;
181 } else {
182 resetprio = 0;
183 }
184
185 memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
186 for (i = 0 ; i < s->num_cpu; i++) {
187 if (s->revision == REV_11MPCORE) {
188 s->priority_mask[i] = 0xf0;
189 } else {
190 s->priority_mask[i] = resetprio;
191 }
192 s->current_pending[i] = 1023;
193 s->running_priority[i] = 0x100;
194 s->cpu_ctlr[i] = 0;
195 s->bpr[i] = GIC_MIN_BPR;
196 s->abpr[i] = GIC_MIN_ABPR;
197 for (j = 0; j < GIC_INTERNAL; j++) {
198 s->priority1[j][i] = resetprio;
199 }
200 for (j = 0; j < GIC_NR_SGIS; j++) {
201 s->sgi_pending[j][i] = 0;
202 }
203 }
204 for (i = 0; i < GIC_NR_SGIS; i++) {
205 GIC_SET_ENABLED(i, ALL_CPU_MASK);
206 GIC_SET_EDGE_TRIGGER(i);
207 }
208
209 for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
210 s->priority2[i] = resetprio;
211 }
212
213 for (i = 0; i < GIC_MAXIRQ; i++) {
214
215 if (s->num_cpu == 1) {
216 s->irq_target[i] = 1;
217 } else {
218 s->irq_target[i] = 0;
219 }
220 }
221 if (s->security_extn && s->irq_reset_nonsecure) {
222 for (i = 0; i < GIC_MAXIRQ; i++) {
223 GIC_SET_GROUP(i, ALL_CPU_MASK);
224 }
225 }
226
227 s->ctlr = 0;
228}
229
230static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
231 bool secure_boot)
232{
233 GICState *s = ARM_GIC_COMMON(obj);
234
235 if (s->security_extn && !secure_boot) {
236
237
238
239
240
241
242
243 s->irq_reset_nonsecure = true;
244 }
245}
246
247static Property arm_gic_common_properties[] = {
248 DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
249 DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
250
251
252
253
254 DEFINE_PROP_UINT32("revision", GICState, revision, 1),
255
256 DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
257 DEFINE_PROP_END_OF_LIST(),
258};
259
260static void arm_gic_common_class_init(ObjectClass *klass, void *data)
261{
262 DeviceClass *dc = DEVICE_CLASS(klass);
263 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
264
265 dc->reset = arm_gic_common_reset;
266 dc->realize = arm_gic_common_realize;
267 dc->props = arm_gic_common_properties;
268 dc->vmsd = &vmstate_gic;
269 albifc->arm_linux_init = arm_gic_common_linux_init;
270}
271
272static const TypeInfo arm_gic_common_type = {
273 .name = TYPE_ARM_GIC_COMMON,
274 .parent = TYPE_SYS_BUS_DEVICE,
275 .instance_size = sizeof(GICState),
276 .class_size = sizeof(ARMGICCommonClass),
277 .class_init = arm_gic_common_class_init,
278 .abstract = true,
279 .interfaces = (InterfaceInfo []) {
280 { TYPE_ARM_LINUX_BOOT_IF },
281 { },
282 },
283};
284
285static void register_types(void)
286{
287 type_register_static(&arm_gic_common_type);
288}
289
290type_init(register_types)
291