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25#include "qemu/osdep.h"
26#include "qemu-common.h"
27#include "cpu.h"
28#include "hw/hw.h"
29#include "hw/i386/pc.h"
30#include "hw/char/serial.h"
31#include "hw/block/fdc.h"
32#include "net/net.h"
33#include "hw/boards.h"
34#include "hw/i2c/smbus.h"
35#include "sysemu/block-backend.h"
36#include "hw/block/flash.h"
37#include "hw/mips/mips.h"
38#include "hw/mips/cpudevs.h"
39#include "hw/pci/pci.h"
40#include "sysemu/char.h"
41#include "sysemu/sysemu.h"
42#include "sysemu/arch_init.h"
43#include "qemu/log.h"
44#include "hw/mips/bios.h"
45#include "hw/ide.h"
46#include "hw/loader.h"
47#include "elf.h"
48#include "hw/timer/mc146818rtc.h"
49#include "hw/timer/i8254.h"
50#include "sysemu/block-backend.h"
51#include "sysemu/blockdev.h"
52#include "exec/address-spaces.h"
53#include "hw/sysbus.h"
54#include "qemu/host-utils.h"
55#include "sysemu/qtest.h"
56#include "qemu/error-report.h"
57#include "hw/empty_slot.h"
58#include "sysemu/kvm.h"
59#include "exec/semihost.h"
60#include "hw/mips/cps.h"
61
62
63
64#define ENVP_ADDR 0x80002000l
65#define ENVP_NB_ENTRIES 16
66#define ENVP_ENTRY_SIZE 256
67
68
69#define FLASH_ADDRESS 0x1e000000ULL
70#define FPGA_ADDRESS 0x1f000000ULL
71#define RESET_ADDRESS 0x1fc00000ULL
72
73#define FLASH_SIZE 0x400000
74
75#define MAX_IDE_BUS 2
76
77typedef struct {
78 MemoryRegion iomem;
79 MemoryRegion iomem_lo;
80 MemoryRegion iomem_hi;
81 uint32_t leds;
82 uint32_t brk;
83 uint32_t gpout;
84 uint32_t i2cin;
85 uint32_t i2coe;
86 uint32_t i2cout;
87 uint32_t i2csel;
88 CharDriverState *display;
89 char display_text[9];
90 SerialState *uart;
91} MaltaFPGAState;
92
93#define TYPE_MIPS_MALTA "mips-malta"
94#define MIPS_MALTA(obj) OBJECT_CHECK(MaltaState, (obj), TYPE_MIPS_MALTA)
95
96typedef struct {
97 SysBusDevice parent_obj;
98
99 MIPSCPSState *cps;
100 qemu_irq *i8259;
101} MaltaState;
102
103static ISADevice *pit;
104
105static struct _loaderparams {
106 int ram_size, ram_low_size;
107 const char *kernel_filename;
108 const char *kernel_cmdline;
109 const char *initrd_filename;
110} loaderparams;
111
112
113static void malta_fpga_update_display(void *opaque)
114{
115 char leds_text[9];
116 int i;
117 MaltaFPGAState *s = opaque;
118
119 for (i = 7 ; i >= 0 ; i--) {
120 if (s->leds & (1 << i))
121 leds_text[i] = '#';
122 else
123 leds_text[i] = ' ';
124 }
125 leds_text[8] = '\0';
126
127 qemu_chr_fe_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
128 qemu_chr_fe_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
129}
130
131
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133
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135
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140
141
142
143#if defined(DEBUG)
144# define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
145#else
146# define logout(fmt, ...) ((void)0)
147#endif
148
149struct _eeprom24c0x_t {
150 uint8_t tick;
151 uint8_t address;
152 uint8_t command;
153 uint8_t ack;
154 uint8_t scl;
155 uint8_t sda;
156 uint8_t data;
157
158 uint8_t contents[256];
159};
160
161typedef struct _eeprom24c0x_t eeprom24c0x_t;
162
163static eeprom24c0x_t spd_eeprom = {
164 .contents = {
165 0x80,0x08,0xFF,0x0D,0x0A,0xFF,0x40,0x00,
166 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
167 0x8F,0x04,0x02,0x01,0x01,0x00,0x00,0x00,
168 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0xFF,
169 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
170 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
171 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
172 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
173 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
174 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
175 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
176 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
177 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
178 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
179 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
180 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
181 },
182};
183
184static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
185{
186 enum { SDR = 0x4, DDR2 = 0x8 } type;
187 uint8_t *spd = spd_eeprom.contents;
188 uint8_t nbanks = 0;
189 uint16_t density = 0;
190 int i;
191
192
193 ram_size >>= 20;
194
195 while ((ram_size >= 4) && (nbanks <= 2)) {
196 int sz_log2 = MIN(31 - clz32(ram_size), 14);
197 nbanks++;
198 density |= 1 << (sz_log2 - 2);
199 ram_size -= 1 << sz_log2;
200 }
201
202
203 if ((nbanks == 1) && (density > 1)) {
204 nbanks++;
205 density >>= 1;
206 }
207
208 if (density & 0xff00) {
209 density = (density & 0xe0) | ((density >> 8) & 0x1f);
210 type = DDR2;
211 } else if (!(density & 0x1f)) {
212 type = DDR2;
213 } else {
214 type = SDR;
215 }
216
217 if (ram_size) {
218 fprintf(stderr, "Warning: SPD cannot represent final %dMB"
219 " of SDRAM\n", (int)ram_size);
220 }
221
222
223 spd[2] = type;
224 spd[5] = nbanks;
225 spd[31] = density;
226
227
228 spd[63] = 0;
229 for (i = 0; i < 63; i++) {
230 spd[63] += spd[i];
231 }
232
233
234 memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
235}
236
237static void generate_eeprom_serial(uint8_t *eeprom)
238{
239 int i, pos = 0;
240 uint8_t mac[6] = { 0x00 };
241 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
242
243
244 eeprom[pos++] = 0x01;
245
246
247 eeprom[pos++] = 0x02;
248
249
250 eeprom[pos++] = 0x01;
251 eeprom[pos++] = 0x06;
252 memcpy(&eeprom[pos], mac, sizeof(mac));
253 pos += sizeof(mac);
254
255
256 eeprom[pos++] = 0x02;
257 eeprom[pos++] = 0x05;
258 memcpy(&eeprom[pos], sn, sizeof(sn));
259 pos += sizeof(sn);
260
261
262 eeprom[pos] = 0;
263 for (i = 0; i < pos; i++) {
264 eeprom[pos] += eeprom[i];
265 }
266}
267
268static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom)
269{
270 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
271 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data);
272 return eeprom->sda;
273}
274
275static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda)
276{
277 if (eeprom->scl && scl && (eeprom->sda != sda)) {
278 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
279 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda,
280 sda ? "stop" : "start");
281 if (!sda) {
282 eeprom->tick = 1;
283 eeprom->command = 0;
284 }
285 } else if (eeprom->tick == 0 && !eeprom->ack) {
286
287 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
288 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
289 } else if (!eeprom->scl && scl) {
290 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
291 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
292 if (eeprom->ack) {
293 logout("\ti2c ack bit = 0\n");
294 sda = 0;
295 eeprom->ack = 0;
296 } else if (eeprom->sda == sda) {
297 uint8_t bit = (sda != 0);
298 logout("\ti2c bit = %d\n", bit);
299 if (eeprom->tick < 9) {
300 eeprom->command <<= 1;
301 eeprom->command += bit;
302 eeprom->tick++;
303 if (eeprom->tick == 9) {
304 logout("\tcommand 0x%04x, %s\n", eeprom->command,
305 bit ? "read" : "write");
306 eeprom->ack = 1;
307 }
308 } else if (eeprom->tick < 17) {
309 if (eeprom->command & 1) {
310 sda = ((eeprom->data & 0x80) != 0);
311 }
312 eeprom->address <<= 1;
313 eeprom->address += bit;
314 eeprom->tick++;
315 eeprom->data <<= 1;
316 if (eeprom->tick == 17) {
317 eeprom->data = eeprom->contents[eeprom->address];
318 logout("\taddress 0x%04x, data 0x%02x\n",
319 eeprom->address, eeprom->data);
320 eeprom->ack = 1;
321 eeprom->tick = 0;
322 }
323 } else if (eeprom->tick >= 17) {
324 sda = 0;
325 }
326 } else {
327 logout("\tsda changed with raising scl\n");
328 }
329 } else {
330 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl,
331 scl, eeprom->sda, sda);
332 }
333 eeprom->scl = scl;
334 eeprom->sda = sda;
335}
336
337static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
338 unsigned size)
339{
340 MaltaFPGAState *s = opaque;
341 uint32_t val = 0;
342 uint32_t saddr;
343
344 saddr = (addr & 0xfffff);
345
346 switch (saddr) {
347
348
349 case 0x00200:
350 val = 0x00000000;
351 break;
352
353
354 case 0x00208:
355#ifdef TARGET_WORDS_BIGENDIAN
356 val = 0x00000012;
357#else
358 val = 0x00000010;
359#endif
360 break;
361
362
363 case 0x00210:
364 val = 0x00;
365 break;
366
367
368 case 0x00408:
369 val = s->leds;
370 break;
371
372
373 case 0x00508:
374 val = s->brk;
375 break;
376
377
378
379
380 case 0x00a00:
381 val = s->gpout;
382 break;
383
384
385
386
387 case 0x00a08:
388
389 if (s->i2csel)
390 val = s->i2cout;
391 else
392 val = 0x00;
393 break;
394
395
396 case 0x00b00:
397 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom));
398 break;
399
400
401 case 0x00b08:
402 val = s->i2coe;
403 break;
404
405
406 case 0x00b10:
407 val = s->i2cout;
408 break;
409
410
411 case 0x00b18:
412 val = s->i2csel;
413 break;
414
415 default:
416#if 0
417 printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
418 addr);
419#endif
420 break;
421 }
422 return val;
423}
424
425static void malta_fpga_write(void *opaque, hwaddr addr,
426 uint64_t val, unsigned size)
427{
428 MaltaFPGAState *s = opaque;
429 uint32_t saddr;
430
431 saddr = (addr & 0xfffff);
432
433 switch (saddr) {
434
435
436 case 0x00200:
437 break;
438
439
440 case 0x00210:
441 break;
442
443
444 case 0x00408:
445 s->leds = val & 0xff;
446 malta_fpga_update_display(s);
447 break;
448
449
450 case 0x00410:
451 snprintf(s->display_text, 9, "%08X", (uint32_t)val);
452 malta_fpga_update_display(s);
453 break;
454
455
456 case 0x00418:
457 case 0x00420:
458 case 0x00428:
459 case 0x00430:
460 case 0x00438:
461 case 0x00440:
462 case 0x00448:
463 case 0x00450:
464 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
465 malta_fpga_update_display(s);
466 break;
467
468
469 case 0x00500:
470 if (val == 0x42)
471 qemu_system_reset_request ();
472 break;
473
474
475 case 0x00508:
476 s->brk = val & 0xff;
477 break;
478
479
480
481
482 case 0x00a00:
483 s->gpout = val & 0xff;
484 break;
485
486
487 case 0x00b08:
488 s->i2coe = val & 0x03;
489 break;
490
491
492 case 0x00b10:
493 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01);
494 s->i2cout = val;
495 break;
496
497
498 case 0x00b18:
499 s->i2csel = val & 0x01;
500 break;
501
502 default:
503#if 0
504 printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
505 addr);
506#endif
507 break;
508 }
509}
510
511static const MemoryRegionOps malta_fpga_ops = {
512 .read = malta_fpga_read,
513 .write = malta_fpga_write,
514 .endianness = DEVICE_NATIVE_ENDIAN,
515};
516
517static void malta_fpga_reset(void *opaque)
518{
519 MaltaFPGAState *s = opaque;
520
521 s->leds = 0x00;
522 s->brk = 0x0a;
523 s->gpout = 0x00;
524 s->i2cin = 0x3;
525 s->i2coe = 0x0;
526 s->i2cout = 0x3;
527 s->i2csel = 0x1;
528
529 s->display_text[8] = '\0';
530 snprintf(s->display_text, 9, " ");
531}
532
533static void malta_fpga_led_init(CharDriverState *chr)
534{
535 qemu_chr_fe_printf(chr, "\e[HMalta LEDBAR\r\n");
536 qemu_chr_fe_printf(chr, "+--------+\r\n");
537 qemu_chr_fe_printf(chr, "+ +\r\n");
538 qemu_chr_fe_printf(chr, "+--------+\r\n");
539 qemu_chr_fe_printf(chr, "\n");
540 qemu_chr_fe_printf(chr, "Malta ASCII\r\n");
541 qemu_chr_fe_printf(chr, "+--------+\r\n");
542 qemu_chr_fe_printf(chr, "+ +\r\n");
543 qemu_chr_fe_printf(chr, "+--------+\r\n");
544}
545
546static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
547 hwaddr base, qemu_irq uart_irq, CharDriverState *uart_chr)
548{
549 MaltaFPGAState *s;
550
551 s = (MaltaFPGAState *)g_malloc0(sizeof(MaltaFPGAState));
552
553 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
554 "malta-fpga", 0x100000);
555 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
556 &s->iomem, 0, 0x900);
557 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
558 &s->iomem, 0xa00, 0x10000-0xa00);
559
560 memory_region_add_subregion(address_space, base, &s->iomem_lo);
561 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
562
563 s->display = qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init);
564
565 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
566 230400, uart_chr, DEVICE_NATIVE_ENDIAN);
567
568 malta_fpga_reset(s);
569 qemu_register_reset(malta_fpga_reset, s);
570
571 return s;
572}
573
574
575static void network_init(PCIBus *pci_bus)
576{
577 int i;
578
579 for(i = 0; i < nb_nics; i++) {
580 NICInfo *nd = &nd_table[i];
581 const char *default_devaddr = NULL;
582
583 if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0))
584
585 default_devaddr = "0b";
586
587 pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr);
588 }
589}
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612
613static void write_bootloader(uint8_t *base, int64_t run_addr,
614 int64_t kernel_entry)
615{
616 uint32_t *p;
617
618
619 p = (uint32_t *)base;
620
621 stl_p(p++, 0x08000000 |
622 ((run_addr + 0x580) & 0x0fffffff) >> 2);
623 stl_p(p++, 0x00000000);
624
625
626 stl_p(base + 0x500, run_addr + 0x0580);
627 stl_p(base + 0x504, run_addr + 0x083c);
628 stl_p(base + 0x520, run_addr + 0x0580);
629 stl_p(base + 0x52c, run_addr + 0x0800);
630 stl_p(base + 0x534, run_addr + 0x0808);
631 stl_p(base + 0x538, run_addr + 0x0800);
632 stl_p(base + 0x53c, run_addr + 0x0800);
633 stl_p(base + 0x540, run_addr + 0x0800);
634 stl_p(base + 0x544, run_addr + 0x0800);
635 stl_p(base + 0x548, run_addr + 0x0800);
636 stl_p(base + 0x54c, run_addr + 0x0800);
637 stl_p(base + 0x550, run_addr + 0x0800);
638 stl_p(base + 0x554, run_addr + 0x0800);
639
640
641
642 p = (uint32_t *) (base + 0x580);
643
644 if (semihosting_get_argc()) {
645
646 stl_p(p++, 0x00000000);
647 } else {
648 stl_p(p++, 0x24040002);
649 }
650 stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff));
651 stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff));
652 stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff));
653 stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff));
654 stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff));
655 stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));
656 stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
657 stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
658
659
660 stl_p(p++, 0x3c09b400);
661
662#ifdef TARGET_WORDS_BIGENDIAN
663 stl_p(p++, 0x3c08df00);
664#else
665 stl_p(p++, 0x340800df);
666#endif
667 stl_p(p++, 0xad280068);
668
669 stl_p(p++, 0x3c09bbe0);
670
671#ifdef TARGET_WORDS_BIGENDIAN
672 stl_p(p++, 0x3c08c000);
673#else
674 stl_p(p++, 0x340800c0);
675#endif
676 stl_p(p++, 0xad280048);
677#ifdef TARGET_WORDS_BIGENDIAN
678 stl_p(p++, 0x3c084000);
679#else
680 stl_p(p++, 0x34080040);
681#endif
682 stl_p(p++, 0xad280050);
683
684#ifdef TARGET_WORDS_BIGENDIAN
685 stl_p(p++, 0x3c088000);
686#else
687 stl_p(p++, 0x34080080);
688#endif
689 stl_p(p++, 0xad280058);
690#ifdef TARGET_WORDS_BIGENDIAN
691 stl_p(p++, 0x3c083f00);
692#else
693 stl_p(p++, 0x3408003f);
694#endif
695 stl_p(p++, 0xad280060);
696
697#ifdef TARGET_WORDS_BIGENDIAN
698 stl_p(p++, 0x3c08c100);
699#else
700 stl_p(p++, 0x340800c1);
701#endif
702 stl_p(p++, 0xad280080);
703#ifdef TARGET_WORDS_BIGENDIAN
704 stl_p(p++, 0x3c085e00);
705#else
706 stl_p(p++, 0x3408005e);
707#endif
708 stl_p(p++, 0xad280088);
709
710
711 stl_p(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff));
712 stl_p(p++, 0x37ff0000 | (kernel_entry & 0xffff));
713 stl_p(p++, 0x03e00009);
714 stl_p(p++, 0x00000000);
715
716
717 p = (uint32_t *) (base + 0x800);
718 stl_p(p++, 0x03e00009);
719 stl_p(p++, 0x24020000);
720
721 stl_p(p++, 0x03e06821);
722 stl_p(p++, 0x00805821);
723 stl_p(p++, 0x00a05021);
724 stl_p(p++, 0x91440000);
725 stl_p(p++, 0x254a0001);
726 stl_p(p++, 0x10800005);
727 stl_p(p++, 0x00000000);
728 stl_p(p++, 0x0ff0021c);
729 stl_p(p++, 0x00000000);
730 stl_p(p++, 0x08000205);
731 stl_p(p++, 0x00000000);
732 stl_p(p++, 0x01a00009);
733 stl_p(p++, 0x01602021);
734
735 stl_p(p++, 0x03e06821);
736 stl_p(p++, 0x00805821);
737 stl_p(p++, 0x00a05021);
738 stl_p(p++, 0x00c06021);
739 stl_p(p++, 0x91440000);
740 stl_p(p++, 0x0ff0021c);
741 stl_p(p++, 0x00000000);
742 stl_p(p++, 0x254a0001);
743 stl_p(p++, 0x258cffff);
744 stl_p(p++, 0x1580fffa);
745 stl_p(p++, 0x00000000);
746 stl_p(p++, 0x01a00009);
747 stl_p(p++, 0x01602021);
748
749 stl_p(p++, 0x3c08b800);
750 stl_p(p++, 0x350803f8);
751 stl_p(p++, 0x91090005);
752 stl_p(p++, 0x00000000);
753 stl_p(p++, 0x31290040);
754 stl_p(p++, 0x1120fffc);
755 stl_p(p++, 0x00000000);
756 stl_p(p++, 0x03e00009);
757 stl_p(p++, 0xa1040000);
758
759}
760
761static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf, int index,
762 const char *string, ...)
763{
764 va_list ap;
765 int32_t table_addr;
766
767 if (index >= ENVP_NB_ENTRIES)
768 return;
769
770 if (string == NULL) {
771 prom_buf[index] = 0;
772 return;
773 }
774
775 table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
776 prom_buf[index] = tswap32(ENVP_ADDR + table_addr);
777
778 va_start(ap, string);
779 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
780 va_end(ap);
781}
782
783
784static int64_t load_kernel (void)
785{
786 int64_t kernel_entry, kernel_high;
787 long initrd_size;
788 ram_addr_t initrd_offset;
789 int big_endian;
790 uint32_t *prom_buf;
791 long prom_size;
792 int prom_index = 0;
793 uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr);
794
795#ifdef TARGET_WORDS_BIGENDIAN
796 big_endian = 1;
797#else
798 big_endian = 0;
799#endif
800
801 if (load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL,
802 (uint64_t *)&kernel_entry, NULL, (uint64_t *)&kernel_high,
803 big_endian, EM_MIPS, 1, 0) < 0) {
804 fprintf(stderr, "qemu: could not load kernel '%s'\n",
805 loaderparams.kernel_filename);
806 exit(1);
807 }
808
809
810 if (kvm_enabled()) {
811 if (kernel_entry & 0x80000000ll) {
812 error_report("KVM guest kernels must be linked in useg. "
813 "Did you forget to enable CONFIG_KVM_GUEST?");
814 exit(1);
815 }
816
817 xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0;
818 } else {
819 if (!(kernel_entry & 0x80000000ll)) {
820 error_report("KVM guest kernels aren't supported with TCG. "
821 "Did you unintentionally enable CONFIG_KVM_GUEST?");
822 exit(1);
823 }
824
825 xlate_to_kseg0 = cpu_mips_phys_to_kseg0;
826 }
827
828
829 initrd_size = 0;
830 initrd_offset = 0;
831 if (loaderparams.initrd_filename) {
832 initrd_size = get_image_size (loaderparams.initrd_filename);
833 if (initrd_size > 0) {
834 initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
835 if (initrd_offset + initrd_size > ram_size) {
836 fprintf(stderr,
837 "qemu: memory too small for initial ram disk '%s'\n",
838 loaderparams.initrd_filename);
839 exit(1);
840 }
841 initrd_size = load_image_targphys(loaderparams.initrd_filename,
842 initrd_offset,
843 ram_size - initrd_offset);
844 }
845 if (initrd_size == (target_ulong) -1) {
846 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
847 loaderparams.initrd_filename);
848 exit(1);
849 }
850 }
851
852
853 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
854 prom_buf = g_malloc(prom_size);
855
856 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
857 if (initrd_size > 0) {
858 prom_set(prom_buf, prom_index++, "rd_start=0x%" PRIx64 " rd_size=%li %s",
859 xlate_to_kseg0(NULL, initrd_offset), initrd_size,
860 loaderparams.kernel_cmdline);
861 } else {
862 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
863 }
864
865 prom_set(prom_buf, prom_index++, "memsize");
866 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size);
867
868 prom_set(prom_buf, prom_index++, "ememsize");
869 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size);
870
871 prom_set(prom_buf, prom_index++, "modetty0");
872 prom_set(prom_buf, prom_index++, "38400n8r");
873 prom_set(prom_buf, prom_index++, NULL);
874
875 rom_add_blob_fixed("prom", prom_buf, prom_size,
876 cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR));
877
878 g_free(prom_buf);
879 return kernel_entry;
880}
881
882static void malta_mips_config(MIPSCPU *cpu)
883{
884 CPUMIPSState *env = &cpu->env;
885 CPUState *cs = CPU(cpu);
886
887 env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
888 ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC);
889}
890
891static void main_cpu_reset(void *opaque)
892{
893 MIPSCPU *cpu = opaque;
894 CPUMIPSState *env = &cpu->env;
895
896 cpu_reset(CPU(cpu));
897
898
899
900
901 if (loaderparams.kernel_filename) {
902 env->CP0_Status &= ~(1 << CP0St_ERL);
903 }
904
905 malta_mips_config(cpu);
906
907 if (kvm_enabled()) {
908
909 env->active_tc.PC = 0x40000000 + loaderparams.ram_low_size;
910 }
911}
912
913static void create_cpu_without_cps(const char *cpu_model,
914 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
915{
916 CPUMIPSState *env;
917 MIPSCPU *cpu;
918 int i;
919
920 for (i = 0; i < smp_cpus; i++) {
921 cpu = cpu_mips_init(cpu_model);
922 if (cpu == NULL) {
923 fprintf(stderr, "Unable to find CPU definition\n");
924 exit(1);
925 }
926 env = &cpu->env;
927
928
929 cpu_mips_irq_init_cpu(env);
930 cpu_mips_clock_init(env);
931 qemu_register_reset(main_cpu_reset, cpu);
932 }
933
934 cpu = MIPS_CPU(first_cpu);
935 env = &cpu->env;
936 *i8259_irq = env->irq[2];
937 *cbus_irq = env->irq[4];
938}
939
940static void create_cps(MaltaState *s, const char *cpu_model,
941 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
942{
943 Error *err = NULL;
944 s->cps = g_new0(MIPSCPSState, 1);
945
946 object_initialize(s->cps, sizeof(MIPSCPSState), TYPE_MIPS_CPS);
947 qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
948
949 object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err);
950 object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
951 object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
952 if (err != NULL) {
953 error_report("%s", error_get_pretty(err));
954 exit(1);
955 }
956
957 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
958
959
960
961 *i8259_irq = get_cps_irq(s->cps, 2);
962 *cbus_irq = NULL;
963}
964
965static void create_cpu(MaltaState *s, const char *cpu_model,
966 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
967{
968 if (cpu_model == NULL) {
969#ifdef TARGET_MIPS64
970 cpu_model = "20Kc";
971#else
972 cpu_model = "24Kf";
973#endif
974 }
975
976 if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_model)) {
977 create_cps(s, cpu_model, cbus_irq, i8259_irq);
978 } else {
979 create_cpu_without_cps(cpu_model, cbus_irq, i8259_irq);
980 }
981}
982
983static
984void mips_malta_init(MachineState *machine)
985{
986 ram_addr_t ram_size = machine->ram_size;
987 ram_addr_t ram_low_size;
988 const char *kernel_filename = machine->kernel_filename;
989 const char *kernel_cmdline = machine->kernel_cmdline;
990 const char *initrd_filename = machine->initrd_filename;
991 char *filename;
992 pflash_t *fl;
993 MemoryRegion *system_memory = get_system_memory();
994 MemoryRegion *ram_high = g_new(MemoryRegion, 1);
995 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1);
996 MemoryRegion *ram_low_postio;
997 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
998 target_long bios_size = FLASH_SIZE;
999 const size_t smbus_eeprom_size = 8 * 256;
1000 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
1001 int64_t kernel_entry, bootloader_run_addr;
1002 PCIBus *pci_bus;
1003 ISABus *isa_bus;
1004 qemu_irq *isa_irq;
1005 qemu_irq cbus_irq, i8259_irq;
1006 int piix4_devfn;
1007 I2CBus *smbus;
1008 int i;
1009 DriveInfo *dinfo;
1010 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
1011 DriveInfo *fd[MAX_FD];
1012 int fl_idx = 0;
1013 int fl_sectors = bios_size >> 16;
1014 int be;
1015
1016 DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA);
1017 MaltaState *s = MIPS_MALTA(dev);
1018
1019
1020
1021
1022 empty_slot_init(0, 0x20000000);
1023
1024 qdev_init_nofail(dev);
1025
1026
1027 for(i = 0; i < 3; i++) {
1028 if (!serial_hds[i]) {
1029 char label[32];
1030 snprintf(label, sizeof(label), "serial%d", i);
1031 serial_hds[i] = qemu_chr_new(label, "null", NULL);
1032 }
1033 }
1034
1035
1036 create_cpu(s, machine->cpu_model, &cbus_irq, &i8259_irq);
1037
1038
1039 if (ram_size > (2048u << 20)) {
1040 fprintf(stderr,
1041 "qemu: Too much memory for this machine: %d MB, maximum 2048 MB\n",
1042 ((unsigned int)ram_size / (1 << 20)));
1043 exit(1);
1044 }
1045
1046
1047 memory_region_allocate_system_memory(ram_high, NULL, "mips_malta.ram",
1048 ram_size);
1049 memory_region_add_subregion(system_memory, 0x80000000, ram_high);
1050
1051
1052 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
1053 ram_high, 0, MIN(ram_size, (256 << 20)));
1054 memory_region_add_subregion(system_memory, 0, ram_low_preio);
1055
1056
1057 if (ram_size > (512 << 20)) {
1058 ram_low_postio = g_new(MemoryRegion, 1);
1059 memory_region_init_alias(ram_low_postio, NULL,
1060 "mips_malta_low_postio.ram",
1061 ram_high, 512 << 20,
1062 ram_size - (512 << 20));
1063 memory_region_add_subregion(system_memory, 512 << 20, ram_low_postio);
1064 }
1065
1066
1067 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
1068 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
1069
1070#ifdef TARGET_WORDS_BIGENDIAN
1071 be = 1;
1072#else
1073 be = 0;
1074#endif
1075
1076
1077 malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hds[2]);
1078
1079
1080 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
1081#ifdef DEBUG_BOARD_INIT
1082 if (dinfo) {
1083 printf("Register parallel flash %d size " TARGET_FMT_lx " at "
1084 "addr %08llx '%s' %x\n",
1085 fl_idx, bios_size, FLASH_ADDRESS,
1086 blk_name(dinfo->bdrv), fl_sectors);
1087 }
1088#endif
1089 fl = pflash_cfi01_register(FLASH_ADDRESS, NULL, "mips_malta.bios",
1090 BIOS_SIZE,
1091 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
1092 65536, fl_sectors,
1093 4, 0x0000, 0x0000, 0x0000, 0x0000, be);
1094 bios = pflash_cfi01_get_memory(fl);
1095 fl_idx++;
1096 if (kernel_filename) {
1097 ram_low_size = MIN(ram_size, 256 << 20);
1098
1099 if (kvm_enabled()) {
1100 ram_low_size -= 0x100000;
1101 bootloader_run_addr = 0x40000000 + ram_low_size;
1102 } else {
1103 bootloader_run_addr = 0xbfc00000;
1104 }
1105
1106
1107 loaderparams.ram_size = ram_size;
1108 loaderparams.ram_low_size = ram_low_size;
1109 loaderparams.kernel_filename = kernel_filename;
1110 loaderparams.kernel_cmdline = kernel_cmdline;
1111 loaderparams.initrd_filename = initrd_filename;
1112 kernel_entry = load_kernel();
1113
1114 write_bootloader(memory_region_get_ram_ptr(bios),
1115 bootloader_run_addr, kernel_entry);
1116 if (kvm_enabled()) {
1117
1118 write_bootloader(memory_region_get_ram_ptr(ram_low_preio) +
1119 ram_low_size,
1120 bootloader_run_addr, kernel_entry);
1121 }
1122 } else {
1123
1124 if (kvm_enabled()) {
1125 error_report("KVM enabled but no -kernel argument was specified. "
1126 "Booting from flash is not supported with KVM.");
1127 exit(1);
1128 }
1129
1130 if (!dinfo) {
1131
1132 if (bios_name == NULL) {
1133 bios_name = BIOS_FILENAME;
1134 }
1135 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1136 if (filename) {
1137 bios_size = load_image_targphys(filename, FLASH_ADDRESS,
1138 BIOS_SIZE);
1139 g_free(filename);
1140 } else {
1141 bios_size = -1;
1142 }
1143 if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
1144 !kernel_filename && !qtest_enabled()) {
1145 error_report("Could not load MIPS bios '%s', and no "
1146 "-kernel argument was specified", bios_name);
1147 exit(1);
1148 }
1149 }
1150
1151
1152#ifndef TARGET_WORDS_BIGENDIAN
1153 {
1154 uint32_t *end, *addr = rom_ptr(FLASH_ADDRESS);
1155 if (!addr) {
1156 addr = memory_region_get_ram_ptr(bios);
1157 }
1158 end = (void *)addr + MIN(bios_size, 0x3e0000);
1159 while (addr < end) {
1160 bswap32s(addr);
1161 addr++;
1162 }
1163 }
1164#endif
1165 }
1166
1167
1168
1169
1170
1171
1172
1173 memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
1174 &error_fatal);
1175 if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
1176 FLASH_ADDRESS, BIOS_SIZE)) {
1177 memcpy(memory_region_get_ram_ptr(bios_copy),
1178 memory_region_get_ram_ptr(bios), BIOS_SIZE);
1179 }
1180 memory_region_set_readonly(bios_copy, true);
1181 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy);
1182
1183
1184 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
1185
1186
1187
1188
1189
1190
1191
1192
1193 isa_irq = qemu_irq_proxy(&s->i8259, 16);
1194
1195
1196 pci_bus = gt64120_register(isa_irq);
1197
1198
1199 ide_drive_get(hd, ARRAY_SIZE(hd));
1200
1201 piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
1202
1203
1204
1205 s->i8259 = i8259_init(isa_bus, i8259_irq);
1206
1207 isa_bus_irqs(isa_bus, s->i8259);
1208 pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
1209 pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
1210 smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
1211 isa_get_irq(NULL, 9), NULL, 0, NULL);
1212 smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
1213 g_free(smbus_eeprom_buf);
1214 pit = pit_init(isa_bus, 0x40, 0, NULL);
1215 DMA_init(isa_bus, 0);
1216
1217
1218 isa_create_simple(isa_bus, "i8042");
1219
1220 rtc_init(isa_bus, 2000, NULL);
1221 serial_hds_isa_init(isa_bus, 2);
1222 parallel_hds_isa_init(isa_bus, 1);
1223
1224 for(i = 0; i < MAX_FD; i++) {
1225 fd[i] = drive_get(IF_FLOPPY, 0, i);
1226 }
1227 fdctrl_init_isa(isa_bus, fd);
1228
1229
1230 network_init(pci_bus);
1231
1232
1233 pci_vga_init(pci_bus);
1234}
1235
1236static int mips_malta_sysbus_device_init(SysBusDevice *sysbusdev)
1237{
1238 return 0;
1239}
1240
1241static void mips_malta_class_init(ObjectClass *klass, void *data)
1242{
1243 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1244
1245 k->init = mips_malta_sysbus_device_init;
1246}
1247
1248static const TypeInfo mips_malta_device = {
1249 .name = TYPE_MIPS_MALTA,
1250 .parent = TYPE_SYS_BUS_DEVICE,
1251 .instance_size = sizeof(MaltaState),
1252 .class_init = mips_malta_class_init,
1253};
1254
1255static void mips_malta_machine_init(MachineClass *mc)
1256{
1257 mc->desc = "MIPS Malta Core LV";
1258 mc->init = mips_malta_init;
1259 mc->max_cpus = 16;
1260 mc->is_default = 1;
1261}
1262
1263DEFINE_MACHINE("malta", mips_malta_machine_init)
1264
1265static void mips_malta_register_types(void)
1266{
1267 type_register_static(&mips_malta_device);
1268}
1269
1270type_init(mips_malta_register_types)
1271