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25#include "qemu/osdep.h"
26#include <zlib.h>
27
28#include "hw/net/cadence_gem.h"
29#include "net/checksum.h"
30
31#ifdef CADENCE_GEM_ERR_DEBUG
32#define DB_PRINT(...) do { \
33 fprintf(stderr, ": %s: ", __func__); \
34 fprintf(stderr, ## __VA_ARGS__); \
35 } while (0);
36#else
37 #define DB_PRINT(...)
38#endif
39
40#define GEM_NWCTRL (0x00000000/4)
41#define GEM_NWCFG (0x00000004/4)
42#define GEM_NWSTATUS (0x00000008/4)
43#define GEM_USERIO (0x0000000C/4)
44#define GEM_DMACFG (0x00000010/4)
45#define GEM_TXSTATUS (0x00000014/4)
46#define GEM_RXQBASE (0x00000018/4)
47#define GEM_TXQBASE (0x0000001C/4)
48#define GEM_RXSTATUS (0x00000020/4)
49#define GEM_ISR (0x00000024/4)
50#define GEM_IER (0x00000028/4)
51#define GEM_IDR (0x0000002C/4)
52#define GEM_IMR (0x00000030/4)
53#define GEM_PHYMNTNC (0x00000034/4)
54#define GEM_RXPAUSE (0x00000038/4)
55#define GEM_TXPAUSE (0x0000003C/4)
56#define GEM_TXPARTIALSF (0x00000040/4)
57#define GEM_RXPARTIALSF (0x00000044/4)
58#define GEM_HASHLO (0x00000080/4)
59#define GEM_HASHHI (0x00000084/4)
60#define GEM_SPADDR1LO (0x00000088/4)
61#define GEM_SPADDR1HI (0x0000008C/4)
62#define GEM_SPADDR2LO (0x00000090/4)
63#define GEM_SPADDR2HI (0x00000094/4)
64#define GEM_SPADDR3LO (0x00000098/4)
65#define GEM_SPADDR3HI (0x0000009C/4)
66#define GEM_SPADDR4LO (0x000000A0/4)
67#define GEM_SPADDR4HI (0x000000A4/4)
68#define GEM_TIDMATCH1 (0x000000A8/4)
69#define GEM_TIDMATCH2 (0x000000AC/4)
70#define GEM_TIDMATCH3 (0x000000B0/4)
71#define GEM_TIDMATCH4 (0x000000B4/4)
72#define GEM_WOLAN (0x000000B8/4)
73#define GEM_IPGSTRETCH (0x000000BC/4)
74#define GEM_SVLAN (0x000000C0/4)
75#define GEM_MODID (0x000000FC/4)
76#define GEM_OCTTXLO (0x00000100/4)
77#define GEM_OCTTXHI (0x00000104/4)
78#define GEM_TXCNT (0x00000108/4)
79#define GEM_TXBCNT (0x0000010C/4)
80#define GEM_TXMCNT (0x00000110/4)
81#define GEM_TXPAUSECNT (0x00000114/4)
82#define GEM_TX64CNT (0x00000118/4)
83#define GEM_TX65CNT (0x0000011C/4)
84#define GEM_TX128CNT (0x00000120/4)
85#define GEM_TX256CNT (0x00000124/4)
86#define GEM_TX512CNT (0x00000128/4)
87#define GEM_TX1024CNT (0x0000012C/4)
88#define GEM_TX1519CNT (0x00000130/4)
89#define GEM_TXURUNCNT (0x00000134/4)
90#define GEM_SINGLECOLLCNT (0x00000138/4)
91#define GEM_MULTCOLLCNT (0x0000013C/4)
92#define GEM_EXCESSCOLLCNT (0x00000140/4)
93#define GEM_LATECOLLCNT (0x00000144/4)
94#define GEM_DEFERTXCNT (0x00000148/4)
95#define GEM_CSENSECNT (0x0000014C/4)
96#define GEM_OCTRXLO (0x00000150/4)
97#define GEM_OCTRXHI (0x00000154/4)
98#define GEM_RXCNT (0x00000158/4)
99#define GEM_RXBROADCNT (0x0000015C/4)
100#define GEM_RXMULTICNT (0x00000160/4)
101#define GEM_RXPAUSECNT (0x00000164/4)
102#define GEM_RX64CNT (0x00000168/4)
103#define GEM_RX65CNT (0x0000016C/4)
104#define GEM_RX128CNT (0x00000170/4)
105#define GEM_RX256CNT (0x00000174/4)
106#define GEM_RX512CNT (0x00000178/4)
107#define GEM_RX1024CNT (0x0000017C/4)
108#define GEM_RX1519CNT (0x00000180/4)
109#define GEM_RXUNDERCNT (0x00000184/4)
110#define GEM_RXOVERCNT (0x00000188/4)
111#define GEM_RXJABCNT (0x0000018C/4)
112#define GEM_RXFCSCNT (0x00000190/4)
113#define GEM_RXLENERRCNT (0x00000194/4)
114#define GEM_RXSYMERRCNT (0x00000198/4)
115#define GEM_RXALIGNERRCNT (0x0000019C/4)
116#define GEM_RXRSCERRCNT (0x000001A0/4)
117#define GEM_RXORUNCNT (0x000001A4/4)
118#define GEM_RXIPCSERRCNT (0x000001A8/4)
119#define GEM_RXTCPCCNT (0x000001AC/4)
120#define GEM_RXUDPCCNT (0x000001B0/4)
121
122#define GEM_1588S (0x000001D0/4)
123#define GEM_1588NS (0x000001D4/4)
124#define GEM_1588ADJ (0x000001D8/4)
125#define GEM_1588INC (0x000001DC/4)
126#define GEM_PTPETXS (0x000001E0/4)
127#define GEM_PTPETXNS (0x000001E4/4)
128#define GEM_PTPERXS (0x000001E8/4)
129#define GEM_PTPERXNS (0x000001EC/4)
130#define GEM_PTPPTXS (0x000001E0/4)
131#define GEM_PTPPTXNS (0x000001E4/4)
132#define GEM_PTPPRXS (0x000001E8/4)
133#define GEM_PTPPRXNS (0x000001EC/4)
134
135
136#define GEM_DESCONF (0x00000280/4)
137#define GEM_DESCONF2 (0x00000284/4)
138#define GEM_DESCONF3 (0x00000288/4)
139#define GEM_DESCONF4 (0x0000028C/4)
140#define GEM_DESCONF5 (0x00000290/4)
141#define GEM_DESCONF6 (0x00000294/4)
142#define GEM_DESCONF7 (0x00000298/4)
143
144
145#define GEM_NWCTRL_TXSTART 0x00000200
146#define GEM_NWCTRL_TXENA 0x00000008
147#define GEM_NWCTRL_RXENA 0x00000004
148#define GEM_NWCTRL_LOCALLOOP 0x00000002
149
150#define GEM_NWCFG_STRIP_FCS 0x00020000
151#define GEM_NWCFG_LERR_DISC 0x00010000
152#define GEM_NWCFG_BUFF_OFST_M 0x0000C000
153#define GEM_NWCFG_BUFF_OFST_S 14
154#define GEM_NWCFG_UCAST_HASH 0x00000080
155#define GEM_NWCFG_MCAST_HASH 0x00000040
156#define GEM_NWCFG_BCAST_REJ 0x00000020
157#define GEM_NWCFG_PROMISC 0x00000010
158
159#define GEM_DMACFG_RBUFSZ_M 0x00FF0000
160#define GEM_DMACFG_RBUFSZ_S 16
161#define GEM_DMACFG_RBUFSZ_MUL 64
162#define GEM_DMACFG_TXCSUM_OFFL 0x00000800
163
164#define GEM_TXSTATUS_TXCMPL 0x00000020
165#define GEM_TXSTATUS_USED 0x00000001
166
167#define GEM_RXSTATUS_FRMRCVD 0x00000002
168#define GEM_RXSTATUS_NOBUF 0x00000001
169
170
171#define GEM_INT_TXCMPL 0x00000080
172#define GEM_INT_TXUSED 0x00000008
173#define GEM_INT_RXUSED 0x00000004
174#define GEM_INT_RXCMPL 0x00000002
175
176#define GEM_PHYMNTNC_OP_R 0x20000000
177#define GEM_PHYMNTNC_OP_W 0x10000000
178#define GEM_PHYMNTNC_ADDR 0x0F800000
179#define GEM_PHYMNTNC_ADDR_SHFT 23
180#define GEM_PHYMNTNC_REG 0x007C0000
181#define GEM_PHYMNTNC_REG_SHIFT 18
182
183
184#define BOARD_PHY_ADDRESS 23
185
186#define PHY_REG_CONTROL 0
187#define PHY_REG_STATUS 1
188#define PHY_REG_PHYID1 2
189#define PHY_REG_PHYID2 3
190#define PHY_REG_ANEGADV 4
191#define PHY_REG_LINKPABIL 5
192#define PHY_REG_ANEGEXP 6
193#define PHY_REG_NEXTP 7
194#define PHY_REG_LINKPNEXTP 8
195#define PHY_REG_100BTCTRL 9
196#define PHY_REG_1000BTSTAT 10
197#define PHY_REG_EXTSTAT 15
198#define PHY_REG_PHYSPCFC_CTL 16
199#define PHY_REG_PHYSPCFC_ST 17
200#define PHY_REG_INT_EN 18
201#define PHY_REG_INT_ST 19
202#define PHY_REG_EXT_PHYSPCFC_CTL 20
203#define PHY_REG_RXERR 21
204#define PHY_REG_EACD 22
205#define PHY_REG_LED 24
206#define PHY_REG_LED_OVRD 25
207#define PHY_REG_EXT_PHYSPCFC_CTL2 26
208#define PHY_REG_EXT_PHYSPCFC_ST 27
209#define PHY_REG_CABLE_DIAG 28
210
211#define PHY_REG_CONTROL_RST 0x8000
212#define PHY_REG_CONTROL_LOOP 0x4000
213#define PHY_REG_CONTROL_ANEG 0x1000
214
215#define PHY_REG_STATUS_LINK 0x0004
216#define PHY_REG_STATUS_ANEGCMPL 0x0020
217
218#define PHY_REG_INT_ST_ANEGCMPL 0x0800
219#define PHY_REG_INT_ST_LINKC 0x0400
220#define PHY_REG_INT_ST_ENERGY 0x0010
221
222
223#define GEM_RX_REJECT (-1)
224#define GEM_RX_PROMISCUOUS_ACCEPT (-2)
225#define GEM_RX_BROADCAST_ACCEPT (-3)
226#define GEM_RX_MULTICAST_HASH_ACCEPT (-4)
227#define GEM_RX_UNICAST_HASH_ACCEPT (-5)
228
229#define GEM_RX_SAR_ACCEPT 0
230
231
232
233#define DESC_1_USED 0x80000000
234#define DESC_1_LENGTH 0x00001FFF
235
236#define DESC_1_TX_WRAP 0x40000000
237#define DESC_1_TX_LAST 0x00008000
238
239#define DESC_0_RX_WRAP 0x00000002
240#define DESC_0_RX_OWNERSHIP 0x00000001
241
242#define R_DESC_1_RX_SAR_SHIFT 25
243#define R_DESC_1_RX_SAR_LENGTH 2
244#define R_DESC_1_RX_SAR_MATCH (1 << 27)
245#define R_DESC_1_RX_UNICAST_HASH (1 << 29)
246#define R_DESC_1_RX_MULTICAST_HASH (1 << 30)
247#define R_DESC_1_RX_BROADCAST (1 << 31)
248
249#define DESC_1_RX_SOF 0x00004000
250#define DESC_1_RX_EOF 0x00008000
251
252static inline unsigned tx_desc_get_buffer(unsigned *desc)
253{
254 return desc[0];
255}
256
257static inline unsigned tx_desc_get_used(unsigned *desc)
258{
259 return (desc[1] & DESC_1_USED) ? 1 : 0;
260}
261
262static inline void tx_desc_set_used(unsigned *desc)
263{
264 desc[1] |= DESC_1_USED;
265}
266
267static inline unsigned tx_desc_get_wrap(unsigned *desc)
268{
269 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0;
270}
271
272static inline unsigned tx_desc_get_last(unsigned *desc)
273{
274 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
275}
276
277static inline unsigned tx_desc_get_length(unsigned *desc)
278{
279 return desc[1] & DESC_1_LENGTH;
280}
281
282static inline void print_gem_tx_desc(unsigned *desc)
283{
284 DB_PRINT("TXDESC:\n");
285 DB_PRINT("bufaddr: 0x%08x\n", *desc);
286 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc));
287 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc));
288 DB_PRINT("last: %d\n", tx_desc_get_last(desc));
289 DB_PRINT("length: %d\n", tx_desc_get_length(desc));
290}
291
292static inline unsigned rx_desc_get_buffer(unsigned *desc)
293{
294 return desc[0] & ~0x3UL;
295}
296
297static inline unsigned rx_desc_get_wrap(unsigned *desc)
298{
299 return desc[0] & DESC_0_RX_WRAP ? 1 : 0;
300}
301
302static inline unsigned rx_desc_get_ownership(unsigned *desc)
303{
304 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0;
305}
306
307static inline void rx_desc_set_ownership(unsigned *desc)
308{
309 desc[0] |= DESC_0_RX_OWNERSHIP;
310}
311
312static inline void rx_desc_set_sof(unsigned *desc)
313{
314 desc[1] |= DESC_1_RX_SOF;
315}
316
317static inline void rx_desc_set_eof(unsigned *desc)
318{
319 desc[1] |= DESC_1_RX_EOF;
320}
321
322static inline void rx_desc_set_length(unsigned *desc, unsigned len)
323{
324 desc[1] &= ~DESC_1_LENGTH;
325 desc[1] |= len;
326}
327
328static inline void rx_desc_set_broadcast(unsigned *desc)
329{
330 desc[1] |= R_DESC_1_RX_BROADCAST;
331}
332
333static inline void rx_desc_set_unicast_hash(unsigned *desc)
334{
335 desc[1] |= R_DESC_1_RX_UNICAST_HASH;
336}
337
338static inline void rx_desc_set_multicast_hash(unsigned *desc)
339{
340 desc[1] |= R_DESC_1_RX_MULTICAST_HASH;
341}
342
343static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
344{
345 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH,
346 sar_idx);
347 desc[1] |= R_DESC_1_RX_SAR_MATCH;
348}
349
350
351static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
352
353
354
355
356
357
358static void gem_init_register_masks(CadenceGEMState *s)
359{
360
361 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
362 s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
363 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
364 s->regs_ro[GEM_DMACFG] = 0xFE00F000;
365 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
366 s->regs_ro[GEM_RXQBASE] = 0x00000003;
367 s->regs_ro[GEM_TXQBASE] = 0x00000003;
368 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
369 s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
370 s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
371 s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
372
373
374 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
375 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
376
377
378 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
379 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
380 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
381
382
383 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
384 s->regs_wo[GEM_NWCTRL] = 0x00073E60;
385 s->regs_wo[GEM_IER] = 0x07FFFFFF;
386 s->regs_wo[GEM_IDR] = 0x07FFFFFF;
387}
388
389
390
391
392
393static void phy_update_link(CadenceGEMState *s)
394{
395 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
396
397
398 if (qemu_get_queue(s->nic)->link_down) {
399 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL |
400 PHY_REG_STATUS_LINK);
401 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC;
402 } else {
403 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL |
404 PHY_REG_STATUS_LINK);
405 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC |
406 PHY_REG_INT_ST_ANEGCMPL |
407 PHY_REG_INT_ST_ENERGY);
408 }
409}
410
411static int gem_can_receive(NetClientState *nc)
412{
413 CadenceGEMState *s;
414
415 s = qemu_get_nic_opaque(nc);
416
417
418 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
419 if (s->can_rx_state != 1) {
420 s->can_rx_state = 1;
421 DB_PRINT("can't receive - no enable\n");
422 }
423 return 0;
424 }
425
426 if (rx_desc_get_ownership(s->rx_desc) == 1) {
427 if (s->can_rx_state != 2) {
428 s->can_rx_state = 2;
429 DB_PRINT("can't receive - busy buffer descriptor 0x%x\n",
430 s->rx_desc_addr);
431 }
432 return 0;
433 }
434
435 if (s->can_rx_state != 0) {
436 s->can_rx_state = 0;
437 DB_PRINT("can receive 0x%x\n", s->rx_desc_addr);
438 }
439 return 1;
440}
441
442
443
444
445
446static void gem_update_int_status(CadenceGEMState *s)
447{
448 if (s->regs[GEM_ISR]) {
449 DB_PRINT("asserting int. (0x%08x)\n", s->regs[GEM_ISR]);
450 qemu_set_irq(s->irq, 1);
451 }
452}
453
454
455
456
457
458static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
459 unsigned bytes)
460{
461 uint64_t octets;
462
463
464 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
465 s->regs[GEM_OCTRXHI];
466 octets += bytes;
467 s->regs[GEM_OCTRXLO] = octets >> 32;
468 s->regs[GEM_OCTRXHI] = octets;
469
470
471 s->regs[GEM_RXCNT]++;
472
473
474 if (!memcmp(packet, broadcast_addr, 6)) {
475 s->regs[GEM_RXBROADCNT]++;
476 }
477
478
479 if (packet[0] == 0x01) {
480 s->regs[GEM_RXMULTICNT]++;
481 }
482
483 if (bytes <= 64) {
484 s->regs[GEM_RX64CNT]++;
485 } else if (bytes <= 127) {
486 s->regs[GEM_RX65CNT]++;
487 } else if (bytes <= 255) {
488 s->regs[GEM_RX128CNT]++;
489 } else if (bytes <= 511) {
490 s->regs[GEM_RX256CNT]++;
491 } else if (bytes <= 1023) {
492 s->regs[GEM_RX512CNT]++;
493 } else if (bytes <= 1518) {
494 s->regs[GEM_RX1024CNT]++;
495 } else {
496 s->regs[GEM_RX1519CNT]++;
497 }
498}
499
500
501
502
503static unsigned get_bit(const uint8_t *mac, unsigned bit)
504{
505 unsigned byte;
506
507 byte = mac[bit / 8];
508 byte >>= (bit & 0x7);
509 byte &= 1;
510
511 return byte;
512}
513
514
515
516
517static unsigned calc_mac_hash(const uint8_t *mac)
518{
519 int index_bit, mac_bit;
520 unsigned hash_index;
521
522 hash_index = 0;
523 mac_bit = 5;
524 for (index_bit = 5; index_bit >= 0; index_bit--) {
525 hash_index |= (get_bit(mac, mac_bit) ^
526 get_bit(mac, mac_bit + 6) ^
527 get_bit(mac, mac_bit + 12) ^
528 get_bit(mac, mac_bit + 18) ^
529 get_bit(mac, mac_bit + 24) ^
530 get_bit(mac, mac_bit + 30) ^
531 get_bit(mac, mac_bit + 36) ^
532 get_bit(mac, mac_bit + 42)) << index_bit;
533 mac_bit--;
534 }
535
536 return hash_index;
537}
538
539
540
541
542
543
544
545
546
547
548
549static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
550{
551 uint8_t *gem_spaddr;
552 int i;
553
554
555 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
556 return GEM_RX_PROMISCUOUS_ACCEPT;
557 }
558
559 if (!memcmp(packet, broadcast_addr, 6)) {
560
561 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
562 return GEM_RX_REJECT;
563 }
564 return GEM_RX_BROADCAST_ACCEPT;
565 }
566
567
568 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
569 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
570 unsigned hash_index;
571
572 hash_index = calc_mac_hash(packet);
573 if (hash_index < 32) {
574 if (s->regs[GEM_HASHLO] & (1<<hash_index)) {
575 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
576 GEM_RX_UNICAST_HASH_ACCEPT;
577 }
578 } else {
579 hash_index -= 32;
580 if (s->regs[GEM_HASHHI] & (1<<hash_index)) {
581 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
582 GEM_RX_UNICAST_HASH_ACCEPT;
583 }
584 }
585 }
586
587
588 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
589 for (i = 3; i >= 0; i--) {
590 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
591 return GEM_RX_SAR_ACCEPT + i;
592 }
593 }
594
595
596 return GEM_RX_REJECT;
597}
598
599static void gem_get_rx_desc(CadenceGEMState *s)
600{
601 DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr);
602
603 cpu_physical_memory_read(s->rx_desc_addr,
604 (uint8_t *)s->rx_desc, sizeof(s->rx_desc));
605
606
607 if (rx_desc_get_ownership(s->rx_desc) == 1) {
608 DB_PRINT("descriptor 0x%x owned by sw.\n",
609 (unsigned)s->rx_desc_addr);
610 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
611 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
612
613 gem_update_int_status(s);
614 }
615}
616
617
618
619
620
621static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
622{
623 CadenceGEMState *s;
624 unsigned rxbufsize, bytes_to_copy;
625 unsigned rxbuf_offset;
626 uint8_t rxbuf[2048];
627 uint8_t *rxbuf_ptr;
628 bool first_desc = true;
629 int maf;
630
631 s = qemu_get_nic_opaque(nc);
632
633
634 maf = gem_mac_address_filter(s, buf);
635 if (maf == GEM_RX_REJECT) {
636 return -1;
637 }
638
639
640 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
641 unsigned type_len;
642
643
644 type_len = buf[12] << 8 | buf[13];
645
646 if (type_len < 0x600) {
647 if (size < type_len) {
648
649 return -1;
650 }
651 }
652 }
653
654
655
656
657 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
658 GEM_NWCFG_BUFF_OFST_S;
659
660
661
662
663 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
664 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
665 bytes_to_copy = size;
666
667
668
669
670
671 if (size < 60) {
672 size = 60;
673 }
674
675
676 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
677 rxbuf_ptr = (void *)buf;
678 } else {
679 unsigned crc_val;
680
681 if (size > sizeof(rxbuf) - sizeof(crc_val)) {
682 size = sizeof(rxbuf) - sizeof(crc_val);
683 }
684 bytes_to_copy = size;
685
686
687
688
689 memcpy(rxbuf, buf, size);
690 memset(rxbuf + size, 0, sizeof(rxbuf) - size);
691 rxbuf_ptr = rxbuf;
692 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
693 memcpy(rxbuf + size, &crc_val, sizeof(crc_val));
694
695 bytes_to_copy += 4;
696 size += 4;
697 }
698
699 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size);
700
701 while (bytes_to_copy) {
702
703 if (!gem_can_receive(nc)) {
704 assert(!first_desc);
705 return -1;
706 }
707
708 DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize),
709 rx_desc_get_buffer(s->rx_desc));
710
711
712 cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc) + rxbuf_offset,
713 rxbuf_ptr, MIN(bytes_to_copy, rxbufsize));
714 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
715 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
716
717
718 if (first_desc) {
719 rx_desc_set_sof(s->rx_desc);
720 first_desc = false;
721 }
722 if (bytes_to_copy == 0) {
723 rx_desc_set_eof(s->rx_desc);
724 rx_desc_set_length(s->rx_desc, size);
725 }
726 rx_desc_set_ownership(s->rx_desc);
727
728 switch (maf) {
729 case GEM_RX_PROMISCUOUS_ACCEPT:
730 break;
731 case GEM_RX_BROADCAST_ACCEPT:
732 rx_desc_set_broadcast(s->rx_desc);
733 break;
734 case GEM_RX_UNICAST_HASH_ACCEPT:
735 rx_desc_set_unicast_hash(s->rx_desc);
736 break;
737 case GEM_RX_MULTICAST_HASH_ACCEPT:
738 rx_desc_set_multicast_hash(s->rx_desc);
739 break;
740 case GEM_RX_REJECT:
741 abort();
742 default:
743 rx_desc_set_sar(s->rx_desc, maf);
744 }
745
746
747 cpu_physical_memory_write(s->rx_desc_addr,
748 (uint8_t *)s->rx_desc, sizeof(s->rx_desc));
749
750
751 if (rx_desc_get_wrap(s->rx_desc)) {
752 DB_PRINT("wrapping RX descriptor list\n");
753 s->rx_desc_addr = s->regs[GEM_RXQBASE];
754 } else {
755 DB_PRINT("incrementing RX descriptor list\n");
756 s->rx_desc_addr += 8;
757 }
758 gem_get_rx_desc(s);
759 }
760
761
762 gem_receive_updatestats(s, buf, size);
763
764 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
765 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]);
766
767
768 gem_update_int_status(s);
769
770 return size;
771}
772
773
774
775
776
777static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
778 unsigned bytes)
779{
780 uint64_t octets;
781
782
783 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
784 s->regs[GEM_OCTTXHI];
785 octets += bytes;
786 s->regs[GEM_OCTTXLO] = octets >> 32;
787 s->regs[GEM_OCTTXHI] = octets;
788
789
790 s->regs[GEM_TXCNT]++;
791
792
793 if (!memcmp(packet, broadcast_addr, 6)) {
794 s->regs[GEM_TXBCNT]++;
795 }
796
797
798 if (packet[0] == 0x01) {
799 s->regs[GEM_TXMCNT]++;
800 }
801
802 if (bytes <= 64) {
803 s->regs[GEM_TX64CNT]++;
804 } else if (bytes <= 127) {
805 s->regs[GEM_TX65CNT]++;
806 } else if (bytes <= 255) {
807 s->regs[GEM_TX128CNT]++;
808 } else if (bytes <= 511) {
809 s->regs[GEM_TX256CNT]++;
810 } else if (bytes <= 1023) {
811 s->regs[GEM_TX512CNT]++;
812 } else if (bytes <= 1518) {
813 s->regs[GEM_TX1024CNT]++;
814 } else {
815 s->regs[GEM_TX1519CNT]++;
816 }
817}
818
819
820
821
822
823static void gem_transmit(CadenceGEMState *s)
824{
825 unsigned desc[2];
826 hwaddr packet_desc_addr;
827 uint8_t tx_packet[2048];
828 uint8_t *p;
829 unsigned total_bytes;
830
831
832 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
833 return;
834 }
835
836 DB_PRINT("\n");
837
838
839
840
841
842 p = tx_packet;
843 total_bytes = 0;
844
845
846 packet_desc_addr = s->tx_desc_addr;
847
848 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
849 cpu_physical_memory_read(packet_desc_addr,
850 (uint8_t *)desc, sizeof(desc));
851
852 while (tx_desc_get_used(desc) == 0) {
853
854
855 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
856 return;
857 }
858 print_gem_tx_desc(desc);
859
860
861
862
863 if ((tx_desc_get_buffer(desc) == 0) ||
864 (tx_desc_get_length(desc) == 0)) {
865 DB_PRINT("Invalid TX descriptor @ 0x%x\n",
866 (unsigned)packet_desc_addr);
867 break;
868 }
869
870 if (tx_desc_get_length(desc) > sizeof(tx_packet) - (p - tx_packet)) {
871 DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space 0x%x\n",
872 (unsigned)packet_desc_addr,
873 (unsigned)tx_desc_get_length(desc),
874 sizeof(tx_packet) - (p - tx_packet));
875 break;
876 }
877
878
879
880
881 cpu_physical_memory_read(tx_desc_get_buffer(desc), p,
882 tx_desc_get_length(desc));
883 p += tx_desc_get_length(desc);
884 total_bytes += tx_desc_get_length(desc);
885
886
887 if (tx_desc_get_last(desc)) {
888 unsigned desc_first[2];
889
890
891
892
893 cpu_physical_memory_read(s->tx_desc_addr, (uint8_t *)desc_first,
894 sizeof(desc_first));
895 tx_desc_set_used(desc_first);
896 cpu_physical_memory_write(s->tx_desc_addr, (uint8_t *)desc_first,
897 sizeof(desc_first));
898
899 if (tx_desc_get_wrap(desc)) {
900 s->tx_desc_addr = s->regs[GEM_TXQBASE];
901 } else {
902 s->tx_desc_addr = packet_desc_addr + 8;
903 }
904 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr);
905
906 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
907 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
908
909
910 gem_update_int_status(s);
911
912
913 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
914 net_checksum_calculate(tx_packet, total_bytes);
915 }
916
917
918 gem_transmit_updatestats(s, tx_packet, total_bytes);
919
920
921 if (s->phy_loop || (s->regs[GEM_NWCTRL] & GEM_NWCTRL_LOCALLOOP)) {
922 gem_receive(qemu_get_queue(s->nic), tx_packet, total_bytes);
923 } else {
924 qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
925 total_bytes);
926 }
927
928
929 p = tx_packet;
930 total_bytes = 0;
931 }
932
933
934 if (tx_desc_get_wrap(desc)) {
935 packet_desc_addr = s->regs[GEM_TXQBASE];
936 } else {
937 packet_desc_addr += 8;
938 }
939 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
940 cpu_physical_memory_read(packet_desc_addr,
941 (uint8_t *)desc, sizeof(desc));
942 }
943
944 if (tx_desc_get_used(desc)) {
945 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
946 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
947 gem_update_int_status(s);
948 }
949}
950
951static void gem_phy_reset(CadenceGEMState *s)
952{
953 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
954 s->phy_regs[PHY_REG_CONTROL] = 0x1140;
955 s->phy_regs[PHY_REG_STATUS] = 0x7969;
956 s->phy_regs[PHY_REG_PHYID1] = 0x0141;
957 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2;
958 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1;
959 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1;
960 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F;
961 s->phy_regs[PHY_REG_NEXTP] = 0x2001;
962 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6;
963 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300;
964 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
965 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
966 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
967 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
968 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
969 s->phy_regs[PHY_REG_LED] = 0x4100;
970 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
971 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B;
972
973 phy_update_link(s);
974}
975
976static void gem_reset(DeviceState *d)
977{
978 int i;
979 CadenceGEMState *s = CADENCE_GEM(d);
980 const uint8_t *a;
981
982 DB_PRINT("\n");
983
984
985 memset(&s->regs[0], 0, sizeof(s->regs));
986 s->regs[GEM_NWCFG] = 0x00080000;
987 s->regs[GEM_NWSTATUS] = 0x00000006;
988 s->regs[GEM_DMACFG] = 0x00020784;
989 s->regs[GEM_IMR] = 0x07ffffff;
990 s->regs[GEM_TXPAUSE] = 0x0000ffff;
991 s->regs[GEM_TXPARTIALSF] = 0x000003ff;
992 s->regs[GEM_RXPARTIALSF] = 0x000003ff;
993 s->regs[GEM_MODID] = 0x00020118;
994 s->regs[GEM_DESCONF] = 0x02500111;
995 s->regs[GEM_DESCONF2] = 0x2ab13fff;
996 s->regs[GEM_DESCONF5] = 0x002f2145;
997 s->regs[GEM_DESCONF6] = 0x00000200;
998
999
1000 a = &s->conf.macaddr.a[0];
1001 s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
1002 s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8);
1003
1004 for (i = 0; i < 4; i++) {
1005 s->sar_active[i] = false;
1006 }
1007
1008 gem_phy_reset(s);
1009
1010 gem_update_int_status(s);
1011}
1012
1013static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num)
1014{
1015 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]);
1016 return s->phy_regs[reg_num];
1017}
1018
1019static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
1020{
1021 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val);
1022
1023 switch (reg_num) {
1024 case PHY_REG_CONTROL:
1025 if (val & PHY_REG_CONTROL_RST) {
1026
1027 gem_phy_reset(s);
1028 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP);
1029 s->phy_loop = 0;
1030 }
1031 if (val & PHY_REG_CONTROL_ANEG) {
1032
1033 val &= ~PHY_REG_CONTROL_ANEG;
1034 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
1035 }
1036 if (val & PHY_REG_CONTROL_LOOP) {
1037 DB_PRINT("PHY placed in loopback\n");
1038 s->phy_loop = 1;
1039 } else {
1040 s->phy_loop = 0;
1041 }
1042 break;
1043 }
1044 s->phy_regs[reg_num] = val;
1045}
1046
1047
1048
1049
1050
1051static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
1052{
1053 CadenceGEMState *s;
1054 uint32_t retval;
1055
1056 s = (CadenceGEMState *)opaque;
1057
1058 offset >>= 2;
1059 retval = s->regs[offset];
1060
1061 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
1062
1063 switch (offset) {
1064 case GEM_ISR:
1065 DB_PRINT("lowering irq on ISR read\n");
1066 qemu_set_irq(s->irq, 0);
1067 break;
1068 case GEM_PHYMNTNC:
1069 if (retval & GEM_PHYMNTNC_OP_R) {
1070 uint32_t phy_addr, reg_num;
1071
1072 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1073 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1074 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1075 retval &= 0xFFFF0000;
1076 retval |= gem_phy_read(s, reg_num);
1077 } else {
1078 retval |= 0xFFFF;
1079 }
1080 }
1081 break;
1082 }
1083
1084
1085 s->regs[offset] &= ~(s->regs_rtc[offset]);
1086
1087
1088 retval &= ~(s->regs_wo[offset]);
1089
1090 DB_PRINT("0x%08x\n", retval);
1091 return retval;
1092}
1093
1094
1095
1096
1097
1098static void gem_write(void *opaque, hwaddr offset, uint64_t val,
1099 unsigned size)
1100{
1101 CadenceGEMState *s = (CadenceGEMState *)opaque;
1102 uint32_t readonly;
1103
1104 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
1105 offset >>= 2;
1106
1107
1108 val &= ~(s->regs_ro[offset]);
1109
1110 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]);
1111
1112
1113 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly;
1114
1115
1116 s->regs[offset] &= ~(s->regs_w1c[offset] & val);
1117
1118
1119 switch (offset) {
1120 case GEM_NWCTRL:
1121 if (val & GEM_NWCTRL_RXENA) {
1122 gem_get_rx_desc(s);
1123 }
1124 if (val & GEM_NWCTRL_TXSTART) {
1125 gem_transmit(s);
1126 }
1127 if (!(val & GEM_NWCTRL_TXENA)) {
1128
1129 s->tx_desc_addr = s->regs[GEM_TXQBASE];
1130 }
1131 if (gem_can_receive(qemu_get_queue(s->nic))) {
1132 qemu_flush_queued_packets(qemu_get_queue(s->nic));
1133 }
1134 break;
1135
1136 case GEM_TXSTATUS:
1137 gem_update_int_status(s);
1138 break;
1139 case GEM_RXQBASE:
1140 s->rx_desc_addr = val;
1141 break;
1142 case GEM_TXQBASE:
1143 s->tx_desc_addr = val;
1144 break;
1145 case GEM_RXSTATUS:
1146 gem_update_int_status(s);
1147 break;
1148 case GEM_IER:
1149 s->regs[GEM_IMR] &= ~val;
1150 gem_update_int_status(s);
1151 break;
1152 case GEM_IDR:
1153 s->regs[GEM_IMR] |= val;
1154 gem_update_int_status(s);
1155 break;
1156 case GEM_SPADDR1LO:
1157 case GEM_SPADDR2LO:
1158 case GEM_SPADDR3LO:
1159 case GEM_SPADDR4LO:
1160 s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
1161 break;
1162 case GEM_SPADDR1HI:
1163 case GEM_SPADDR2HI:
1164 case GEM_SPADDR3HI:
1165 case GEM_SPADDR4HI:
1166 s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
1167 break;
1168 case GEM_PHYMNTNC:
1169 if (val & GEM_PHYMNTNC_OP_W) {
1170 uint32_t phy_addr, reg_num;
1171
1172 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1173 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1174 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1175 gem_phy_write(s, reg_num, val);
1176 }
1177 }
1178 break;
1179 }
1180
1181 DB_PRINT("newval: 0x%08x\n", s->regs[offset]);
1182}
1183
1184static const MemoryRegionOps gem_ops = {
1185 .read = gem_read,
1186 .write = gem_write,
1187 .endianness = DEVICE_LITTLE_ENDIAN,
1188};
1189
1190static void gem_set_link(NetClientState *nc)
1191{
1192 DB_PRINT("\n");
1193 phy_update_link(qemu_get_nic_opaque(nc));
1194}
1195
1196static NetClientInfo net_gem_info = {
1197 .type = NET_CLIENT_OPTIONS_KIND_NIC,
1198 .size = sizeof(NICState),
1199 .can_receive = gem_can_receive,
1200 .receive = gem_receive,
1201 .link_status_changed = gem_set_link,
1202};
1203
1204static int gem_init(SysBusDevice *sbd)
1205{
1206 DeviceState *dev = DEVICE(sbd);
1207 CadenceGEMState *s = CADENCE_GEM(dev);
1208
1209 DB_PRINT("\n");
1210
1211 gem_init_register_masks(s);
1212 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
1213 "enet", sizeof(s->regs));
1214 sysbus_init_mmio(sbd, &s->iomem);
1215 sysbus_init_irq(sbd, &s->irq);
1216 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1217
1218 s->nic = qemu_new_nic(&net_gem_info, &s->conf,
1219 object_get_typename(OBJECT(dev)), dev->id, s);
1220
1221 return 0;
1222}
1223
1224static const VMStateDescription vmstate_cadence_gem = {
1225 .name = "cadence_gem",
1226 .version_id = 2,
1227 .minimum_version_id = 2,
1228 .fields = (VMStateField[]) {
1229 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
1230 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32),
1231 VMSTATE_UINT8(phy_loop, CadenceGEMState),
1232 VMSTATE_UINT32(rx_desc_addr, CadenceGEMState),
1233 VMSTATE_UINT32(tx_desc_addr, CadenceGEMState),
1234 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
1235 VMSTATE_END_OF_LIST(),
1236 }
1237};
1238
1239static Property gem_properties[] = {
1240 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
1241 DEFINE_PROP_END_OF_LIST(),
1242};
1243
1244static void gem_class_init(ObjectClass *klass, void *data)
1245{
1246 DeviceClass *dc = DEVICE_CLASS(klass);
1247 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1248
1249 sdc->init = gem_init;
1250 dc->props = gem_properties;
1251 dc->vmsd = &vmstate_cadence_gem;
1252 dc->reset = gem_reset;
1253}
1254
1255static const TypeInfo gem_info = {
1256 .name = TYPE_CADENCE_GEM,
1257 .parent = TYPE_SYS_BUS_DEVICE,
1258 .instance_size = sizeof(CadenceGEMState),
1259 .class_init = gem_class_init,
1260};
1261
1262static void gem_register_types(void)
1263{
1264 type_register_static(&gem_info);
1265}
1266
1267type_init(gem_register_types)
1268