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24#include "qemu/osdep.h"
25#include "net/checksum.h"
26
27#include "etsec.h"
28#include "registers.h"
29
30
31
32
33
34#ifdef ETSEC_RING_DEBUG
35static const int debug_etsec = 1;
36#else
37static const int debug_etsec;
38#endif
39
40#define RING_DEBUG(fmt, ...) do { \
41 if (debug_etsec) { \
42 qemu_log(fmt , ## __VA_ARGS__); \
43 } \
44 } while (0)
45
46#ifdef DEBUG_BD
47
48static void print_tx_bd_flags(uint16_t flags)
49{
50 qemu_log(" Ready: %d\n", !!(flags & BD_TX_READY));
51 qemu_log(" PAD/CRC: %d\n", !!(flags & BD_TX_PADCRC));
52 qemu_log(" Wrap: %d\n", !!(flags & BD_WRAP));
53 qemu_log(" Interrupt: %d\n", !!(flags & BD_INTERRUPT));
54 qemu_log(" Last in frame: %d\n", !!(flags & BD_LAST));
55 qemu_log(" Tx CRC: %d\n", !!(flags & BD_TX_TC));
56 qemu_log(" User-defined preamble / defer: %d\n",
57 !!(flags & BD_TX_PREDEF));
58 qemu_log(" Huge frame enable / Late collision: %d\n",
59 !!(flags & BD_TX_HFELC));
60 qemu_log(" Control frame / Retransmission Limit: %d\n",
61 !!(flags & BD_TX_CFRL));
62 qemu_log(" Retry count: %d\n",
63 (flags >> BD_TX_RC_OFFSET) & BD_TX_RC_MASK);
64 qemu_log(" Underrun / TCP/IP off-load enable: %d\n",
65 !!(flags & BD_TX_TOEUN));
66 qemu_log(" Truncation: %d\n", !!(flags & BD_TX_TR));
67}
68
69static void print_rx_bd_flags(uint16_t flags)
70{
71 qemu_log(" Empty: %d\n", !!(flags & BD_RX_EMPTY));
72 qemu_log(" Receive software ownership: %d\n", !!(flags & BD_RX_RO1));
73 qemu_log(" Wrap: %d\n", !!(flags & BD_WRAP));
74 qemu_log(" Interrupt: %d\n", !!(flags & BD_INTERRUPT));
75 qemu_log(" Last in frame: %d\n", !!(flags & BD_LAST));
76 qemu_log(" First in frame: %d\n", !!(flags & BD_RX_FIRST));
77 qemu_log(" Miss: %d\n", !!(flags & BD_RX_MISS));
78 qemu_log(" Broadcast: %d\n", !!(flags & BD_RX_BROADCAST));
79 qemu_log(" Multicast: %d\n", !!(flags & BD_RX_MULTICAST));
80 qemu_log(" Rx frame length violation: %d\n", !!(flags & BD_RX_LG));
81 qemu_log(" Rx non-octet aligned frame: %d\n", !!(flags & BD_RX_NO));
82 qemu_log(" Short frame: %d\n", !!(flags & BD_RX_SH));
83 qemu_log(" Rx CRC Error: %d\n", !!(flags & BD_RX_CR));
84 qemu_log(" Overrun: %d\n", !!(flags & BD_RX_OV));
85 qemu_log(" Truncation: %d\n", !!(flags & BD_RX_TR));
86}
87
88
89static void print_bd(eTSEC_rxtx_bd bd, int mode, uint32_t index)
90{
91 qemu_log("eTSEC %s Data Buffer Descriptor (%u)\n",
92 mode == eTSEC_TRANSMIT ? "Transmit" : "Receive",
93 index);
94 qemu_log(" Flags : 0x%04x\n", bd.flags);
95 if (mode == eTSEC_TRANSMIT) {
96 print_tx_bd_flags(bd.flags);
97 } else {
98 print_rx_bd_flags(bd.flags);
99 }
100 qemu_log(" Length : 0x%04x\n", bd.length);
101 qemu_log(" Pointer : 0x%08x\n", bd.bufptr);
102}
103
104#endif
105
106static void read_buffer_descriptor(eTSEC *etsec,
107 hwaddr addr,
108 eTSEC_rxtx_bd *bd)
109{
110 assert(bd != NULL);
111
112 RING_DEBUG("READ Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr);
113 cpu_physical_memory_read(addr,
114 bd,
115 sizeof(eTSEC_rxtx_bd));
116
117 if (etsec->regs[DMACTRL].value & DMACTRL_LE) {
118 bd->flags = lduw_le_p(&bd->flags);
119 bd->length = lduw_le_p(&bd->length);
120 bd->bufptr = ldl_le_p(&bd->bufptr);
121 } else {
122 bd->flags = lduw_be_p(&bd->flags);
123 bd->length = lduw_be_p(&bd->length);
124 bd->bufptr = ldl_be_p(&bd->bufptr);
125 }
126}
127
128static void write_buffer_descriptor(eTSEC *etsec,
129 hwaddr addr,
130 eTSEC_rxtx_bd *bd)
131{
132 assert(bd != NULL);
133
134 if (etsec->regs[DMACTRL].value & DMACTRL_LE) {
135 stw_le_p(&bd->flags, bd->flags);
136 stw_le_p(&bd->length, bd->length);
137 stl_le_p(&bd->bufptr, bd->bufptr);
138 } else {
139 stw_be_p(&bd->flags, bd->flags);
140 stw_be_p(&bd->length, bd->length);
141 stl_be_p(&bd->bufptr, bd->bufptr);
142 }
143
144 RING_DEBUG("Write Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr);
145 cpu_physical_memory_write(addr,
146 bd,
147 sizeof(eTSEC_rxtx_bd));
148}
149
150static void ievent_set(eTSEC *etsec,
151 uint32_t flags)
152{
153 etsec->regs[IEVENT].value |= flags;
154
155 if ((flags & IEVENT_TXB && etsec->regs[IMASK].value & IMASK_TXBEN)
156 || (flags & IEVENT_TXF && etsec->regs[IMASK].value & IMASK_TXFEN)) {
157 qemu_irq_raise(etsec->tx_irq);
158 RING_DEBUG("%s Raise Tx IRQ\n", __func__);
159 }
160
161 if ((flags & IEVENT_RXB && etsec->regs[IMASK].value & IMASK_RXBEN)
162 || (flags & IEVENT_RXF && etsec->regs[IMASK].value & IMASK_RXFEN)) {
163 qemu_irq_raise(etsec->rx_irq);
164 RING_DEBUG("%s Raise Rx IRQ\n", __func__);
165 }
166}
167
168static void tx_padding_and_crc(eTSEC *etsec, uint32_t min_frame_len)
169{
170 int add = min_frame_len - etsec->tx_buffer_len;
171
172
173 if (add > 0) {
174 RING_DEBUG("pad:%u\n", add);
175 etsec->tx_buffer = g_realloc(etsec->tx_buffer,
176 etsec->tx_buffer_len + add);
177
178 memset(etsec->tx_buffer + etsec->tx_buffer_len, 0x0, add);
179 etsec->tx_buffer_len += add;
180 }
181
182
183}
184
185static void process_tx_fcb(eTSEC *etsec)
186{
187 uint8_t flags = (uint8_t)(*etsec->tx_buffer);
188
189 uint8_t l3_header_offset = (uint8_t)*(etsec->tx_buffer + 3);
190
191 uint8_t l4_header_offset = (uint8_t)*(etsec->tx_buffer + 2);
192
193 uint8_t *l3_header = etsec->tx_buffer + 8 + l3_header_offset;
194
195 uint8_t *l4_header = l3_header + l4_header_offset;
196
197
198 if (flags & FCB_TX_IP && flags & FCB_TX_CIP) {
199
200
201 net_checksum_calculate(etsec->tx_buffer + 8,
202 etsec->tx_buffer_len - 8);
203 }
204
205
206
207
208 if (flags & FCB_TX_IP && flags & FCB_TX_TUP) {
209
210 if (flags & FCB_TX_UDP) {
211
212 if (flags & FCB_TX_CTU) {
213
214
215 net_checksum_calculate(etsec->tx_buffer + 8,
216 etsec->tx_buffer_len - 8);
217 } else {
218
219 l4_header[6] = 0;
220 l4_header[7] = 0;
221 }
222 } else if (flags & FCB_TX_CTU) {
223
224 net_checksum_calculate(etsec->tx_buffer + 8,
225 etsec->tx_buffer_len - 8);
226 }
227 }
228}
229
230static void process_tx_bd(eTSEC *etsec,
231 eTSEC_rxtx_bd *bd)
232{
233 uint8_t *tmp_buff = NULL;
234 hwaddr tbdbth = (hwaddr)(etsec->regs[TBDBPH].value & 0xF) << 32;
235
236 if (bd->length == 0) {
237
238 return;
239 }
240
241 if (etsec->tx_buffer_len == 0) {
242
243 etsec->first_bd = *bd;
244 }
245
246
247
248
249 etsec->tx_buffer = g_realloc(etsec->tx_buffer,
250 etsec->tx_buffer_len + bd->length);
251 tmp_buff = etsec->tx_buffer + etsec->tx_buffer_len;
252 cpu_physical_memory_read(bd->bufptr + tbdbth, tmp_buff, bd->length);
253
254
255 etsec->tx_buffer_len += bd->length;
256
257
258 if (etsec->tx_buffer_len != 0 && (bd->flags & BD_LAST)) {
259 if (etsec->regs[MACCFG1].value & MACCFG1_TX_EN) {
260
261
262
263 if (etsec->first_bd.flags & BD_TX_TOEUN) {
264 process_tx_fcb(etsec);
265 }
266
267 if (etsec->first_bd.flags & BD_TX_PADCRC
268 || etsec->regs[MACCFG2].value & MACCFG2_PADCRC) {
269
270
271 tx_padding_and_crc(etsec, 64);
272
273 } else if (etsec->first_bd.flags & BD_TX_TC
274 || etsec->regs[MACCFG2].value & MACCFG2_CRC_EN) {
275
276
277
278 }
279
280#if defined(HEX_DUMP)
281 qemu_log("eTSEC Send packet size:%d\n", etsec->tx_buffer_len);
282 qemu_hexdump(etsec->tx_buffer, stderr, "", etsec->tx_buffer_len);
283#endif
284
285 if (etsec->first_bd.flags & BD_TX_TOEUN) {
286 qemu_send_packet(qemu_get_queue(etsec->nic),
287 etsec->tx_buffer + 8,
288 etsec->tx_buffer_len - 8);
289 } else {
290 qemu_send_packet(qemu_get_queue(etsec->nic),
291 etsec->tx_buffer,
292 etsec->tx_buffer_len);
293 }
294
295 }
296
297 etsec->tx_buffer_len = 0;
298
299 if (bd->flags & BD_INTERRUPT) {
300 ievent_set(etsec, IEVENT_TXF);
301 }
302 } else {
303 if (bd->flags & BD_INTERRUPT) {
304 ievent_set(etsec, IEVENT_TXB);
305 }
306 }
307
308
309
310
311 bd->flags &= ~BD_TX_READY;
312
313
314 bd->flags &= ~BD_TX_PREDEF;
315
316
317 bd->flags &= ~BD_TX_HFELC;
318
319
320 bd->flags &= ~BD_TX_CFRL;
321
322
323 bd->flags &= ~(BD_TX_RC_MASK << BD_TX_RC_OFFSET);
324
325
326 bd->flags &= ~BD_TX_TOEUN;
327
328
329 bd->flags &= ~BD_TX_TR;
330}
331
332void etsec_walk_tx_ring(eTSEC *etsec, int ring_nbr)
333{
334 hwaddr ring_base = 0;
335 hwaddr bd_addr = 0;
336 eTSEC_rxtx_bd bd;
337 uint16_t bd_flags;
338
339 if (!(etsec->regs[MACCFG1].value & MACCFG1_TX_EN)) {
340 RING_DEBUG("%s: MAC Transmit not enabled\n", __func__);
341 return;
342 }
343
344 ring_base = (hwaddr)(etsec->regs[TBASEH].value & 0xF) << 32;
345 ring_base += etsec->regs[TBASE0 + ring_nbr].value & ~0x7;
346 bd_addr = etsec->regs[TBPTR0 + ring_nbr].value & ~0x7;
347
348 do {
349 read_buffer_descriptor(etsec, bd_addr, &bd);
350
351#ifdef DEBUG_BD
352 print_bd(bd,
353 eTSEC_TRANSMIT,
354 (bd_addr - ring_base) / sizeof(eTSEC_rxtx_bd));
355
356#endif
357
358
359 bd_flags = bd.flags;
360
361 if (bd_flags & BD_TX_READY) {
362 process_tx_bd(etsec, &bd);
363
364
365 write_buffer_descriptor(etsec, bd_addr, &bd);
366 }
367
368
369 if (bd_flags & BD_WRAP) {
370 bd_addr = ring_base;
371 } else {
372 bd_addr += sizeof(eTSEC_rxtx_bd);
373 }
374
375 } while (bd_addr != ring_base);
376
377 bd_addr = ring_base;
378
379
380 etsec->regs[TBPTR0 + ring_nbr].value = bd_addr;
381
382
383 etsec->regs[TSTAT].value |= 1 << (31 - ring_nbr);
384}
385
386static void fill_rx_bd(eTSEC *etsec,
387 eTSEC_rxtx_bd *bd,
388 const uint8_t **buf,
389 size_t *size)
390{
391 uint16_t to_write;
392 hwaddr bufptr = bd->bufptr +
393 ((hwaddr)(etsec->regs[TBDBPH].value & 0xF) << 32);
394 uint8_t padd[etsec->rx_padding];
395 uint8_t rem;
396
397 RING_DEBUG("eTSEC fill Rx buffer @ 0x%016" HWADDR_PRIx
398 " size:%zu(padding + crc:%u) + fcb:%u\n",
399 bufptr, *size, etsec->rx_padding, etsec->rx_fcb_size);
400
401 bd->length = 0;
402
403
404 if (etsec->rx_fcb_size != 0) {
405
406 cpu_physical_memory_write(bufptr, etsec->rx_fcb, etsec->rx_fcb_size);
407
408 bufptr += etsec->rx_fcb_size;
409 bd->length += etsec->rx_fcb_size;
410 etsec->rx_fcb_size = 0;
411
412 }
413
414
415
416
417 to_write = MIN(*size - etsec->rx_padding,
418 etsec->regs[MRBLR].value - etsec->rx_fcb_size);
419
420
421 if (to_write > 0) {
422 cpu_physical_memory_write(bufptr, *buf, to_write);
423
424 *buf += to_write;
425 bufptr += to_write;
426 *size -= to_write;
427
428 bd->flags &= ~BD_RX_EMPTY;
429 bd->length += to_write;
430 }
431
432 if (*size == etsec->rx_padding) {
433
434
435
436
437 rem = MIN(etsec->regs[MRBLR].value - bd->length, etsec->rx_padding);
438
439 if (rem > 0) {
440 memset(padd, 0x0, sizeof(padd));
441 etsec->rx_padding -= rem;
442 *size -= rem;
443 bd->length += rem;
444 cpu_physical_memory_write(bufptr, padd, rem);
445 }
446 }
447}
448
449static void rx_init_frame(eTSEC *etsec, const uint8_t *buf, size_t size)
450{
451 uint32_t fcb_size = 0;
452 uint8_t prsdep = (etsec->regs[RCTRL].value >> RCTRL_PRSDEP_OFFSET)
453 & RCTRL_PRSDEP_MASK;
454
455 if (prsdep != 0) {
456
457 fcb_size = 8 + ((etsec->regs[RCTRL].value >> 16) & 0x1F);
458
459 etsec->rx_fcb_size = fcb_size;
460
461
462 memset(etsec->rx_fcb, 0x0, sizeof(etsec->rx_fcb));
463
464 } else {
465 etsec->rx_fcb_size = 0;
466 }
467
468 g_free(etsec->rx_buffer);
469
470
471 etsec->rx_buffer = (uint8_t *)buf;
472 etsec->rx_buffer_len = size;
473
474
475 etsec->rx_padding = 4;
476
477 etsec->rx_first_in_frame = 1;
478 etsec->rx_remaining_data = etsec->rx_buffer_len;
479 RING_DEBUG("%s: rx_buffer_len:%u rx_padding+crc:%u\n", __func__,
480 etsec->rx_buffer_len, etsec->rx_padding);
481}
482
483ssize_t etsec_rx_ring_write(eTSEC *etsec, const uint8_t *buf, size_t size)
484{
485 int ring_nbr = 0;
486
487 if (etsec->rx_buffer_len != 0) {
488 RING_DEBUG("%s: We can't receive now,"
489 " a buffer is already in the pipe\n", __func__);
490 return 0;
491 }
492
493 if (etsec->regs[RSTAT].value & 1 << (23 - ring_nbr)) {
494 RING_DEBUG("%s: The ring is halted\n", __func__);
495 return -1;
496 }
497
498 if (etsec->regs[DMACTRL].value & DMACTRL_GRS) {
499 RING_DEBUG("%s: Graceful receive stop\n", __func__);
500 return -1;
501 }
502
503 if (!(etsec->regs[MACCFG1].value & MACCFG1_RX_EN)) {
504 RING_DEBUG("%s: MAC Receive not enabled\n", __func__);
505 return -1;
506 }
507
508 if ((etsec->regs[RCTRL].value & RCTRL_RSF) && (size < 60)) {
509
510 RING_DEBUG("%s: Drop short frame\n", __func__);
511 return -1;
512 }
513
514 rx_init_frame(etsec, buf, size);
515
516 etsec_walk_rx_ring(etsec, ring_nbr);
517
518 return size;
519}
520
521void etsec_walk_rx_ring(eTSEC *etsec, int ring_nbr)
522{
523 hwaddr ring_base = 0;
524 hwaddr bd_addr = 0;
525 hwaddr start_bd_addr = 0;
526 eTSEC_rxtx_bd bd;
527 uint16_t bd_flags;
528 size_t remaining_data;
529 const uint8_t *buf;
530 uint8_t *tmp_buf;
531 size_t size;
532
533 if (etsec->rx_buffer_len == 0) {
534
535 RING_DEBUG("No frame to send\n");
536 return;
537 }
538
539 remaining_data = etsec->rx_remaining_data + etsec->rx_padding;
540 buf = etsec->rx_buffer
541 + (etsec->rx_buffer_len - etsec->rx_remaining_data);
542 size = etsec->rx_buffer_len + etsec->rx_padding;
543
544 ring_base = (hwaddr)(etsec->regs[RBASEH].value & 0xF) << 32;
545 ring_base += etsec->regs[RBASE0 + ring_nbr].value & ~0x7;
546 start_bd_addr = bd_addr = etsec->regs[RBPTR0 + ring_nbr].value & ~0x7;
547
548 do {
549 read_buffer_descriptor(etsec, bd_addr, &bd);
550
551#ifdef DEBUG_BD
552 print_bd(bd,
553 eTSEC_RECEIVE,
554 (bd_addr - ring_base) / sizeof(eTSEC_rxtx_bd));
555
556#endif
557
558
559 bd_flags = bd.flags;
560
561 if (bd_flags & BD_RX_EMPTY) {
562 fill_rx_bd(etsec, &bd, &buf, &remaining_data);
563
564 if (etsec->rx_first_in_frame) {
565 bd.flags |= BD_RX_FIRST;
566 etsec->rx_first_in_frame = 0;
567 etsec->rx_first_bd = bd;
568 }
569
570
571 if (remaining_data == 0) {
572
573
574
575 bd.flags &= ~0x7ff;
576
577 bd.flags |= BD_LAST;
578
579
580
581 if (size >= etsec->regs[MAXFRM].value) {
582
583 qemu_log("%s frame length violation: size:%zu MAXFRM:%d\n",
584 __func__, size, etsec->regs[MAXFRM].value);
585
586 bd.flags |= BD_RX_LG;
587 }
588
589 if (size < 64) {
590
591 bd.flags |= BD_RX_SH;
592 }
593
594
595
596 if (bd.flags & BD_INTERRUPT) {
597
598 etsec->regs[RSTAT].value |= 1 << (7 - ring_nbr);
599
600
601 ievent_set(etsec, IEVENT_RXF);
602 }
603
604 } else {
605 if (bd.flags & BD_INTERRUPT) {
606
607 ievent_set(etsec, IEVENT_RXB);
608 }
609 }
610
611
612 write_buffer_descriptor(etsec, bd_addr, &bd);
613 }
614
615
616 if (bd_flags & BD_WRAP) {
617 bd_addr = ring_base;
618 } else {
619 bd_addr += sizeof(eTSEC_rxtx_bd);
620 }
621 } while (remaining_data != 0
622 && (bd_flags & BD_RX_EMPTY)
623 && bd_addr != start_bd_addr);
624
625
626 etsec->regs[RBPTR0 + ring_nbr].value = bd_addr;
627
628
629 if (remaining_data > 0) {
630
631
632 etsec->regs[RSTAT].value |= 1 << (23 - ring_nbr);
633
634
635
636
637 etsec->rx_remaining_data = remaining_data;
638
639
640 tmp_buf = g_malloc(size);
641 memcpy(tmp_buf, etsec->rx_buffer, size);
642 etsec->rx_buffer = tmp_buf;
643
644 RING_DEBUG("no empty RxBD available any more\n");
645 } else {
646 etsec->rx_buffer_len = 0;
647 etsec->rx_buffer = NULL;
648 if (etsec->need_flush) {
649 qemu_flush_queued_packets(qemu_get_queue(etsec->nic));
650 }
651 }
652
653 RING_DEBUG("eTSEC End of ring_write: remaining_data:%zu\n", remaining_data);
654}
655