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23#include "qemu/osdep.h"
24#include "hw/pci/pci_ids.h"
25#include "hw/pci/msi.h"
26#include "hw/pci/pcie.h"
27#include "ioh3420.h"
28
29#define PCI_DEVICE_ID_IOH_EPORT 0x3420
30#define PCI_DEVICE_ID_IOH_REV 0x2
31#define IOH_EP_SSVID_OFFSET 0x40
32#define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL
33#define IOH_EP_SSVID_SSID 0
34#define IOH_EP_MSI_OFFSET 0x60
35#define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT
36#define IOH_EP_MSI_NR_VECTOR 2
37#define IOH_EP_EXP_OFFSET 0x90
38#define IOH_EP_AER_OFFSET 0x100
39
40
41
42
43
44
45static uint8_t ioh3420_aer_vector(const PCIDevice *d)
46{
47 switch (msi_nr_vectors_allocated(d)) {
48 case 1:
49 return 0;
50 case 2:
51 return 1;
52 case 4:
53 case 8:
54 case 16:
55 case 32:
56 default:
57 break;
58 }
59 abort();
60 return 0;
61}
62
63static void ioh3420_aer_vector_update(PCIDevice *d)
64{
65 pcie_aer_root_set_vector(d, ioh3420_aer_vector(d));
66}
67
68static void ioh3420_write_config(PCIDevice *d,
69 uint32_t address, uint32_t val, int len)
70{
71 uint32_t root_cmd =
72 pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
73
74 pci_bridge_write_config(d, address, val, len);
75 ioh3420_aer_vector_update(d);
76 pcie_cap_slot_write_config(d, address, val, len);
77 pcie_aer_write_config(d, address, val, len);
78 pcie_aer_root_write_config(d, address, val, len, root_cmd);
79}
80
81static void ioh3420_reset(DeviceState *qdev)
82{
83 PCIDevice *d = PCI_DEVICE(qdev);
84
85 ioh3420_aer_vector_update(d);
86 pcie_cap_root_reset(d);
87 pcie_cap_deverr_reset(d);
88 pcie_cap_slot_reset(d);
89 pcie_cap_arifwd_reset(d);
90 pcie_aer_root_reset(d);
91 pci_bridge_reset(qdev);
92 pci_bridge_disable_base_limit(d);
93}
94
95static int ioh3420_initfn(PCIDevice *d)
96{
97 PCIEPort *p = PCIE_PORT(d);
98 PCIESlot *s = PCIE_SLOT(d);
99 int rc;
100
101 pci_bridge_initfn(d, TYPE_PCIE_BUS);
102 pcie_port_init_reg(d);
103
104 rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
105 IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
106 if (rc < 0) {
107 goto err_bridge;
108 }
109 rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
110 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
111 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
112 if (rc < 0) {
113 goto err_bridge;
114 }
115 rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port);
116 if (rc < 0) {
117 goto err_msi;
118 }
119
120 pcie_cap_arifwd_init(d);
121 pcie_cap_deverr_init(d);
122 pcie_cap_slot_init(d, s->slot);
123 pcie_chassis_create(s->chassis);
124 rc = pcie_chassis_add_slot(s);
125 if (rc < 0) {
126 goto err_pcie_cap;
127 }
128 pcie_cap_root_init(d);
129 rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF);
130 if (rc < 0) {
131 goto err;
132 }
133 pcie_aer_root_init(d);
134 ioh3420_aer_vector_update(d);
135 return 0;
136
137err:
138 pcie_chassis_del_slot(s);
139err_pcie_cap:
140 pcie_cap_exit(d);
141err_msi:
142 msi_uninit(d);
143err_bridge:
144 pci_bridge_exitfn(d);
145 return rc;
146}
147
148static void ioh3420_exitfn(PCIDevice *d)
149{
150 PCIESlot *s = PCIE_SLOT(d);
151
152 pcie_aer_exit(d);
153 pcie_chassis_del_slot(s);
154 pcie_cap_exit(d);
155 msi_uninit(d);
156 pci_bridge_exitfn(d);
157}
158
159static Property ioh3420_props[] = {
160 DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
161 QEMU_PCIE_SLTCAP_PCP_BITNR, true),
162 DEFINE_PROP_END_OF_LIST()
163};
164
165static const VMStateDescription vmstate_ioh3420 = {
166 .name = "ioh-3240-express-root-port",
167 .version_id = 1,
168 .minimum_version_id = 1,
169 .post_load = pcie_cap_slot_post_load,
170 .fields = (VMStateField[]) {
171 VMSTATE_PCIE_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
172 VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
173 PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
174 VMSTATE_END_OF_LIST()
175 }
176};
177
178static void ioh3420_class_init(ObjectClass *klass, void *data)
179{
180 DeviceClass *dc = DEVICE_CLASS(klass);
181 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
182
183 k->is_express = 1;
184 k->is_bridge = 1;
185 k->config_write = ioh3420_write_config;
186 k->init = ioh3420_initfn;
187 k->exit = ioh3420_exitfn;
188 k->vendor_id = PCI_VENDOR_ID_INTEL;
189 k->device_id = PCI_DEVICE_ID_IOH_EPORT;
190 k->revision = PCI_DEVICE_ID_IOH_REV;
191 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
192 dc->desc = "Intel IOH device id 3420 PCIE Root Port";
193 dc->reset = ioh3420_reset;
194 dc->vmsd = &vmstate_ioh3420;
195 dc->props = ioh3420_props;
196}
197
198static const TypeInfo ioh3420_info = {
199 .name = "ioh3420",
200 .parent = TYPE_PCIE_SLOT,
201 .class_init = ioh3420_class_init,
202};
203
204static void ioh3420_register_types(void)
205{
206 type_register_static(&ioh3420_info);
207}
208
209type_init(ioh3420_register_types)
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