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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "qemu-common.h"
24#include "hw/pci/pci_bridge.h"
25#include "hw/pci/pcie.h"
26#include "hw/pci/msix.h"
27#include "hw/pci/msi.h"
28#include "hw/pci/pci_bus.h"
29#include "hw/pci/pcie_regs.h"
30#include "qemu/range.h"
31
32
33#ifdef DEBUG_PCIE
34# define PCIE_DPRINTF(fmt, ...) \
35 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
36#else
37# define PCIE_DPRINTF(fmt, ...) do {} while (0)
38#endif
39#define PCIE_DEV_PRINTF(dev, fmt, ...) \
40 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
41
42
43
44
45
46int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
47{
48 int pos;
49 uint8_t *exp_cap;
50 uint8_t *cmask;
51
52 assert(pci_is_express(dev));
53
54 pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
55 PCI_EXP_VER2_SIZEOF);
56 if (pos < 0) {
57 return pos;
58 }
59 dev->exp.exp_cap = pos;
60 exp_cap = dev->config + pos;
61 cmask = dev->cmask + pos;
62
63
64
65 pci_set_word(exp_cap + PCI_EXP_FLAGS,
66 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
67 PCI_EXP_FLAGS_VER2);
68
69
70
71
72
73
74
75
76 pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
77
78 pci_set_long(exp_cap + PCI_EXP_LNKCAP,
79 (port << PCI_EXP_LNKCAP_PN_SHIFT) |
80 PCI_EXP_LNKCAP_ASPMS_0S |
81 PCI_EXP_LNK_MLW_1 |
82 PCI_EXP_LNK_LS_25);
83
84 pci_set_word(exp_cap + PCI_EXP_LNKSTA,
85 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25);
86
87 if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
88 pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
89 PCI_EXP_LNKSTA_DLLLA);
90 }
91
92
93
94
95
96 pci_set_word(cmask + PCI_EXP_LNKSTA, 0);
97
98 pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
99 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
100
101 pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
102 return pos;
103}
104
105int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
106{
107 uint8_t type = PCI_EXP_TYPE_ENDPOINT;
108
109
110
111
112
113
114 if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) {
115 type = PCI_EXP_TYPE_RC_END;
116 }
117
118 return pcie_cap_init(dev, offset, type, 0);
119}
120
121void pcie_cap_exit(PCIDevice *dev)
122{
123 pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
124}
125
126uint8_t pcie_cap_get_type(const PCIDevice *dev)
127{
128 uint32_t pos = dev->exp.exp_cap;
129 assert(pos > 0);
130 return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
131 PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
132}
133
134
135
136
137void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
138{
139 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
140 assert(vector < 32);
141 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
142 pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
143 vector << PCI_EXP_FLAGS_IRQ_SHIFT);
144}
145
146uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
147{
148 return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
149 PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
150}
151
152void pcie_cap_deverr_init(PCIDevice *dev)
153{
154 uint32_t pos = dev->exp.exp_cap;
155 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
156 PCI_EXP_DEVCAP_RBER);
157 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
158 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
159 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
160 pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
161 PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
162 PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD);
163}
164
165void pcie_cap_deverr_reset(PCIDevice *dev)
166{
167 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
168 pci_long_test_and_clear_mask(devctl,
169 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
170 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
171}
172
173static void hotplug_event_update_event_status(PCIDevice *dev)
174{
175 uint32_t pos = dev->exp.exp_cap;
176 uint8_t *exp_cap = dev->config + pos;
177 uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
178 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
179
180 dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
181 (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
182}
183
184static void hotplug_event_notify(PCIDevice *dev)
185{
186 bool prev = dev->exp.hpev_notified;
187
188 hotplug_event_update_event_status(dev);
189
190 if (prev == dev->exp.hpev_notified) {
191 return;
192 }
193
194
195
196
197
198
199
200 if (msix_enabled(dev)) {
201 msix_notify(dev, pcie_cap_flags_get_vector(dev));
202 } else if (msi_enabled(dev)) {
203 msi_notify(dev, pcie_cap_flags_get_vector(dev));
204 } else {
205 pci_set_irq(dev, dev->exp.hpev_notified);
206 }
207}
208
209static void hotplug_event_clear(PCIDevice *dev)
210{
211 hotplug_event_update_event_status(dev);
212 if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
213 pci_irq_deassert(dev);
214 }
215}
216
217
218
219
220
221
222
223
224static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
225{
226
227 if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
228 PCI_EXP_SLTSTA, event)) {
229 return;
230 }
231 hotplug_event_notify(dev);
232}
233
234static void pcie_cap_slot_hotplug_common(PCIDevice *hotplug_dev,
235 DeviceState *dev,
236 uint8_t **exp_cap, Error **errp)
237{
238 *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap;
239 uint16_t sltsta = pci_get_word(*exp_cap + PCI_EXP_SLTSTA);
240
241 PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta);
242 if (sltsta & PCI_EXP_SLTSTA_EIS) {
243
244
245
246 error_setg_errno(errp, EBUSY, "slot is electromechanically locked");
247 }
248}
249
250void pcie_cap_slot_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
251 Error **errp)
252{
253 uint8_t *exp_cap;
254 PCIDevice *pci_dev = PCI_DEVICE(dev);
255
256 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp);
257
258
259
260
261 if (!dev->hotplugged) {
262 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
263 PCI_EXP_SLTSTA_PDS);
264 return;
265 }
266
267
268
269
270
271 if (pci_get_function_0(pci_dev)) {
272 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
273 PCI_EXP_SLTSTA_PDS);
274 pcie_cap_slot_event(PCI_DEVICE(hotplug_dev),
275 PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP);
276 }
277}
278
279static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque)
280{
281 object_unparent(OBJECT(dev));
282}
283
284void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler *hotplug_dev,
285 DeviceState *dev, Error **errp)
286{
287 uint8_t *exp_cap;
288 PCIDevice *pci_dev = PCI_DEVICE(dev);
289 PCIBus *bus = pci_dev->bus;
290
291 pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp);
292
293
294
295
296
297 if (pci_dev->devfn &&
298 !bus->devices[0]) {
299 pcie_unplug_device(bus, pci_dev, NULL);
300
301 return;
302 }
303
304 pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev));
305}
306
307
308
309void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
310{
311 uint32_t pos = dev->exp.exp_cap;
312
313 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
314 PCI_EXP_FLAGS_SLOT);
315
316 pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
317 ~PCI_EXP_SLTCAP_PSN);
318 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
319 (slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
320 PCI_EXP_SLTCAP_EIP |
321 PCI_EXP_SLTCAP_HPS |
322 PCI_EXP_SLTCAP_HPC |
323 PCI_EXP_SLTCAP_PIP |
324 PCI_EXP_SLTCAP_AIP |
325 PCI_EXP_SLTCAP_ABP);
326
327 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
328 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
329 PCI_EXP_SLTCAP_PCP);
330 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
331 PCI_EXP_SLTCTL_PCC);
332 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
333 PCI_EXP_SLTCTL_PCC);
334 }
335
336 pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
337 PCI_EXP_SLTCTL_PIC |
338 PCI_EXP_SLTCTL_AIC);
339 pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
340 PCI_EXP_SLTCTL_PIC_OFF |
341 PCI_EXP_SLTCTL_AIC_OFF);
342 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
343 PCI_EXP_SLTCTL_PIC |
344 PCI_EXP_SLTCTL_AIC |
345 PCI_EXP_SLTCTL_HPIE |
346 PCI_EXP_SLTCTL_CCIE |
347 PCI_EXP_SLTCTL_PDCE |
348 PCI_EXP_SLTCTL_ABPE);
349
350
351
352
353
354 pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
355 PCI_EXP_SLTCTL_EIC);
356
357 pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
358 PCI_EXP_HP_EV_SUPPORTED);
359
360 dev->exp.hpev_notified = false;
361
362 qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))),
363 DEVICE(dev), NULL);
364}
365
366void pcie_cap_slot_reset(PCIDevice *dev)
367{
368 uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
369 uint8_t port_type = pcie_cap_get_type(dev);
370
371 assert(port_type == PCI_EXP_TYPE_DOWNSTREAM ||
372 port_type == PCI_EXP_TYPE_ROOT_PORT);
373
374 PCIE_DEV_PRINTF(dev, "reset\n");
375
376 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
377 PCI_EXP_SLTCTL_EIC |
378 PCI_EXP_SLTCTL_PIC |
379 PCI_EXP_SLTCTL_AIC |
380 PCI_EXP_SLTCTL_HPIE |
381 PCI_EXP_SLTCTL_CCIE |
382 PCI_EXP_SLTCTL_PDCE |
383 PCI_EXP_SLTCTL_ABPE);
384 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
385 PCI_EXP_SLTCTL_AIC_OFF);
386
387 if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
388
389 bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0];
390 uint16_t pic;
391
392 if (populated) {
393 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
394 PCI_EXP_SLTCTL_PCC);
395 } else {
396 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
397 PCI_EXP_SLTCTL_PCC);
398 }
399
400 pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF;
401 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic);
402 }
403
404 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
405 PCI_EXP_SLTSTA_EIS |
406
407 PCI_EXP_SLTSTA_CC |
408 PCI_EXP_SLTSTA_PDC |
409 PCI_EXP_SLTSTA_ABP);
410
411 hotplug_event_update_event_status(dev);
412}
413
414void pcie_cap_slot_write_config(PCIDevice *dev,
415 uint32_t addr, uint32_t val, int len)
416{
417 uint32_t pos = dev->exp.exp_cap;
418 uint8_t *exp_cap = dev->config + pos;
419 uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
420
421 if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
422 hotplug_event_clear(dev);
423 }
424
425 if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
426 return;
427 }
428
429 if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
430 PCI_EXP_SLTCTL_EIC)) {
431 sltsta ^= PCI_EXP_SLTSTA_EIS;
432 pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
433 PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
434 "sltsta -> 0x%02"PRIx16"\n",
435 sltsta);
436 }
437
438
439
440
441
442 if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) &&
443 ((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) {
444 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
445 pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
446 pcie_unplug_device, NULL);
447
448 pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
449 PCI_EXP_SLTSTA_PDS);
450 pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
451 PCI_EXP_SLTSTA_PDC);
452 }
453
454 hotplug_event_notify(dev);
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
473}
474
475int pcie_cap_slot_post_load(void *opaque, int version_id)
476{
477 PCIDevice *dev = opaque;
478 hotplug_event_update_event_status(dev);
479 return 0;
480}
481
482void pcie_cap_slot_push_attention_button(PCIDevice *dev)
483{
484 pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
485}
486
487
488void pcie_cap_root_init(PCIDevice *dev)
489{
490 pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
491 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
492 PCI_EXP_RTCTL_SEFEE);
493}
494
495void pcie_cap_root_reset(PCIDevice *dev)
496{
497 pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
498}
499
500
501void pcie_cap_flr_init(PCIDevice *dev)
502{
503 pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
504 PCI_EXP_DEVCAP_FLR);
505
506
507
508
509
510
511 pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
512 PCI_EXP_DEVCTL_BCR_FLR);
513}
514
515void pcie_cap_flr_write_config(PCIDevice *dev,
516 uint32_t addr, uint32_t val, int len)
517{
518 uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
519 if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
520
521
522 pci_device_reset(dev);
523 pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
524 }
525}
526
527
528
529
530void pcie_cap_arifwd_init(PCIDevice *dev)
531{
532 uint32_t pos = dev->exp.exp_cap;
533 pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
534 PCI_EXP_DEVCAP2_ARI);
535 pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
536 PCI_EXP_DEVCTL2_ARI);
537}
538
539void pcie_cap_arifwd_reset(PCIDevice *dev)
540{
541 uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
542 pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
543}
544
545bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev)
546{
547 if (!pci_is_express(dev)) {
548 return false;
549 }
550 if (!dev->exp.exp_cap) {
551 return false;
552 }
553
554 return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
555 PCI_EXP_DEVCTL2_ARI;
556}
557
558
559
560
561
562
563
564
565
566static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id,
567 uint16_t *prev_p)
568{
569 uint16_t prev = 0;
570 uint16_t next;
571 uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
572
573 if (!header) {
574
575 next = 0;
576 goto out;
577 }
578 for (next = PCI_CONFIG_SPACE_SIZE; next;
579 prev = next, next = PCI_EXT_CAP_NEXT(header)) {
580
581 assert(next >= PCI_CONFIG_SPACE_SIZE);
582 assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
583
584 header = pci_get_long(dev->config + next);
585 if (PCI_EXT_CAP_ID(header) == cap_id) {
586 break;
587 }
588 }
589
590out:
591 if (prev_p) {
592 *prev_p = prev;
593 }
594 return next;
595}
596
597uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
598{
599 return pcie_find_capability_list(dev, cap_id, NULL);
600}
601
602static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
603{
604 uint32_t header = pci_get_long(dev->config + pos);
605 assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
606 header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
607 ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
608 pci_set_long(dev->config + pos, header);
609}
610
611
612
613
614
615
616void pcie_add_capability(PCIDevice *dev,
617 uint16_t cap_id, uint8_t cap_ver,
618 uint16_t offset, uint16_t size)
619{
620 uint32_t header;
621 uint16_t next;
622
623 assert(offset >= PCI_CONFIG_SPACE_SIZE);
624 assert(offset < offset + size);
625 assert(offset + size <= PCIE_CONFIG_SPACE_SIZE);
626 assert(size >= 8);
627 assert(pci_is_express(dev));
628
629 if (offset == PCI_CONFIG_SPACE_SIZE) {
630 header = pci_get_long(dev->config + offset);
631 next = PCI_EXT_CAP_NEXT(header);
632 } else {
633 uint16_t prev;
634
635
636
637 next = pcie_find_capability_list(dev, 0, &prev);
638
639 assert(prev >= PCI_CONFIG_SPACE_SIZE);
640 assert(next == 0);
641 pcie_ext_cap_set_next(dev, prev, offset);
642 }
643 pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next));
644
645
646 memset(dev->wmask + offset, 0, size);
647 memset(dev->w1cmask + offset, 0, size);
648
649 memset(dev->cmask + offset, 0xFF, size);
650}
651
652
653
654
655
656
657void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
658{
659 pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
660 offset, PCI_ARI_SIZEOF);
661 pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8);
662}
663