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22#include "qemu/osdep.h"
23#include "hw/timer/arm_mptimer.h"
24#include "qapi/error.h"
25#include "qemu/timer.h"
26#include "qom/cpu.h"
27
28
29
30
31
32static inline int get_current_cpu(ARMMPTimerState *s)
33{
34 if (current_cpu->cpu_index >= s->num_cpu) {
35 hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
36 s->num_cpu, current_cpu->cpu_index);
37 }
38 return current_cpu->cpu_index;
39}
40
41static inline void timerblock_update_irq(TimerBlock *tb)
42{
43 qemu_set_irq(tb->irq, tb->status && (tb->control & 4));
44}
45
46
47static inline uint32_t timerblock_scale(TimerBlock *tb)
48{
49 return (((tb->control >> 8) & 0xff) + 1) * 10;
50}
51
52static void timerblock_reload(TimerBlock *tb, int restart)
53{
54 if (tb->count == 0) {
55 return;
56 }
57 if (restart) {
58 tb->tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
59 }
60 tb->tick += (int64_t)tb->count * timerblock_scale(tb);
61 timer_mod(tb->timer, tb->tick);
62}
63
64static void timerblock_tick(void *opaque)
65{
66 TimerBlock *tb = (TimerBlock *)opaque;
67 tb->status = 1;
68 if (tb->control & 2) {
69 tb->count = tb->load;
70 timerblock_reload(tb, 0);
71 } else {
72 tb->count = 0;
73 }
74 timerblock_update_irq(tb);
75}
76
77static uint64_t timerblock_read(void *opaque, hwaddr addr,
78 unsigned size)
79{
80 TimerBlock *tb = (TimerBlock *)opaque;
81 int64_t val;
82 switch (addr) {
83 case 0:
84 return tb->load;
85 case 4:
86 if (((tb->control & 1) == 0) || (tb->count == 0)) {
87 return 0;
88 }
89
90 val = tb->tick - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
91 val /= timerblock_scale(tb);
92 if (val < 0) {
93 val = 0;
94 }
95 return val;
96 case 8:
97 return tb->control;
98 case 12:
99 return tb->status;
100 default:
101 return 0;
102 }
103}
104
105static void timerblock_write(void *opaque, hwaddr addr,
106 uint64_t value, unsigned size)
107{
108 TimerBlock *tb = (TimerBlock *)opaque;
109 int64_t old;
110 switch (addr) {
111 case 0:
112 tb->load = value;
113
114 case 4:
115 if ((tb->control & 1) && tb->count) {
116
117 timer_del(tb->timer);
118 }
119 tb->count = value;
120 if (tb->control & 1) {
121 timerblock_reload(tb, 1);
122 }
123 break;
124 case 8:
125 old = tb->control;
126 tb->control = value;
127 if (value & 1) {
128 if ((old & 1) && (tb->count != 0)) {
129
130 break;
131 }
132 if (tb->control & 2) {
133 tb->count = tb->load;
134 }
135 timerblock_reload(tb, 1);
136 } else if (old & 1) {
137
138 timer_del(tb->timer);
139 }
140 break;
141 case 12:
142 tb->status &= ~value;
143 timerblock_update_irq(tb);
144 break;
145 }
146}
147
148
149
150
151static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
152 unsigned size)
153{
154 ARMMPTimerState *s = (ARMMPTimerState *)opaque;
155 int id = get_current_cpu(s);
156 return timerblock_read(&s->timerblock[id], addr, size);
157}
158
159static void arm_thistimer_write(void *opaque, hwaddr addr,
160 uint64_t value, unsigned size)
161{
162 ARMMPTimerState *s = (ARMMPTimerState *)opaque;
163 int id = get_current_cpu(s);
164 timerblock_write(&s->timerblock[id], addr, value, size);
165}
166
167static const MemoryRegionOps arm_thistimer_ops = {
168 .read = arm_thistimer_read,
169 .write = arm_thistimer_write,
170 .valid = {
171 .min_access_size = 4,
172 .max_access_size = 4,
173 },
174 .endianness = DEVICE_NATIVE_ENDIAN,
175};
176
177static const MemoryRegionOps timerblock_ops = {
178 .read = timerblock_read,
179 .write = timerblock_write,
180 .valid = {
181 .min_access_size = 4,
182 .max_access_size = 4,
183 },
184 .endianness = DEVICE_NATIVE_ENDIAN,
185};
186
187static void timerblock_reset(TimerBlock *tb)
188{
189 tb->count = 0;
190 tb->load = 0;
191 tb->control = 0;
192 tb->status = 0;
193 tb->tick = 0;
194 if (tb->timer) {
195 timer_del(tb->timer);
196 }
197}
198
199static void arm_mptimer_reset(DeviceState *dev)
200{
201 ARMMPTimerState *s = ARM_MPTIMER(dev);
202 int i;
203
204 for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) {
205 timerblock_reset(&s->timerblock[i]);
206 }
207}
208
209static void arm_mptimer_init(Object *obj)
210{
211 ARMMPTimerState *s = ARM_MPTIMER(obj);
212
213 memory_region_init_io(&s->iomem, obj, &arm_thistimer_ops, s,
214 "arm_mptimer_timer", 0x20);
215 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
216}
217
218static void arm_mptimer_realize(DeviceState *dev, Error **errp)
219{
220 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
221 ARMMPTimerState *s = ARM_MPTIMER(dev);
222 int i;
223
224 if (s->num_cpu < 1 || s->num_cpu > ARM_MPTIMER_MAX_CPUS) {
225 error_setg(errp, "num-cpu must be between 1 and %d",
226 ARM_MPTIMER_MAX_CPUS);
227 return;
228 }
229
230
231
232
233
234
235
236
237
238
239 for (i = 0; i < s->num_cpu; i++) {
240 TimerBlock *tb = &s->timerblock[i];
241 tb->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, timerblock_tick, tb);
242 sysbus_init_irq(sbd, &tb->irq);
243 memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb,
244 "arm_mptimer_timerblock", 0x20);
245 sysbus_init_mmio(sbd, &tb->iomem);
246 }
247}
248
249static const VMStateDescription vmstate_timerblock = {
250 .name = "arm_mptimer_timerblock",
251 .version_id = 2,
252 .minimum_version_id = 2,
253 .fields = (VMStateField[]) {
254 VMSTATE_UINT32(count, TimerBlock),
255 VMSTATE_UINT32(load, TimerBlock),
256 VMSTATE_UINT32(control, TimerBlock),
257 VMSTATE_UINT32(status, TimerBlock),
258 VMSTATE_INT64(tick, TimerBlock),
259 VMSTATE_TIMER_PTR(timer, TimerBlock),
260 VMSTATE_END_OF_LIST()
261 }
262};
263
264static const VMStateDescription vmstate_arm_mptimer = {
265 .name = "arm_mptimer",
266 .version_id = 2,
267 .minimum_version_id = 2,
268 .fields = (VMStateField[]) {
269 VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu,
270 2, vmstate_timerblock, TimerBlock),
271 VMSTATE_END_OF_LIST()
272 }
273};
274
275static Property arm_mptimer_properties[] = {
276 DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0),
277 DEFINE_PROP_END_OF_LIST()
278};
279
280static void arm_mptimer_class_init(ObjectClass *klass, void *data)
281{
282 DeviceClass *dc = DEVICE_CLASS(klass);
283
284 dc->realize = arm_mptimer_realize;
285 dc->vmsd = &vmstate_arm_mptimer;
286 dc->reset = arm_mptimer_reset;
287 dc->props = arm_mptimer_properties;
288}
289
290static const TypeInfo arm_mptimer_info = {
291 .name = TYPE_ARM_MPTIMER,
292 .parent = TYPE_SYS_BUS_DEVICE,
293 .instance_size = sizeof(ARMMPTimerState),
294 .instance_init = arm_mptimer_init,
295 .class_init = arm_mptimer_class_init,
296};
297
298static void arm_mptimer_register_types(void)
299{
300 type_register_static(&arm_mptimer_info);
301}
302
303type_init(arm_mptimer_register_types)
304