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19#if !defined(__HW_SPAPR_H__)
20#error Please include spapr.h before this file!
21#endif
22
23#if !defined(__HW_SPAPR_PCI_H__)
24#define __HW_SPAPR_PCI_H__
25
26#include "hw/pci/pci.h"
27#include "hw/pci/pci_host.h"
28#include "hw/ppc/xics.h"
29
30#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
31
32#define SPAPR_PCI_HOST_BRIDGE(obj) \
33 OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
34
35typedef struct sPAPRPHBState sPAPRPHBState;
36
37typedef struct spapr_pci_msi {
38 uint32_t first_irq;
39 uint32_t num;
40} spapr_pci_msi;
41
42typedef struct spapr_pci_msi_mig {
43 uint32_t key;
44 spapr_pci_msi value;
45} spapr_pci_msi_mig;
46
47struct sPAPRPHBState {
48 PCIHostState parent_obj;
49
50 uint32_t index;
51 uint64_t buid;
52 char *dtbusname;
53 bool dr_enabled;
54
55 MemoryRegion memspace, iospace;
56 hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
57 MemoryRegion memwindow, iowindow, msiwindow;
58
59 uint32_t dma_liobn;
60 hwaddr dma_win_addr, dma_win_size;
61 AddressSpace iommu_as;
62 MemoryRegion iommu_root;
63
64 struct spapr_pci_lsi {
65 uint32_t irq;
66 } lsi_table[PCI_NUM_PINS];
67
68 GHashTable *msi;
69
70 int32_t msi_devs_num;
71 spapr_pci_msi_mig *msi_devs;
72
73 QLIST_ENTRY(sPAPRPHBState) list;
74};
75
76#define SPAPR_PCI_MAX_INDEX 255
77
78#define SPAPR_PCI_BASE_BUID 0x800000020000000ULL
79
80#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
81
82#define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL
83#define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL
84#define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000
85#define SPAPR_PCI_MMIO_WIN_SIZE (SPAPR_PCI_WINDOW_SPACING - \
86 SPAPR_PCI_MEM_WIN_BUS_OFFSET)
87#define SPAPR_PCI_IO_WIN_OFF 0x80000000
88#define SPAPR_PCI_IO_WIN_SIZE 0x10000
89
90#define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
91
92static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
93{
94 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
95
96 return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
97}
98
99PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);
100
101int spapr_populate_pci_dt(sPAPRPHBState *phb,
102 uint32_t xics_phandle,
103 void *fdt);
104
105void spapr_pci_msi_init(sPAPRMachineState *spapr, hwaddr addr);
106
107void spapr_pci_rtas_init(void);
108
109sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid);
110PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
111 uint32_t config_addr);
112
113
114#ifdef CONFIG_LINUX
115bool spapr_phb_eeh_available(sPAPRPHBState *sphb);
116int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
117 unsigned int addr, int option);
118int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state);
119int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option);
120int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb);
121void spapr_phb_vfio_reset(DeviceState *qdev);
122#else
123static inline bool spapr_phb_eeh_available(sPAPRPHBState *sphb)
124{
125 return false;
126}
127static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
128 unsigned int addr, int option)
129{
130 return RTAS_OUT_HW_ERROR;
131}
132static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb,
133 int *state)
134{
135 return RTAS_OUT_HW_ERROR;
136}
137static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
138{
139 return RTAS_OUT_HW_ERROR;
140}
141static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
142{
143 return RTAS_OUT_HW_ERROR;
144}
145static inline void spapr_phb_vfio_reset(DeviceState *qdev)
146{
147}
148#endif
149
150#endif
151