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10#ifndef DMA_H
11#define DMA_H
12
13#include "exec/memory.h"
14#include "exec/address-spaces.h"
15#include "hw/hw.h"
16#include "block/block.h"
17#include "block/accounting.h"
18#include "sysemu/kvm.h"
19
20typedef struct ScatterGatherEntry ScatterGatherEntry;
21
22typedef enum {
23 DMA_DIRECTION_TO_DEVICE = 0,
24 DMA_DIRECTION_FROM_DEVICE = 1,
25} DMADirection;
26
27struct QEMUSGList {
28 ScatterGatherEntry *sg;
29 int nsg;
30 int nalloc;
31 size_t size;
32 DeviceState *dev;
33 AddressSpace *as;
34};
35
36#ifndef CONFIG_USER_ONLY
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43
44
45typedef uint64_t dma_addr_t;
46
47#define DMA_ADDR_BITS 64
48#define DMA_ADDR_FMT "%" PRIx64
49
50static inline void dma_barrier(AddressSpace *as, DMADirection dir)
51{
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69
70 if (kvm_enabled()) {
71 smp_mb();
72 }
73}
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77
78static inline bool dma_memory_valid(AddressSpace *as,
79 dma_addr_t addr, dma_addr_t len,
80 DMADirection dir)
81{
82 return address_space_access_valid(as, addr, len,
83 dir == DMA_DIRECTION_FROM_DEVICE);
84}
85
86static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
87 void *buf, dma_addr_t len,
88 DMADirection dir)
89{
90 return (bool)address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED,
91 buf, len, dir == DMA_DIRECTION_FROM_DEVICE);
92}
93
94static inline int dma_memory_read_relaxed(AddressSpace *as, dma_addr_t addr,
95 void *buf, dma_addr_t len)
96{
97 return dma_memory_rw_relaxed(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
98}
99
100static inline int dma_memory_write_relaxed(AddressSpace *as, dma_addr_t addr,
101 const void *buf, dma_addr_t len)
102{
103 return dma_memory_rw_relaxed(as, addr, (void *)buf, len,
104 DMA_DIRECTION_FROM_DEVICE);
105}
106
107static inline int dma_memory_rw(AddressSpace *as, dma_addr_t addr,
108 void *buf, dma_addr_t len,
109 DMADirection dir)
110{
111 dma_barrier(as, dir);
112
113 return dma_memory_rw_relaxed(as, addr, buf, len, dir);
114}
115
116static inline int dma_memory_read(AddressSpace *as, dma_addr_t addr,
117 void *buf, dma_addr_t len)
118{
119 return dma_memory_rw(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
120}
121
122static inline int dma_memory_write(AddressSpace *as, dma_addr_t addr,
123 const void *buf, dma_addr_t len)
124{
125 return dma_memory_rw(as, addr, (void *)buf, len,
126 DMA_DIRECTION_FROM_DEVICE);
127}
128
129int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len);
130
131static inline void *dma_memory_map(AddressSpace *as,
132 dma_addr_t addr, dma_addr_t *len,
133 DMADirection dir)
134{
135 hwaddr xlen = *len;
136 void *p;
137
138 p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
139 *len = xlen;
140 return p;
141}
142
143static inline void dma_memory_unmap(AddressSpace *as,
144 void *buffer, dma_addr_t len,
145 DMADirection dir, dma_addr_t access_len)
146{
147 address_space_unmap(as, buffer, (hwaddr)len,
148 dir == DMA_DIRECTION_FROM_DEVICE, access_len);
149}
150
151#define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \
152 static inline uint##_bits##_t ld##_lname##_##_end##_dma(AddressSpace *as, \
153 dma_addr_t addr) \
154 { \
155 uint##_bits##_t val; \
156 dma_memory_read(as, addr, &val, (_bits) / 8); \
157 return _end##_bits##_to_cpu(val); \
158 } \
159 static inline void st##_sname##_##_end##_dma(AddressSpace *as, \
160 dma_addr_t addr, \
161 uint##_bits##_t val) \
162 { \
163 val = cpu_to_##_end##_bits(val); \
164 dma_memory_write(as, addr, &val, (_bits) / 8); \
165 }
166
167static inline uint8_t ldub_dma(AddressSpace *as, dma_addr_t addr)
168{
169 uint8_t val;
170
171 dma_memory_read(as, addr, &val, 1);
172 return val;
173}
174
175static inline void stb_dma(AddressSpace *as, dma_addr_t addr, uint8_t val)
176{
177 dma_memory_write(as, addr, &val, 1);
178}
179
180DEFINE_LDST_DMA(uw, w, 16, le);
181DEFINE_LDST_DMA(l, l, 32, le);
182DEFINE_LDST_DMA(q, q, 64, le);
183DEFINE_LDST_DMA(uw, w, 16, be);
184DEFINE_LDST_DMA(l, l, 32, be);
185DEFINE_LDST_DMA(q, q, 64, be);
186
187#undef DEFINE_LDST_DMA
188
189struct ScatterGatherEntry {
190 dma_addr_t base;
191 dma_addr_t len;
192};
193
194void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint,
195 AddressSpace *as);
196void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len);
197void qemu_sglist_destroy(QEMUSGList *qsg);
198#endif
199
200typedef BlockAIOCB *DMAIOFunc(BlockBackend *blk, int64_t sector_num,
201 QEMUIOVector *iov, int nb_sectors,
202 BlockCompletionFunc *cb, void *opaque);
203
204BlockAIOCB *dma_blk_io(BlockBackend *blk,
205 QEMUSGList *sg, uint64_t sector_num,
206 DMAIOFunc *io_func, BlockCompletionFunc *cb,
207 void *opaque, DMADirection dir);
208BlockAIOCB *dma_blk_read(BlockBackend *blk,
209 QEMUSGList *sg, uint64_t sector,
210 BlockCompletionFunc *cb, void *opaque);
211BlockAIOCB *dma_blk_write(BlockBackend *blk,
212 QEMUSGList *sg, uint64_t sector,
213 BlockCompletionFunc *cb, void *opaque);
214uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg);
215uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg);
216
217void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
218 QEMUSGList *sg, enum BlockAcctType type);
219
220#endif
221