1#ifndef TARGET_ARM_TRANSLATE_H
2#define TARGET_ARM_TRANSLATE_H
3
4
5typedef struct DisasContext {
6 target_ulong pc;
7 uint32_t insn;
8 int is_jmp;
9
10 int condjmp;
11
12 TCGLabel *condlabel;
13
14 int condexec_mask;
15 int condexec_cond;
16 struct TranslationBlock *tb;
17 int singlestep_enabled;
18 int thumb;
19 int sctlr_b;
20 TCGMemOp be_data;
21#if !defined(CONFIG_USER_ONLY)
22 int user;
23#endif
24 ARMMMUIdx mmu_idx;
25 bool ns;
26 int fp_excp_el;
27
28 bool secure_routed_to_el3;
29 bool vfp_enabled;
30 int vec_len;
31 int vec_stride;
32
33
34
35 uint32_t svc_imm;
36 int aarch64;
37 int current_el;
38 GHashTable *cp_regs;
39 uint64_t features;
40
41
42
43
44
45
46
47 bool fp_access_checked;
48
49
50
51 bool ss_active;
52 bool pstate_ss;
53
54
55
56
57 bool is_ldex;
58
59 bool ss_same_el;
60
61 int c15_cpar;
62#define TMP_A64_MAX 16
63 int tmp_a64_count;
64 TCGv_i64 tmp_a64[TMP_A64_MAX];
65} DisasContext;
66
67typedef struct DisasCompare {
68 TCGCond cond;
69 TCGv_i32 value;
70 bool value_global;
71} DisasCompare;
72
73
74extern TCGv_env cpu_env;
75extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
76extern TCGv_i64 cpu_exclusive_addr;
77extern TCGv_i64 cpu_exclusive_val;
78#ifdef CONFIG_USER_ONLY
79extern TCGv_i64 cpu_exclusive_test;
80extern TCGv_i32 cpu_exclusive_info;
81#endif
82
83static inline int arm_dc_feature(DisasContext *dc, int feature)
84{
85 return (dc->features & (1ULL << feature)) != 0;
86}
87
88static inline int get_mem_index(DisasContext *s)
89{
90 return s->mmu_idx;
91}
92
93
94
95
96static inline int default_exception_el(DisasContext *s)
97{
98
99
100
101
102
103 return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
104 ? 3 : MAX(1, s->current_el);
105}
106
107
108
109
110
111
112#define DISAS_WFI 4
113#define DISAS_SWI 5
114
115
116
117#define DISAS_EXC 6
118
119#define DISAS_WFE 7
120#define DISAS_HVC 8
121#define DISAS_SMC 9
122#define DISAS_YIELD 10
123
124#ifdef TARGET_AARCH64
125void a64_translate_init(void);
126void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);
127void gen_a64_set_pc_im(uint64_t val);
128void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
129 fprintf_function cpu_fprintf, int flags);
130#else
131static inline void a64_translate_init(void)
132{
133}
134
135static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
136{
137}
138
139static inline void gen_a64_set_pc_im(uint64_t val)
140{
141}
142
143static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
144 fprintf_function cpu_fprintf,
145 int flags)
146{
147}
148#endif
149
150void arm_test_cc(DisasCompare *cmp, int cc);
151void arm_free_cc(DisasCompare *cmp);
152void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
153void arm_gen_test_cc(int cc, TCGLabel *label);
154
155#endif
156