LXR qemu/target-microblaze/helper.c

   1/*
   2 *  MicroBlaze helper routines.
   3 *
   4 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
   5 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "cpu.h"
  23#include "qemu/host-utils.h"
  24#include "exec/log.h"
  25
  26#define D(x)
  27
  28#if defined(CONFIG_USER_ONLY)
  29
  30void mb_cpu_do_interrupt(CPUState *cs)
  31{
  32    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  33    CPUMBState *env = &cpu->env;
  34
  35    cs->exception_index = -1;
  36    env->res_addr = RES_ADDR_NONE;
  37    env->regs[14] = env->sregs[SR_PC];
  38}
  39
  40int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  41                            int mmu_idx)
  42{
  43    cs->exception_index = 0xaa;
  44    cpu_dump_state(cs, stderr, fprintf, 0);
  45    return 1;
  46}
  47
  48#else /* !CONFIG_USER_ONLY */
  49
  50int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  51                            int mmu_idx)
  52{
  53    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  54    CPUMBState *env = &cpu->env;
  55    unsigned int hit;
  56    unsigned int mmu_available;
  57    int r = 1;
  58    int prot;
  59
  60    mmu_available = 0;
  61    if (cpu->cfg.use_mmu) {
  62        mmu_available = 1;
  63        if ((cpu->cfg.pvr == C_PVR_FULL) &&
  64            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
  65            mmu_available = 0;
  66        }
  67    }
  68
  69    /* Translate if the MMU is available and enabled.  */
  70    if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
  71        target_ulong vaddr, paddr;
  72        struct microblaze_mmu_lookup lu;
  73
  74        hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
  75        if (hit) {
  76            vaddr = address & TARGET_PAGE_MASK;
  77            paddr = lu.paddr + vaddr - lu.vaddr;
  78
  79            qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
  80                    mmu_idx, vaddr, paddr, lu.prot);
  81            tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
  82            r = 0;
  83        } else {
  84            env->sregs[SR_EAR] = address;
  85            qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
  86                                        mmu_idx, address);
  87
  88            switch (lu.err) {
  89                case ERR_PROT:
  90                    env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
  91                    env->sregs[SR_ESR] |= (rw == 1) << 10;
  92                    break;
  93                case ERR_MISS:
  94                    env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
  95                    env->sregs[SR_ESR] |= (rw == 1) << 10;
  96                    break;
  97                default:
  98                    abort();
  99                    break;
 100            }
 101
 102            if (cs->exception_index == EXCP_MMU) {
 103                cpu_abort(cs, "recursive faults\n");
 104            }
 105
 106            /* TLB miss.  */
 107            cs->exception_index = EXCP_MMU;
 108        }
 109    } else {
 110        /* MMU disabled or not available.  */
 111        address &= TARGET_PAGE_MASK;
 112        prot = PAGE_BITS;
 113        tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
 114        r = 0;
 115    }
 116    return r;
 117}
 118
 119void mb_cpu_do_interrupt(CPUState *cs)
 120{
 121    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 122    CPUMBState *env = &cpu->env;
 123    uint32_t t;
 124
 125    /* IMM flag cannot propagate across a branch and into the dslot.  */
 126    assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
 127    assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
 128/*    assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions.  */
 129    env->res_addr = RES_ADDR_NONE;
 130    switch (cs->exception_index) {
 131        case EXCP_HW_EXCP:
 132            if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
 133                qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n");
 134                return;
 135            }
 136
 137            env->regs[17] = env->sregs[SR_PC] + 4;
 138            env->sregs[SR_ESR] &= ~(1 << 12);
 139
 140            /* Exception breaks branch + dslot sequence?  */
 141            if (env->iflags & D_FLAG) {
 142                env->sregs[SR_ESR] |= 1 << 12 ;
 143                env->sregs[SR_BTR] = env->btarget;
 144            }
 145
 146            /* Disable the MMU.  */
 147            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 148            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 149            env->sregs[SR_MSR] |= t;
 150            /* Exception in progress.  */
 151            env->sregs[SR_MSR] |= MSR_EIP;
 152
 153            qemu_log_mask(CPU_LOG_INT,
 154                          "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
 155                          env->sregs[SR_PC], env->sregs[SR_EAR],
 156                          env->sregs[SR_ESR], env->iflags);
 157            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 158            env->iflags &= ~(IMM_FLAG | D_FLAG);
 159            env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
 160            break;
 161
 162        case EXCP_MMU:
 163            env->regs[17] = env->sregs[SR_PC];
 164
 165            env->sregs[SR_ESR] &= ~(1 << 12);
 166            /* Exception breaks branch + dslot sequence?  */
 167            if (env->iflags & D_FLAG) {
 168                D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
 169                env->sregs[SR_ESR] |= 1 << 12 ;
 170                env->sregs[SR_BTR] = env->btarget;
 171
 172                /* Reexecute the branch.  */
 173                env->regs[17] -= 4;
 174                /* was the branch immprefixed?.  */
 175                if (env->bimm) {
 176                    qemu_log_mask(CPU_LOG_INT,
 177                                  "bimm exception at pc=%x iflags=%x\n",
 178                                  env->sregs[SR_PC], env->iflags);
 179                    env->regs[17] -= 4;
 180                    log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 181                }
 182            } else if (env->iflags & IMM_FLAG) {
 183                D(qemu_log("IMM_FLAG set at exception\n"));
 184                env->regs[17] -= 4;
 185            }
 186
 187            /* Disable the MMU.  */
 188            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 189            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 190            env->sregs[SR_MSR] |= t;
 191            /* Exception in progress.  */
 192            env->sregs[SR_MSR] |= MSR_EIP;
 193
 194            qemu_log_mask(CPU_LOG_INT,
 195                          "exception at pc=%x ear=%x iflags=%x\n",
 196                          env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
 197            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 198            env->iflags &= ~(IMM_FLAG | D_FLAG);
 199            env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
 200            break;
 201
 202        case EXCP_IRQ:
 203            assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
 204            assert(env->sregs[SR_MSR] & MSR_IE);
 205            assert(!(env->iflags & D_FLAG));
 206
 207            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 208
 209#if 0
 210#include "disas/disas.h"
 211
 212/* Useful instrumentation when debugging interrupt issues in either
 213   the models or in sw.  */
 214            {
 215                const char *sym;
 216
 217                sym = lookup_symbol(env->sregs[SR_PC]);
 218                if (sym
 219                    && (!strcmp("netif_rx", sym)
 220                        || !strcmp("process_backlog", sym))) {
 221
 222                    qemu_log(
 223                         "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
 224                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
 225                         sym);
 226
 227                    log_cpu_state(cs, 0);
 228                }
 229            }
 230#endif
 231            qemu_log_mask(CPU_LOG_INT,
 232                         "interrupt at pc=%x msr=%x %x iflags=%x\n",
 233                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 234
 235            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
 236                                    | MSR_UM | MSR_IE);
 237            env->sregs[SR_MSR] |= t;
 238
 239            env->regs[14] = env->sregs[SR_PC];
 240            env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10;
 241            //log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 242            break;
 243
 244        case EXCP_BREAK:
 245        case EXCP_HW_BREAK:
 246            assert(!(env->iflags & IMM_FLAG));
 247            assert(!(env->iflags & D_FLAG));
 248            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 249            qemu_log_mask(CPU_LOG_INT,
 250                        "break at pc=%x msr=%x %x iflags=%x\n",
 251                        env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 252            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 253            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 254            env->sregs[SR_MSR] |= t;
 255            env->sregs[SR_MSR] |= MSR_BIP;
 256            if (cs->exception_index == EXCP_HW_BREAK) {
 257                env->regs[16] = env->sregs[SR_PC];
 258                env->sregs[SR_MSR] |= MSR_BIP;
 259                env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18;
 260            } else
 261                env->sregs[SR_PC] = env->btarget;
 262            break;
 263        default:
 264            cpu_abort(cs, "unhandled exception type=%d\n",
 265                      cs->exception_index);
 266            break;
 267    }
 268}
 269
 270hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 271{
 272    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 273    CPUMBState *env = &cpu->env;
 274    target_ulong vaddr, paddr = 0;
 275    struct microblaze_mmu_lookup lu;
 276    unsigned int hit;
 277
 278    if (env->sregs[SR_MSR] & MSR_VM) {
 279        hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
 280        if (hit) {
 281            vaddr = addr & TARGET_PAGE_MASK;
 282            paddr = lu.paddr + vaddr - lu.vaddr;
 283        } else
 284            paddr = 0; /* ???.  */
 285    } else
 286        paddr = addr & TARGET_PAGE_MASK;
 287
 288    return paddr;
 289}
 290#endif
 291
 292bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 293{
 294    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 295    CPUMBState *env = &cpu->env;
 296
 297    if ((interrupt_request & CPU_INTERRUPT_HARD)
 298        && (env->sregs[SR_MSR] & MSR_IE)
 299        && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
 300        && !(env->iflags & (D_FLAG | IMM_FLAG))) {
 301        cs->exception_index = EXCP_IRQ;
 302        mb_cpu_do_interrupt(cs);
 303        return true;
 304    }
 305    return false;
 306}
 307