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20#ifndef CPU_OPENRISC_H
21#define CPU_OPENRISC_H
22
23#define TARGET_LONG_BITS 32
24
25#define CPUArchState struct CPUOpenRISCState
26
27
28struct OpenRISCCPU;
29
30#include "qemu-common.h"
31#include "exec/cpu-defs.h"
32#include "fpu/softfloat.h"
33#include "qom/cpu.h"
34
35#define TYPE_OPENRISC_CPU "or32-cpu"
36
37#define OPENRISC_CPU_CLASS(klass) \
38 OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
39#define OPENRISC_CPU(obj) \
40 OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
41#define OPENRISC_CPU_GET_CLASS(obj) \
42 OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
43
44
45
46
47
48
49
50
51typedef struct OpenRISCCPUClass {
52
53 CPUClass parent_class;
54
55
56 DeviceRealize parent_realize;
57 void (*parent_reset)(CPUState *cpu);
58} OpenRISCCPUClass;
59
60#define NB_MMU_MODES 3
61
62enum {
63 MMU_NOMMU_IDX = 0,
64 MMU_SUPERVISOR_IDX = 1,
65 MMU_USER_IDX = 2,
66};
67
68#define TARGET_PAGE_BITS 13
69
70#define TARGET_PHYS_ADDR_SPACE_BITS 32
71#define TARGET_VIRT_ADDR_SPACE_BITS 32
72
73#define SET_FP_CAUSE(reg, v) do {\
74 (reg) = ((reg) & ~(0x3f << 12)) | \
75 ((v & 0x3f) << 12);\
76 } while (0)
77#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
78#define UPDATE_FP_FLAGS(reg, v) do {\
79 (reg) |= ((v & 0x1f) << 2);\
80 } while (0)
81
82
83#define SPR_VR 0xFFFF003F
84
85
86#define D_FLAG 1
87
88
89#define NR_IRQS 32
90
91
92enum {
93 UPR_UP = (1 << 0),
94 UPR_DCP = (1 << 1),
95 UPR_ICP = (1 << 2),
96 UPR_DMP = (1 << 3),
97 UPR_IMP = (1 << 4),
98 UPR_MP = (1 << 5),
99 UPR_DUP = (1 << 6),
100 UPR_PCUR = (1 << 7),
101 UPR_PMP = (1 << 8),
102 UPR_PICP = (1 << 9),
103 UPR_TTP = (1 << 10),
104 UPR_CUP = (255 << 24),
105};
106
107
108enum {
109 CPUCFGR_NSGF = (15 << 0),
110 CPUCFGR_CGF = (1 << 4),
111 CPUCFGR_OB32S = (1 << 5),
112 CPUCFGR_OB64S = (1 << 6),
113 CPUCFGR_OF32S = (1 << 7),
114 CPUCFGR_OF64S = (1 << 8),
115 CPUCFGR_OV64S = (1 << 9),
116};
117
118
119enum {
120 DMMUCFGR_NTW = (3 << 0),
121 DMMUCFGR_NTS = (7 << 2),
122 DMMUCFGR_NAE = (7 << 5),
123 DMMUCFGR_CRI = (1 << 8),
124 DMMUCFGR_PRI = (1 << 9),
125 DMMUCFGR_TEIRI = (1 << 10),
126 DMMUCFGR_HTR = (1 << 11),
127};
128
129
130enum {
131 IMMUCFGR_NTW = (3 << 0),
132 IMMUCFGR_NTS = (7 << 2),
133 IMMUCFGR_NAE = (7 << 5),
134 IMMUCFGR_CRI = (1 << 8),
135 IMMUCFGR_PRI = (1 << 9),
136 IMMUCFGR_TEIRI = (1 << 10),
137 IMMUCFGR_HTR = (1 << 11),
138};
139
140
141enum {
142 FPCSR_FPEE = 1,
143 FPCSR_RM = (3 << 1),
144 FPCSR_OVF = (1 << 3),
145 FPCSR_UNF = (1 << 4),
146 FPCSR_SNF = (1 << 5),
147 FPCSR_QNF = (1 << 6),
148 FPCSR_ZF = (1 << 7),
149 FPCSR_IXF = (1 << 8),
150 FPCSR_IVF = (1 << 9),
151 FPCSR_INF = (1 << 10),
152 FPCSR_DZF = (1 << 11),
153};
154
155
156enum {
157 EXCP_RESET = 0x1,
158 EXCP_BUSERR = 0x2,
159 EXCP_DPF = 0x3,
160 EXCP_IPF = 0x4,
161 EXCP_TICK = 0x5,
162 EXCP_ALIGN = 0x6,
163 EXCP_ILLEGAL = 0x7,
164 EXCP_INT = 0x8,
165 EXCP_DTLBMISS = 0x9,
166 EXCP_ITLBMISS = 0xa,
167 EXCP_RANGE = 0xb,
168 EXCP_SYSCALL = 0xc,
169 EXCP_FPE = 0xd,
170 EXCP_TRAP = 0xe,
171 EXCP_NR,
172};
173
174
175enum {
176 SR_SM = (1 << 0),
177 SR_TEE = (1 << 1),
178 SR_IEE = (1 << 2),
179 SR_DCE = (1 << 3),
180 SR_ICE = (1 << 4),
181 SR_DME = (1 << 5),
182 SR_IME = (1 << 6),
183 SR_LEE = (1 << 7),
184 SR_CE = (1 << 8),
185 SR_F = (1 << 9),
186 SR_CY = (1 << 10),
187 SR_OV = (1 << 11),
188 SR_OVE = (1 << 12),
189 SR_DSX = (1 << 13),
190 SR_EPH = (1 << 14),
191 SR_FO = (1 << 15),
192 SR_SUMRA = (1 << 16),
193 SR_SCE = (1 << 17),
194};
195
196
197enum {
198 OPENRISC_FEATURE_NSGF = (15 << 0),
199 OPENRISC_FEATURE_CGF = (1 << 4),
200 OPENRISC_FEATURE_OB32S = (1 << 5),
201 OPENRISC_FEATURE_OB64S = (1 << 6),
202 OPENRISC_FEATURE_OF32S = (1 << 7),
203 OPENRISC_FEATURE_OF64S = (1 << 8),
204 OPENRISC_FEATURE_OV64S = (1 << 9),
205};
206
207
208enum {
209 TTMR_TP = (0xfffffff),
210 TTMR_IP = (1 << 28),
211 TTMR_IE = (1 << 29),
212 TTMR_M = (3 << 30),
213};
214
215
216enum {
217 TIMER_NONE = (0 << 30),
218 TIMER_INTR = (1 << 30),
219 TIMER_SHOT = (2 << 30),
220 TIMER_CONT = (3 << 30),
221};
222
223
224enum {
225 DTLB_WAYS = 1,
226 DTLB_SIZE = 64,
227 DTLB_MASK = (DTLB_SIZE-1),
228 ITLB_WAYS = 1,
229 ITLB_SIZE = 64,
230 ITLB_MASK = (ITLB_SIZE-1),
231};
232
233
234enum {
235 URE = (1 << 6),
236 UWE = (1 << 7),
237 SRE = (1 << 8),
238 SWE = (1 << 9),
239
240 SXE = (1 << 6),
241 UXE = (1 << 7),
242};
243
244
245enum {
246 TLBRET_INVALID = -3,
247 TLBRET_NOMATCH = -2,
248 TLBRET_BADADDR = -1,
249 TLBRET_MATCH = 0
250};
251
252typedef struct OpenRISCTLBEntry {
253 uint32_t mr;
254 uint32_t tr;
255} OpenRISCTLBEntry;
256
257#ifndef CONFIG_USER_ONLY
258typedef struct CPUOpenRISCTLBContext {
259 OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
260 OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
261
262 int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
263 hwaddr *physical,
264 int *prot,
265 target_ulong address, int rw);
266 int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
267 hwaddr *physical,
268 int *prot,
269 target_ulong address, int rw);
270} CPUOpenRISCTLBContext;
271#endif
272
273typedef struct CPUOpenRISCState {
274 target_ulong gpr[32];
275 target_ulong pc;
276 target_ulong npc;
277 target_ulong ppc;
278 target_ulong jmp_pc;
279
280 target_ulong machi;
281 target_ulong maclo;
282
283 target_ulong fpmaddhi;
284 target_ulong fpmaddlo;
285
286 target_ulong epcr;
287 target_ulong eear;
288
289 uint32_t sr;
290 uint32_t vr;
291 uint32_t upr;
292 uint32_t cpucfgr;
293 uint32_t dmmucfgr;
294 uint32_t immucfgr;
295 uint32_t esr;
296 uint32_t fpcsr;
297 float_status fp_status;
298
299 uint32_t flags;
300
301 uint32_t btaken;
302
303 CPU_COMMON
304
305
306#ifndef CONFIG_USER_ONLY
307 CPUOpenRISCTLBContext * tlb;
308
309 QEMUTimer *timer;
310 uint32_t ttmr;
311 uint32_t ttcr;
312
313 uint32_t picmr;
314 uint32_t picsr;
315#endif
316 void *irq[32];
317} CPUOpenRISCState;
318
319
320
321
322
323
324
325typedef struct OpenRISCCPU {
326
327 CPUState parent_obj;
328
329
330 CPUOpenRISCState env;
331
332 uint32_t feature;
333} OpenRISCCPU;
334
335static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
336{
337 return container_of(env, OpenRISCCPU, env);
338}
339
340#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
341
342#define ENV_OFFSET offsetof(OpenRISCCPU, env)
343
344OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
345
346void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
347int cpu_openrisc_exec(CPUState *cpu);
348void openrisc_cpu_do_interrupt(CPUState *cpu);
349bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
350void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
351 fprintf_function cpu_fprintf, int flags);
352hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
353int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
354int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
355void openrisc_translate_init(void);
356int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
357 int rw, int mmu_idx);
358int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
359
360#define cpu_list cpu_openrisc_list
361#define cpu_exec cpu_openrisc_exec
362#define cpu_signal_handler cpu_openrisc_signal_handler
363
364#ifndef CONFIG_USER_ONLY
365extern const struct VMStateDescription vmstate_openrisc_cpu;
366
367
368void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
369
370
371void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
372void cpu_openrisc_count_update(OpenRISCCPU *cpu);
373void cpu_openrisc_timer_update(OpenRISCCPU *cpu);
374void cpu_openrisc_count_start(OpenRISCCPU *cpu);
375void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
376
377void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
378int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
379 hwaddr *physical,
380 int *prot, target_ulong address, int rw);
381int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
382 hwaddr *physical,
383 int *prot, target_ulong address, int rw);
384int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
385 hwaddr *physical,
386 int *prot, target_ulong address, int rw);
387#endif
388
389#define cpu_init(cpu_model) CPU(cpu_openrisc_init(cpu_model))
390
391#include "exec/cpu-all.h"
392
393static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
394 target_ulong *pc,
395 target_ulong *cs_base, int *flags)
396{
397 *pc = env->pc;
398 *cs_base = 0;
399
400 *flags = (env->flags & D_FLAG);
401}
402
403static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
404{
405 if (!(env->sr & SR_IME)) {
406 return MMU_NOMMU_IDX;
407 }
408 return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
409}
410
411#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
412
413#include "exec/exec-all.h"
414
415#endif
416