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19#ifndef _CPU_SH4_H
20#define _CPU_SH4_H
21
22#include "qemu-common.h"
23
24#define TARGET_LONG_BITS 32
25
26
27#define SH_CPU_SH7750 (1 << 0)
28#define SH_CPU_SH7750S (1 << 1)
29#define SH_CPU_SH7750R (1 << 2)
30#define SH_CPU_SH7751 (1 << 3)
31#define SH_CPU_SH7751R (1 << 4)
32#define SH_CPU_SH7785 (1 << 5)
33#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
34#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
35
36#define CPUArchState struct CPUSH4State
37
38#include "exec/cpu-defs.h"
39
40#include "fpu/softfloat.h"
41
42#define TARGET_PAGE_BITS 12
43
44#define TARGET_PHYS_ADDR_SPACE_BITS 32
45#define TARGET_VIRT_ADDR_SPACE_BITS 32
46
47#define SR_MD 30
48#define SR_RB 29
49#define SR_BL 28
50#define SR_FD 15
51#define SR_M 9
52#define SR_Q 8
53#define SR_I3 7
54#define SR_I2 6
55#define SR_I1 5
56#define SR_I0 4
57#define SR_S 1
58#define SR_T 0
59
60#define FPSCR_MASK (0x003fffff)
61#define FPSCR_FR (1 << 21)
62#define FPSCR_SZ (1 << 20)
63#define FPSCR_PR (1 << 19)
64#define FPSCR_DN (1 << 18)
65#define FPSCR_CAUSE_MASK (0x3f << 12)
66#define FPSCR_CAUSE_SHIFT (12)
67#define FPSCR_CAUSE_E (1 << 17)
68#define FPSCR_CAUSE_V (1 << 16)
69#define FPSCR_CAUSE_Z (1 << 15)
70#define FPSCR_CAUSE_O (1 << 14)
71#define FPSCR_CAUSE_U (1 << 13)
72#define FPSCR_CAUSE_I (1 << 12)
73#define FPSCR_ENABLE_MASK (0x1f << 7)
74#define FPSCR_ENABLE_SHIFT (7)
75#define FPSCR_ENABLE_V (1 << 11)
76#define FPSCR_ENABLE_Z (1 << 10)
77#define FPSCR_ENABLE_O (1 << 9)
78#define FPSCR_ENABLE_U (1 << 8)
79#define FPSCR_ENABLE_I (1 << 7)
80#define FPSCR_FLAG_MASK (0x1f << 2)
81#define FPSCR_FLAG_SHIFT (2)
82#define FPSCR_FLAG_V (1 << 6)
83#define FPSCR_FLAG_Z (1 << 5)
84#define FPSCR_FLAG_O (1 << 4)
85#define FPSCR_FLAG_U (1 << 3)
86#define FPSCR_FLAG_I (1 << 2)
87#define FPSCR_RM_MASK (0x03 << 0)
88#define FPSCR_RM_NEAREST (0 << 0)
89#define FPSCR_RM_ZERO (1 << 0)
90
91#define DELAY_SLOT (1 << 0)
92#define DELAY_SLOT_CONDITIONAL (1 << 1)
93#define DELAY_SLOT_TRUE (1 << 2)
94#define DELAY_SLOT_CLEARME (1 << 3)
95
96
97
98
99
100
101
102typedef struct tlb_t {
103 uint32_t vpn;
104 uint32_t ppn;
105 uint32_t size;
106 uint8_t asid;
107 uint8_t v:1;
108 uint8_t sz:2;
109 uint8_t sh:1;
110 uint8_t c:1;
111 uint8_t pr:2;
112 uint8_t d:1;
113 uint8_t wt:1;
114 uint8_t sa:3;
115 uint8_t tc:1;
116} tlb_t;
117
118#define UTLB_SIZE 64
119#define ITLB_SIZE 4
120
121#define NB_MMU_MODES 2
122#define TARGET_INSN_START_EXTRA_WORDS 1
123
124enum sh_features {
125 SH_FEATURE_SH4A = 1,
126 SH_FEATURE_BCR3_AND_BCR4 = 2,
127};
128
129typedef struct memory_content {
130 uint32_t address;
131 uint32_t value;
132 struct memory_content *next;
133} memory_content;
134
135typedef struct CPUSH4State {
136 uint32_t flags;
137 uint32_t gregs[24];
138 float32 fregs[32];
139 uint32_t sr;
140 uint32_t sr_m;
141 uint32_t sr_q;
142 uint32_t sr_t;
143 uint32_t ssr;
144 uint32_t spc;
145 uint32_t gbr;
146 uint32_t vbr;
147 uint32_t sgr;
148 uint32_t dbr;
149 uint32_t pc;
150 uint32_t delayed_pc;
151 uint32_t mach;
152 uint32_t macl;
153 uint32_t pr;
154 uint32_t fpscr;
155 uint32_t fpul;
156
157
158 float_status fp_status;
159
160
161 uint32_t mmucr;
162 uint32_t pteh;
163 uint32_t ptel;
164 uint32_t ptea;
165 uint32_t ttb;
166 uint32_t tea;
167 uint32_t tra;
168 uint32_t expevt;
169 uint32_t intevt;
170
171 tlb_t itlb[ITLB_SIZE];
172 tlb_t utlb[UTLB_SIZE];
173
174 uint32_t ldst;
175
176 CPU_COMMON
177
178
179 int id;
180
181
182 uint32_t features;
183
184 void *intc_handle;
185 int in_sleep;
186 memory_content *movcal_backup;
187 memory_content **movcal_backup_tail;
188} CPUSH4State;
189
190#include "cpu-qom.h"
191
192void sh4_translate_init(void);
193SuperHCPU *cpu_sh4_init(const char *cpu_model);
194int cpu_sh4_exec(CPUState *s);
195int cpu_sh4_signal_handler(int host_signum, void *pinfo,
196 void *puc);
197int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
198 int mmu_idx);
199
200void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
201#if !defined(CONFIG_USER_ONLY)
202void cpu_sh4_invalidate_tlb(CPUSH4State *s);
203uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
204 hwaddr addr);
205void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
206 uint32_t mem_value);
207uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
208 hwaddr addr);
209void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
210 uint32_t mem_value);
211uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
212 hwaddr addr);
213void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
214 uint32_t mem_value);
215uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
216 hwaddr addr);
217void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
218 uint32_t mem_value);
219#endif
220
221int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
222
223void cpu_load_tlb(CPUSH4State * env);
224
225#define cpu_init(cpu_model) CPU(cpu_sh4_init(cpu_model))
226
227#define cpu_exec cpu_sh4_exec
228#define cpu_signal_handler cpu_sh4_signal_handler
229#define cpu_list sh4_cpu_list
230
231
232#define MMU_MODE0_SUFFIX _kernel
233#define MMU_MODE1_SUFFIX _user
234#define MMU_USER_IDX 1
235static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
236{
237 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
238}
239
240#include "exec/cpu-all.h"
241
242
243enum {
244
245 ACCESS_PRIV = 0x01,
246
247 ACCESS_WRITE = 0x02,
248
249 ACCESS_CODE = 0x10,
250 ACCESS_INT = 0x20
251};
252
253
254#define MMUCR 0x1F000010
255#define MMUCR_AT (1<<0)
256#define MMUCR_TI (1<<2)
257#define MMUCR_SV (1<<8)
258#define MMUCR_URC_BITS (6)
259#define MMUCR_URC_OFFSET (10)
260#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
261#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
262static inline int cpu_mmucr_urc (uint32_t mmucr)
263{
264 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
265}
266
267
268#define PTEH_ASID_BITS (8)
269#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
270#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
271#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
272#define PTEH_VPN_BITS (22)
273#define PTEH_VPN_OFFSET (10)
274#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
275#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
276static inline int cpu_pteh_vpn (uint32_t pteh)
277{
278 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
279}
280
281
282#define PTEL_V (1 << 8)
283#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
284#define PTEL_C (1 << 3)
285#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
286#define PTEL_D (1 << 2)
287#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
288#define PTEL_SH (1 << 1)
289#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
290#define PTEL_WT (1 << 0)
291#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
292
293#define PTEL_SZ_HIGH_OFFSET (7)
294#define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
295#define PTEL_SZ_LOW_OFFSET (4)
296#define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
297static inline int cpu_ptel_sz (uint32_t ptel)
298{
299 int sz;
300 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET;
301 sz <<= 1;
302 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET;
303 return sz;
304}
305
306#define PTEL_PPN_BITS (19)
307#define PTEL_PPN_OFFSET (10)
308#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
309#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
310static inline int cpu_ptel_ppn (uint32_t ptel)
311{
312 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
313}
314
315#define PTEL_PR_BITS (2)
316#define PTEL_PR_OFFSET (5)
317#define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
318#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
319static inline int cpu_ptel_pr (uint32_t ptel)
320{
321 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
322}
323
324
325#define PTEA_SA_BITS (3)
326#define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
327#define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
328#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
329#define PTEA_TC (1 << 3)
330#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
331
332#define TB_FLAG_PENDING_MOVCA (1 << 4)
333
334static inline target_ulong cpu_read_sr(CPUSH4State *env)
335{
336 return env->sr | (env->sr_m << SR_M) |
337 (env->sr_q << SR_Q) |
338 (env->sr_t << SR_T);
339}
340
341static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
342{
343 env->sr_m = (sr >> SR_M) & 1;
344 env->sr_q = (sr >> SR_Q) & 1;
345 env->sr_t = (sr >> SR_T) & 1;
346 env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
347}
348
349static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
350 target_ulong *cs_base, int *flags)
351{
352 *pc = env->pc;
353 *cs_base = 0;
354 *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
355 | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME))
356 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))
357 | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))
358 | (env->sr & (1u << SR_FD))
359 | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0);
360}
361
362#include "exec/exec-all.h"
363
364#endif
365