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19#ifndef CPU_TILEGX_H
20#define CPU_TILEGX_H
21
22#include "qemu-common.h"
23
24#define TARGET_LONG_BITS 64
25
26#define CPUArchState struct CPUTLGState
27
28#include "exec/cpu-defs.h"
29
30
31
32#define TILEGX_R_RE 0
33#define TILEGX_R_ERR 1
34#define TILEGX_R_NR 10
35#define TILEGX_R_BP 52
36#define TILEGX_R_TP 53
37#define TILEGX_R_SP 54
38#define TILEGX_R_LR 55
39#define TILEGX_R_COUNT 56
40#define TILEGX_R_SN 56
41#define TILEGX_R_IDN0 57
42#define TILEGX_R_IDN1 58
43#define TILEGX_R_UDN0 59
44#define TILEGX_R_UDN1 60
45#define TILEGX_R_UDN2 61
46#define TILEGX_R_UDN3 62
47#define TILEGX_R_ZERO 63
48#define TILEGX_R_NOREG 255
49
50
51enum {
52 TILEGX_SPR_CMPEXCH = 0,
53 TILEGX_SPR_CRITICAL_SEC = 1,
54 TILEGX_SPR_SIM_CONTROL = 2,
55 TILEGX_SPR_EX_CONTEXT_0_0 = 3,
56 TILEGX_SPR_EX_CONTEXT_0_1 = 4,
57 TILEGX_SPR_COUNT
58};
59
60
61typedef enum {
62 TILEGX_EXCP_NONE = 0,
63 TILEGX_EXCP_SYSCALL = 1,
64 TILEGX_EXCP_SIGNAL = 2,
65 TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
66 TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
67 TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
68 TILEGX_EXCP_OPCODE_CMPEXCH4 = 0x104,
69 TILEGX_EXCP_OPCODE_EXCH = 0x105,
70 TILEGX_EXCP_OPCODE_EXCH4 = 0x106,
71 TILEGX_EXCP_OPCODE_FETCHADD = 0x107,
72 TILEGX_EXCP_OPCODE_FETCHADD4 = 0x108,
73 TILEGX_EXCP_OPCODE_FETCHADDGEZ = 0x109,
74 TILEGX_EXCP_OPCODE_FETCHADDGEZ4 = 0x10a,
75 TILEGX_EXCP_OPCODE_FETCHAND = 0x10b,
76 TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
77 TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
78 TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
79 TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
80 TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
81 TILEGX_EXCP_UNALIGNMENT = 0x201,
82 TILEGX_EXCP_DBUG_BREAK = 0x301
83} TileExcp;
84
85typedef struct CPUTLGState {
86 uint64_t regs[TILEGX_R_COUNT];
87 uint64_t spregs[TILEGX_SPR_COUNT];
88 uint64_t pc;
89
90#if defined(CONFIG_USER_ONLY)
91 uint64_t excaddr;
92 uint64_t atomic_srca;
93 uint64_t atomic_srcb;
94 uint32_t atomic_dstr;
95 uint32_t signo;
96 uint32_t sigcode;
97#endif
98
99 CPU_COMMON
100} CPUTLGState;
101
102#include "qom/cpu.h"
103
104#define TYPE_TILEGX_CPU "tilegx-cpu"
105
106#define TILEGX_CPU_CLASS(klass) \
107 OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
108#define TILEGX_CPU(obj) \
109 OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU)
110#define TILEGX_CPU_GET_CLASS(obj) \
111 OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU)
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119
120typedef struct TileGXCPUClass {
121
122 CPUClass parent_class;
123
124
125 DeviceRealize parent_realize;
126 void (*parent_reset)(CPUState *cpu);
127} TileGXCPUClass;
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133
134
135typedef struct TileGXCPU {
136
137 CPUState parent_obj;
138
139
140 CPUTLGState env;
141} TileGXCPU;
142
143static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
144{
145 return container_of(env, TileGXCPU, env);
146}
147
148#define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e))
149
150#define ENV_OFFSET offsetof(TileGXCPU, env)
151
152
153#define TARGET_PAGE_BITS 16
154#define TARGET_PHYS_ADDR_SPACE_BITS 42
155#define TARGET_VIRT_ADDR_SPACE_BITS 64
156#define MMU_USER_IDX 0
157
158#include "exec/cpu-all.h"
159
160void tilegx_tcg_init(void);
161int cpu_tilegx_exec(CPUState *s);
162int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
163
164TileGXCPU *cpu_tilegx_init(const char *cpu_model);
165
166#define cpu_init(cpu_model) CPU(cpu_tilegx_init(cpu_model))
167
168#define cpu_exec cpu_tilegx_exec
169#define cpu_signal_handler cpu_tilegx_signal_handler
170
171static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
172 target_ulong *cs_base, int *flags)
173{
174 *pc = env->pc;
175 *cs_base = 0;
176 *flags = 0;
177}
178
179#include "exec/exec-all.h"
180
181#endif
182