LXR qemu/hw/misc/arm11scu.c

   1/*
   2 * ARM11MPCore Snoop Control Unit (SCU) emulation
   3 *
   4 * Copyright (c) 2006-2007 CodeSourcery.
   5 * Copyright (c) 2013 SUSE LINUX Products GmbH
   6 * Written by Paul Brook and Andreas Färber
   7 *
   8 * This code is licensed under the GPL.
   9 */
  10
  11#include "qemu/osdep.h"
  12#include "hw/misc/arm11scu.h"
  13
  14static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
  15                                unsigned size)
  16{
  17    ARM11SCUState *s = (ARM11SCUState *)opaque;
  18    int id;
  19    /* SCU */
  20    switch (offset) {
  21    case 0x00: /* Control.  */
  22        return s->control;
  23    case 0x04: /* Configuration.  */
  24        id = ((1 << s->num_cpu) - 1) << 4;
  25        return id | (s->num_cpu - 1);
  26    case 0x08: /* CPU status.  */
  27        return 0;
  28    case 0x0c: /* Invalidate all.  */
  29        return 0;
  30    default:
  31        qemu_log_mask(LOG_GUEST_ERROR,
  32                      "mpcore_priv_read: Bad offset %x\n", (int)offset);
  33        return 0;
  34    }
  35}
  36
  37static void mpcore_scu_write(void *opaque, hwaddr offset,
  38                             uint64_t value, unsigned size)
  39{
  40    ARM11SCUState *s = (ARM11SCUState *)opaque;
  41    /* SCU */
  42    switch (offset) {
  43    case 0: /* Control register.  */
  44        s->control = value & 1;
  45        break;
  46    case 0x0c: /* Invalidate all.  */
  47        /* This is a no-op as cache is not emulated.  */
  48        break;
  49    default:
  50        qemu_log_mask(LOG_GUEST_ERROR,
  51                      "mpcore_priv_read: Bad offset %x\n", (int)offset);
  52    }
  53}
  54
  55static const MemoryRegionOps mpcore_scu_ops = {
  56    .read = mpcore_scu_read,
  57    .write = mpcore_scu_write,
  58    .endianness = DEVICE_NATIVE_ENDIAN,
  59};
  60
  61static void arm11_scu_realize(DeviceState *dev, Error **errp)
  62{
  63}
  64
  65static void arm11_scu_init(Object *obj)
  66{
  67    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  68    ARM11SCUState *s = ARM11_SCU(obj);
  69
  70    memory_region_init_io(&s->iomem, OBJECT(s),
  71                          &mpcore_scu_ops, s, "mpcore-scu", 0x100);
  72    sysbus_init_mmio(sbd, &s->iomem);
  73}
  74
  75static Property arm11_scu_properties[] = {
  76    DEFINE_PROP_UINT32("num-cpu", ARM11SCUState, num_cpu, 1),
  77    DEFINE_PROP_END_OF_LIST()
  78};
  79
  80static void arm11_scu_class_init(ObjectClass *oc, void *data)
  81{
  82    DeviceClass *dc = DEVICE_CLASS(oc);
  83
  84    dc->realize = arm11_scu_realize;
  85    dc->props = arm11_scu_properties;
  86}
  87
  88static const TypeInfo arm11_scu_type_info = {
  89    .name          = TYPE_ARM11_SCU,
  90    .parent        = TYPE_SYS_BUS_DEVICE,
  91    .instance_size = sizeof(ARM11SCUState),
  92    .instance_init = arm11_scu_init,
  93    .class_init    = arm11_scu_class_init,
  94};
  95
  96static void arm11_scu_register_types(void)
  97{
  98    type_register_static(&arm11_scu_type_info);
  99}
 100
 101type_init(arm11_scu_register_types)
 102