LXR qemu/hw/misc/arm

   1/*
   2 * ARM dummy L210, L220, PL310 cache controller.
   3 *
   4 * Copyright (c) 2010-2012 Calxeda
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2 or any later version, as published by the Free Software
   9 * Foundation.
  10 *
  11 * This program is distributed in the hope it will be useful, but WITHOUT
  12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 * more details.
  15 *
  16 * You should have received a copy of the GNU General Public License along with
  17 * this program.  If not, see <http://www.gnu.org/licenses/>.
  18 *
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "hw/sysbus.h"
  23
  24/* L2C-310 r3p2 */
  25#define CACHE_ID 0x410000c8
  26
  27#define TYPE_ARM_L2X0 "l2x0"
  28#define ARM_L2X0(obj) OBJECT_CHECK(L2x0State, (obj), TYPE_ARM_L2X0)
  29
  30typedef struct L2x0State {
  31    SysBusDevice parent_obj;
  32
  33    MemoryRegion iomem;
  34    uint32_t cache_type;
  35    uint32_t ctrl;
  36    uint32_t aux_ctrl;
  37    uint32_t data_ctrl;
  38    uint32_t tag_ctrl;
  39    uint32_t filter_start;
  40    uint32_t filter_end;
  41} L2x0State;
  42
  43static const VMStateDescription vmstate_l2x0 = {
  44    .name = "l2x0",
  45    .version_id = 1,
  46    .minimum_version_id = 1,
  47    .fields = (VMStateField[]) {
  48        VMSTATE_UINT32(ctrl, L2x0State),
  49        VMSTATE_UINT32(aux_ctrl, L2x0State),
  50        VMSTATE_UINT32(data_ctrl, L2x0State),
  51        VMSTATE_UINT32(tag_ctrl, L2x0State),
  52        VMSTATE_UINT32(filter_start, L2x0State),
  53        VMSTATE_UINT32(filter_end, L2x0State),
  54        VMSTATE_END_OF_LIST()
  55    }
  56};
  57
  58
  59static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
  60                               unsigned size)
  61{
  62    uint32_t cache_data;
  63    L2x0State *s = (L2x0State *)opaque;
  64    offset &= 0xfff;
  65    if (offset >= 0x730 && offset < 0x800) {
  66        return 0; /* cache ops complete */
  67    }
  68    switch (offset) {
  69    case 0:
  70        return CACHE_ID;
  71    case 0x4:
  72        /* aux_ctrl values affect cache_type values */
  73        cache_data = (s->aux_ctrl & (7 << 17)) >> 15;
  74        cache_data |= (s->aux_ctrl & (1 << 16)) >> 16;
  75        return s->cache_type |= (cache_data << 18) | (cache_data << 6);
  76    case 0x100:
  77        return s->ctrl;
  78    case 0x104:
  79        return s->aux_ctrl;
  80    case 0x108:
  81        return s->tag_ctrl;
  82    case 0x10C:
  83        return s->data_ctrl;
  84    case 0xC00:
  85        return s->filter_start;
  86    case 0xC04:
  87        return s->filter_end;
  88    case 0xF40:
  89        return 0;
  90    case 0xF60:
  91        return 0;
  92    case 0xF80:
  93        return 0;
  94    default:
  95        qemu_log_mask(LOG_GUEST_ERROR,
  96                      "l2x0_priv_read: Bad offset %x\n", (int)offset);
  97        break;
  98    }
  99    return 0;
 100}
 101
 102static void l2x0_priv_write(void *opaque, hwaddr offset,
 103                            uint64_t value, unsigned size)
 104{
 105    L2x0State *s = (L2x0State *)opaque;
 106    offset &= 0xfff;
 107    if (offset >= 0x730 && offset < 0x800) {
 108        /* ignore */
 109        return;
 110    }
 111    switch (offset) {
 112    case 0x100:
 113        s->ctrl = value & 1;
 114        break;
 115    case 0x104:
 116        s->aux_ctrl = value;
 117        break;
 118    case 0x108:
 119        s->tag_ctrl = value;
 120        break;
 121    case 0x10C:
 122        s->data_ctrl = value;
 123        break;
 124    case 0xC00:
 125        s->filter_start = value;
 126        break;
 127    case 0xC04:
 128        s->filter_end = value;
 129        break;
 130    case 0xF40:
 131        return;
 132    case 0xF60:
 133        return;
 134    case 0xF80:
 135        return;
 136    default:
 137        qemu_log_mask(LOG_GUEST_ERROR,
 138                      "l2x0_priv_write: Bad offset %x\n", (int)offset);
 139        break;
 140    }
 141}
 142
 143static void l2x0_priv_reset(DeviceState *dev)
 144{
 145    L2x0State *s = ARM_L2X0(dev);
 146
 147    s->ctrl = 0;
 148    s->aux_ctrl = 0x02020000;
 149    s->tag_ctrl = 0;
 150    s->data_ctrl = 0;
 151    s->filter_start = 0;
 152    s->filter_end = 0;
 153}
 154
 155static const MemoryRegionOps l2x0_mem_ops = {
 156    .read = l2x0_priv_read,
 157    .write = l2x0_priv_write,
 158    .endianness = DEVICE_NATIVE_ENDIAN,
 159 };
 160
 161static int l2x0_priv_init(SysBusDevice *dev)
 162{
 163    L2x0State *s = ARM_L2X0(dev);
 164
 165    memory_region_init_io(&s->iomem, OBJECT(dev), &l2x0_mem_ops, s,
 166                          "l2x0_cc", 0x1000);
 167    sysbus_init_mmio(dev, &s->iomem);
 168    return 0;
 169}
 170
 171static Property l2x0_properties[] = {
 172    DEFINE_PROP_UINT32("cache-type", L2x0State, cache_type, 0x1c100100),
 173    DEFINE_PROP_END_OF_LIST(),
 174};
 175
 176static void l2x0_class_init(ObjectClass *klass, void *data)
 177{
 178    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 179    DeviceClass *dc = DEVICE_CLASS(klass);
 180
 181    k->init = l2x0_priv_init;
 182    dc->vmsd = &vmstate_l2x0;
 183    dc->props = l2x0_properties;
 184    dc->reset = l2x0_priv_reset;
 185}
 186
 187static const TypeInfo l2x0_info = {
 188    .name = TYPE_ARM_L2X0,
 189    .parent = TYPE_SYS_BUS_DEVICE,
 190    .instance_size = sizeof(L2x0State),
 191    .class_init = l2x0_class_init,
 192};
 193
 194static void l2x0_register_types(void)
 195{
 196    type_register_static(&l2x0_info);
 197}
 198
 199type_init(l2x0_register_types)
 200