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26#include "qemu/osdep.h"
27#include "hw/sysbus.h"
28#include "hw/scsi/esp.h"
29#include "trace.h"
30#include "qapi/error.h"
31#include "qemu/log.h"
32
33
34
35
36
37
38
39
40
41static void esp_raise_irq(ESPState *s)
42{
43 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
44 s->rregs[ESP_RSTAT] |= STAT_INT;
45 qemu_irq_raise(s->irq);
46 trace_esp_raise_irq();
47 }
48}
49
50static void esp_lower_irq(ESPState *s)
51{
52 if (s->rregs[ESP_RSTAT] & STAT_INT) {
53 s->rregs[ESP_RSTAT] &= ~STAT_INT;
54 qemu_irq_lower(s->irq);
55 trace_esp_lower_irq();
56 }
57}
58
59void esp_dma_enable(ESPState *s, int irq, int level)
60{
61 if (level) {
62 s->dma_enabled = 1;
63 trace_esp_dma_enable();
64 if (s->dma_cb) {
65 s->dma_cb(s);
66 s->dma_cb = NULL;
67 }
68 } else {
69 trace_esp_dma_disable();
70 s->dma_enabled = 0;
71 }
72}
73
74void esp_request_cancelled(SCSIRequest *req)
75{
76 ESPState *s = req->hba_private;
77
78 if (req == s->current_req) {
79 scsi_req_unref(s->current_req);
80 s->current_req = NULL;
81 s->current_dev = NULL;
82 }
83}
84
85static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen)
86{
87 uint32_t dmalen;
88 int target;
89
90 target = s->wregs[ESP_WBUSID] & BUSID_DID;
91 if (s->dma) {
92 dmalen = s->rregs[ESP_TCLO];
93 dmalen |= s->rregs[ESP_TCMID] << 8;
94 dmalen |= s->rregs[ESP_TCHI] << 16;
95 if (dmalen > buflen) {
96 return 0;
97 }
98 s->dma_memory_read(s->dma_opaque, buf, dmalen);
99 } else {
100 dmalen = s->ti_size;
101 if (dmalen > TI_BUFSZ) {
102 return 0;
103 }
104 memcpy(buf, s->ti_buf, dmalen);
105 buf[0] = buf[2] >> 5;
106 }
107 trace_esp_get_cmd(dmalen, target);
108
109 s->ti_size = 0;
110 s->ti_rptr = 0;
111 s->ti_wptr = 0;
112
113 if (s->current_req) {
114
115 scsi_req_cancel(s->current_req);
116 s->async_len = 0;
117 }
118
119 s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
120 if (!s->current_dev) {
121
122 s->rregs[ESP_RSTAT] = 0;
123 s->rregs[ESP_RINTR] = INTR_DC;
124 s->rregs[ESP_RSEQ] = SEQ_0;
125 esp_raise_irq(s);
126 return 0;
127 }
128 return dmalen;
129}
130
131static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
132{
133 int32_t datalen;
134 int lun;
135 SCSIDevice *current_lun;
136
137 trace_esp_do_busid_cmd(busid);
138 lun = busid & 7;
139 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
140 s->current_req = scsi_req_new(current_lun, 0, lun, buf, s);
141 datalen = scsi_req_enqueue(s->current_req);
142 s->ti_size = datalen;
143 if (datalen != 0) {
144 s->rregs[ESP_RSTAT] = STAT_TC;
145 s->dma_left = 0;
146 s->dma_counter = 0;
147 if (datalen > 0) {
148 s->rregs[ESP_RSTAT] |= STAT_DI;
149 } else {
150 s->rregs[ESP_RSTAT] |= STAT_DO;
151 }
152 scsi_req_continue(s->current_req);
153 }
154 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
155 s->rregs[ESP_RSEQ] = SEQ_CD;
156 esp_raise_irq(s);
157}
158
159static void do_cmd(ESPState *s, uint8_t *buf)
160{
161 uint8_t busid = buf[0];
162
163 do_busid_cmd(s, &buf[1], busid);
164}
165
166static void handle_satn(ESPState *s)
167{
168 uint8_t buf[32];
169 int len;
170
171 if (s->dma && !s->dma_enabled) {
172 s->dma_cb = handle_satn;
173 return;
174 }
175 len = get_cmd(s, buf, sizeof(buf));
176 if (len)
177 do_cmd(s, buf);
178}
179
180static void handle_s_without_atn(ESPState *s)
181{
182 uint8_t buf[32];
183 int len;
184
185 if (s->dma && !s->dma_enabled) {
186 s->dma_cb = handle_s_without_atn;
187 return;
188 }
189 len = get_cmd(s, buf, sizeof(buf));
190 if (len) {
191 do_busid_cmd(s, buf, 0);
192 }
193}
194
195static void handle_satn_stop(ESPState *s)
196{
197 if (s->dma && !s->dma_enabled) {
198 s->dma_cb = handle_satn_stop;
199 return;
200 }
201 s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf));
202 if (s->cmdlen) {
203 trace_esp_handle_satn_stop(s->cmdlen);
204 s->do_cmd = 1;
205 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
206 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
207 s->rregs[ESP_RSEQ] = SEQ_CD;
208 esp_raise_irq(s);
209 }
210}
211
212static void write_response(ESPState *s)
213{
214 trace_esp_write_response(s->status);
215 s->ti_buf[0] = s->status;
216 s->ti_buf[1] = 0;
217 if (s->dma) {
218 s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
219 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
220 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
221 s->rregs[ESP_RSEQ] = SEQ_CD;
222 } else {
223 s->ti_size = 2;
224 s->ti_rptr = 0;
225 s->ti_wptr = 2;
226 s->rregs[ESP_RFLAGS] = 2;
227 }
228 esp_raise_irq(s);
229}
230
231static void esp_dma_done(ESPState *s)
232{
233 s->rregs[ESP_RSTAT] |= STAT_TC;
234 s->rregs[ESP_RINTR] = INTR_BS;
235 s->rregs[ESP_RSEQ] = 0;
236 s->rregs[ESP_RFLAGS] = 0;
237 s->rregs[ESP_TCLO] = 0;
238 s->rregs[ESP_TCMID] = 0;
239 s->rregs[ESP_TCHI] = 0;
240 esp_raise_irq(s);
241}
242
243static void esp_do_dma(ESPState *s)
244{
245 uint32_t len;
246 int to_device;
247
248 len = s->dma_left;
249 if (s->do_cmd) {
250 trace_esp_do_dma(s->cmdlen, len);
251 assert (s->cmdlen <= sizeof(s->cmdbuf) &&
252 len <= sizeof(s->cmdbuf) - s->cmdlen);
253 s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
254 return;
255 }
256 if (s->async_len == 0) {
257
258 return;
259 }
260 if (len > s->async_len) {
261 len = s->async_len;
262 }
263 to_device = (s->ti_size < 0);
264 if (to_device) {
265 s->dma_memory_read(s->dma_opaque, s->async_buf, len);
266 } else {
267 s->dma_memory_write(s->dma_opaque, s->async_buf, len);
268 }
269 s->dma_left -= len;
270 s->async_buf += len;
271 s->async_len -= len;
272 if (to_device)
273 s->ti_size += len;
274 else
275 s->ti_size -= len;
276 if (s->async_len == 0) {
277 scsi_req_continue(s->current_req);
278
279
280
281 if (to_device || s->dma_left != 0 || s->ti_size == 0) {
282 return;
283 }
284 }
285
286
287 esp_dma_done(s);
288}
289
290void esp_command_complete(SCSIRequest *req, uint32_t status,
291 size_t resid)
292{
293 ESPState *s = req->hba_private;
294
295 trace_esp_command_complete();
296 if (s->ti_size != 0) {
297 trace_esp_command_complete_unexpected();
298 }
299 s->ti_size = 0;
300 s->dma_left = 0;
301 s->async_len = 0;
302 if (status) {
303 trace_esp_command_complete_fail();
304 }
305 s->status = status;
306 s->rregs[ESP_RSTAT] = STAT_ST;
307 esp_dma_done(s);
308 if (s->current_req) {
309 scsi_req_unref(s->current_req);
310 s->current_req = NULL;
311 s->current_dev = NULL;
312 }
313}
314
315void esp_transfer_data(SCSIRequest *req, uint32_t len)
316{
317 ESPState *s = req->hba_private;
318
319 assert(!s->do_cmd);
320 trace_esp_transfer_data(s->dma_left, s->ti_size);
321 s->async_len = len;
322 s->async_buf = scsi_req_get_buf(req);
323 if (s->dma_left) {
324 esp_do_dma(s);
325 } else if (s->dma_counter != 0 && s->ti_size <= 0) {
326
327
328 esp_dma_done(s);
329 }
330}
331
332static void handle_ti(ESPState *s)
333{
334 uint32_t dmalen, minlen;
335
336 if (s->dma && !s->dma_enabled) {
337 s->dma_cb = handle_ti;
338 return;
339 }
340
341 dmalen = s->rregs[ESP_TCLO];
342 dmalen |= s->rregs[ESP_TCMID] << 8;
343 dmalen |= s->rregs[ESP_TCHI] << 16;
344 if (dmalen==0) {
345 dmalen=0x10000;
346 }
347 s->dma_counter = dmalen;
348
349 if (s->do_cmd)
350 minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ;
351 else if (s->ti_size < 0)
352 minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
353 else
354 minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
355 trace_esp_handle_ti(minlen);
356 if (s->dma) {
357 s->dma_left = minlen;
358 s->rregs[ESP_RSTAT] &= ~STAT_TC;
359 esp_do_dma(s);
360 }
361 if (s->do_cmd) {
362 trace_esp_handle_ti_cmd(s->cmdlen);
363 s->ti_size = 0;
364 s->cmdlen = 0;
365 s->do_cmd = 0;
366 do_cmd(s, s->cmdbuf);
367 }
368}
369
370void esp_hard_reset(ESPState *s)
371{
372 memset(s->rregs, 0, ESP_REGS);
373 memset(s->wregs, 0, ESP_REGS);
374 s->tchi_written = 0;
375 s->ti_size = 0;
376 s->ti_rptr = 0;
377 s->ti_wptr = 0;
378 s->dma = 0;
379 s->do_cmd = 0;
380 s->dma_cb = NULL;
381
382 s->rregs[ESP_CFG1] = 7;
383}
384
385static void esp_soft_reset(ESPState *s)
386{
387 qemu_irq_lower(s->irq);
388 esp_hard_reset(s);
389}
390
391static void parent_esp_reset(ESPState *s, int irq, int level)
392{
393 if (level) {
394 esp_soft_reset(s);
395 }
396}
397
398uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
399{
400 uint32_t old_val;
401
402 trace_esp_mem_readb(saddr, s->rregs[saddr]);
403 switch (saddr) {
404 case ESP_FIFO:
405 if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
406
407 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n");
408 s->rregs[ESP_FIFO] = 0;
409 esp_raise_irq(s);
410 } else if (s->ti_rptr < s->ti_wptr) {
411 s->ti_size--;
412 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
413 esp_raise_irq(s);
414 }
415 if (s->ti_rptr == s->ti_wptr) {
416 s->ti_rptr = 0;
417 s->ti_wptr = 0;
418 }
419 break;
420 case ESP_RINTR:
421
422
423 old_val = s->rregs[ESP_RINTR];
424 s->rregs[ESP_RINTR] = 0;
425 s->rregs[ESP_RSTAT] &= ~STAT_TC;
426 s->rregs[ESP_RSEQ] = SEQ_CD;
427 esp_lower_irq(s);
428
429 return old_val;
430 case ESP_TCHI:
431
432 if (!s->tchi_written) {
433 return s->chip_id;
434 }
435 default:
436 break;
437 }
438 return s->rregs[saddr];
439}
440
441void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
442{
443 trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
444 switch (saddr) {
445 case ESP_TCHI:
446 s->tchi_written = true;
447
448 case ESP_TCLO:
449 case ESP_TCMID:
450 s->rregs[ESP_RSTAT] &= ~STAT_TC;
451 break;
452 case ESP_FIFO:
453 if (s->do_cmd) {
454 if (s->cmdlen < ESP_CMDBUF_SZ) {
455 s->cmdbuf[s->cmdlen++] = val & 0xff;
456 } else {
457 trace_esp_error_fifo_overrun();
458 }
459 } else if (s->ti_wptr == TI_BUFSZ - 1) {
460 trace_esp_error_fifo_overrun();
461 } else {
462 s->ti_size++;
463 s->ti_buf[s->ti_wptr++] = val & 0xff;
464 }
465 break;
466 case ESP_CMD:
467 s->rregs[saddr] = val;
468 if (val & CMD_DMA) {
469 s->dma = 1;
470
471 s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
472 s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
473 s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI];
474 } else {
475 s->dma = 0;
476 }
477 switch(val & CMD_CMD) {
478 case CMD_NOP:
479 trace_esp_mem_writeb_cmd_nop(val);
480 break;
481 case CMD_FLUSH:
482 trace_esp_mem_writeb_cmd_flush(val);
483
484 s->rregs[ESP_RINTR] = INTR_FC;
485 s->rregs[ESP_RSEQ] = 0;
486 s->rregs[ESP_RFLAGS] = 0;
487 break;
488 case CMD_RESET:
489 trace_esp_mem_writeb_cmd_reset(val);
490 esp_soft_reset(s);
491 break;
492 case CMD_BUSRESET:
493 trace_esp_mem_writeb_cmd_bus_reset(val);
494 s->rregs[ESP_RINTR] = INTR_RST;
495 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
496 esp_raise_irq(s);
497 }
498 break;
499 case CMD_TI:
500 handle_ti(s);
501 break;
502 case CMD_ICCS:
503 trace_esp_mem_writeb_cmd_iccs(val);
504 write_response(s);
505 s->rregs[ESP_RINTR] = INTR_FC;
506 s->rregs[ESP_RSTAT] |= STAT_MI;
507 break;
508 case CMD_MSGACC:
509 trace_esp_mem_writeb_cmd_msgacc(val);
510 s->rregs[ESP_RINTR] = INTR_DC;
511 s->rregs[ESP_RSEQ] = 0;
512 s->rregs[ESP_RFLAGS] = 0;
513 esp_raise_irq(s);
514 break;
515 case CMD_PAD:
516 trace_esp_mem_writeb_cmd_pad(val);
517 s->rregs[ESP_RSTAT] = STAT_TC;
518 s->rregs[ESP_RINTR] = INTR_FC;
519 s->rregs[ESP_RSEQ] = 0;
520 break;
521 case CMD_SATN:
522 trace_esp_mem_writeb_cmd_satn(val);
523 break;
524 case CMD_RSTATN:
525 trace_esp_mem_writeb_cmd_rstatn(val);
526 break;
527 case CMD_SEL:
528 trace_esp_mem_writeb_cmd_sel(val);
529 handle_s_without_atn(s);
530 break;
531 case CMD_SELATN:
532 trace_esp_mem_writeb_cmd_selatn(val);
533 handle_satn(s);
534 break;
535 case CMD_SELATNS:
536 trace_esp_mem_writeb_cmd_selatns(val);
537 handle_satn_stop(s);
538 break;
539 case CMD_ENSEL:
540 trace_esp_mem_writeb_cmd_ensel(val);
541 s->rregs[ESP_RINTR] = 0;
542 break;
543 case CMD_DISSEL:
544 trace_esp_mem_writeb_cmd_dissel(val);
545 s->rregs[ESP_RINTR] = 0;
546 esp_raise_irq(s);
547 break;
548 default:
549 trace_esp_error_unhandled_command(val);
550 break;
551 }
552 break;
553 case ESP_WBUSID ... ESP_WSYNO:
554 break;
555 case ESP_CFG1:
556 case ESP_CFG2: case ESP_CFG3:
557 case ESP_RES3: case ESP_RES4:
558 s->rregs[saddr] = val;
559 break;
560 case ESP_WCCF ... ESP_WTEST:
561 break;
562 default:
563 trace_esp_error_invalid_write(val, saddr);
564 return;
565 }
566 s->wregs[saddr] = val;
567}
568
569static bool esp_mem_accepts(void *opaque, hwaddr addr,
570 unsigned size, bool is_write)
571{
572 return (size == 1) || (is_write && size == 4);
573}
574
575const VMStateDescription vmstate_esp = {
576 .name ="esp",
577 .version_id = 3,
578 .minimum_version_id = 3,
579 .fields = (VMStateField[]) {
580 VMSTATE_BUFFER(rregs, ESPState),
581 VMSTATE_BUFFER(wregs, ESPState),
582 VMSTATE_INT32(ti_size, ESPState),
583 VMSTATE_UINT32(ti_rptr, ESPState),
584 VMSTATE_UINT32(ti_wptr, ESPState),
585 VMSTATE_BUFFER(ti_buf, ESPState),
586 VMSTATE_UINT32(status, ESPState),
587 VMSTATE_UINT32(dma, ESPState),
588 VMSTATE_BUFFER(cmdbuf, ESPState),
589 VMSTATE_UINT32(cmdlen, ESPState),
590 VMSTATE_UINT32(do_cmd, ESPState),
591 VMSTATE_UINT32(dma_left, ESPState),
592 VMSTATE_END_OF_LIST()
593 }
594};
595
596#define TYPE_ESP "esp"
597#define ESP(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP)
598
599typedef struct {
600
601 SysBusDevice parent_obj;
602
603
604 MemoryRegion iomem;
605 uint32_t it_shift;
606 ESPState esp;
607} SysBusESPState;
608
609static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
610 uint64_t val, unsigned int size)
611{
612 SysBusESPState *sysbus = opaque;
613 uint32_t saddr;
614
615 saddr = addr >> sysbus->it_shift;
616 esp_reg_write(&sysbus->esp, saddr, val);
617}
618
619static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
620 unsigned int size)
621{
622 SysBusESPState *sysbus = opaque;
623 uint32_t saddr;
624
625 saddr = addr >> sysbus->it_shift;
626 return esp_reg_read(&sysbus->esp, saddr);
627}
628
629static const MemoryRegionOps sysbus_esp_mem_ops = {
630 .read = sysbus_esp_mem_read,
631 .write = sysbus_esp_mem_write,
632 .endianness = DEVICE_NATIVE_ENDIAN,
633 .valid.accepts = esp_mem_accepts,
634};
635
636void esp_init(hwaddr espaddr, int it_shift,
637 ESPDMAMemoryReadWriteFunc dma_memory_read,
638 ESPDMAMemoryReadWriteFunc dma_memory_write,
639 void *dma_opaque, qemu_irq irq, qemu_irq *reset,
640 qemu_irq *dma_enable)
641{
642 DeviceState *dev;
643 SysBusDevice *s;
644 SysBusESPState *sysbus;
645 ESPState *esp;
646
647 dev = qdev_create(NULL, TYPE_ESP);
648 sysbus = ESP(dev);
649 esp = &sysbus->esp;
650 esp->dma_memory_read = dma_memory_read;
651 esp->dma_memory_write = dma_memory_write;
652 esp->dma_opaque = dma_opaque;
653 sysbus->it_shift = it_shift;
654
655 esp->dma_enabled = 1;
656 qdev_init_nofail(dev);
657 s = SYS_BUS_DEVICE(dev);
658 sysbus_connect_irq(s, 0, irq);
659 sysbus_mmio_map(s, 0, espaddr);
660 *reset = qdev_get_gpio_in(dev, 0);
661 *dma_enable = qdev_get_gpio_in(dev, 1);
662}
663
664static const struct SCSIBusInfo esp_scsi_info = {
665 .tcq = false,
666 .max_target = ESP_MAX_DEVS,
667 .max_lun = 7,
668
669 .transfer_data = esp_transfer_data,
670 .complete = esp_command_complete,
671 .cancel = esp_request_cancelled
672};
673
674static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
675{
676 SysBusESPState *sysbus = ESP(opaque);
677 ESPState *s = &sysbus->esp;
678
679 switch (irq) {
680 case 0:
681 parent_esp_reset(s, irq, level);
682 break;
683 case 1:
684 esp_dma_enable(opaque, irq, level);
685 break;
686 }
687}
688
689static void sysbus_esp_realize(DeviceState *dev, Error **errp)
690{
691 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
692 SysBusESPState *sysbus = ESP(dev);
693 ESPState *s = &sysbus->esp;
694 Error *err = NULL;
695
696 sysbus_init_irq(sbd, &s->irq);
697 assert(sysbus->it_shift != -1);
698
699 s->chip_id = TCHI_FAS100A;
700 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
701 sysbus, "esp", ESP_REGS << sysbus->it_shift);
702 sysbus_init_mmio(sbd, &sysbus->iomem);
703
704 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
705
706 scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
707 scsi_bus_legacy_handle_cmdline(&s->bus, &err);
708 if (err != NULL) {
709 error_propagate(errp, err);
710 return;
711 }
712}
713
714static void sysbus_esp_hard_reset(DeviceState *dev)
715{
716 SysBusESPState *sysbus = ESP(dev);
717 esp_hard_reset(&sysbus->esp);
718}
719
720static const VMStateDescription vmstate_sysbus_esp_scsi = {
721 .name = "sysbusespscsi",
722 .version_id = 0,
723 .minimum_version_id = 0,
724 .fields = (VMStateField[]) {
725 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
726 VMSTATE_END_OF_LIST()
727 }
728};
729
730static void sysbus_esp_class_init(ObjectClass *klass, void *data)
731{
732 DeviceClass *dc = DEVICE_CLASS(klass);
733
734 dc->realize = sysbus_esp_realize;
735 dc->reset = sysbus_esp_hard_reset;
736 dc->vmsd = &vmstate_sysbus_esp_scsi;
737 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
738}
739
740static const TypeInfo sysbus_esp_info = {
741 .name = TYPE_ESP,
742 .parent = TYPE_SYS_BUS_DEVICE,
743 .instance_size = sizeof(SysBusESPState),
744 .class_init = sysbus_esp_class_init,
745};
746
747static void esp_register_types(void)
748{
749 type_register_static(&sysbus_esp_info);
750}
751
752type_init(esp_register_types)
753
