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18#include "qemu/osdep.h"
19#include "hw/sysbus.h"
20#include "sysemu/sysemu.h"
21#include "hw/timer/allwinner-a10-pit.h"
22
23static void a10_pit_update_irq(AwA10PITState *s)
24{
25 int i;
26
27 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
28 qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i)));
29 }
30}
31
32static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
33{
34 AwA10PITState *s = AW_A10_PIT(opaque);
35 uint8_t index;
36
37 switch (offset) {
38 case AW_A10_PIT_TIMER_IRQ_EN:
39 return s->irq_enable;
40 case AW_A10_PIT_TIMER_IRQ_ST:
41 return s->irq_status;
42 case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
43 index = offset & 0xf0;
44 index >>= 4;
45 index -= 1;
46 switch (offset & 0x0f) {
47 case AW_A10_PIT_TIMER_CONTROL:
48 return s->control[index];
49 case AW_A10_PIT_TIMER_INTERVAL:
50 return s->interval[index];
51 case AW_A10_PIT_TIMER_COUNT:
52 s->count[index] = ptimer_get_count(s->timer[index]);
53 return s->count[index];
54 default:
55 qemu_log_mask(LOG_GUEST_ERROR,
56 "%s: Bad offset 0x%x\n", __func__, (int)offset);
57 break;
58 }
59 case AW_A10_PIT_WDOG_CONTROL:
60 break;
61 case AW_A10_PIT_WDOG_MODE:
62 break;
63 case AW_A10_PIT_COUNT_LO:
64 return s->count_lo;
65 case AW_A10_PIT_COUNT_HI:
66 return s->count_hi;
67 case AW_A10_PIT_COUNT_CTL:
68 return s->count_ctl;
69 default:
70 qemu_log_mask(LOG_GUEST_ERROR,
71 "%s: Bad offset 0x%x\n", __func__, (int)offset);
72 break;
73 }
74
75 return 0;
76}
77
78static void a10_pit_set_freq(AwA10PITState *s, int index)
79{
80 uint32_t prescaler, source, source_freq;
81
82 prescaler = 1 << extract32(s->control[index], 4, 3);
83 source = extract32(s->control[index], 2, 2);
84 source_freq = s->clk_freq[source];
85
86 if (source_freq) {
87 ptimer_set_freq(s->timer[index], source_freq / prescaler);
88 } else {
89 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n",
90 __func__, source);
91 }
92}
93
94static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
95 unsigned size)
96{
97 AwA10PITState *s = AW_A10_PIT(opaque);
98 uint8_t index;
99
100 switch (offset) {
101 case AW_A10_PIT_TIMER_IRQ_EN:
102 s->irq_enable = value;
103 a10_pit_update_irq(s);
104 break;
105 case AW_A10_PIT_TIMER_IRQ_ST:
106 s->irq_status &= ~value;
107 a10_pit_update_irq(s);
108 break;
109 case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
110 index = offset & 0xf0;
111 index >>= 4;
112 index -= 1;
113 switch (offset & 0x0f) {
114 case AW_A10_PIT_TIMER_CONTROL:
115 s->control[index] = value;
116 a10_pit_set_freq(s, index);
117 if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) {
118 ptimer_set_count(s->timer[index], s->interval[index]);
119 }
120 if (s->control[index] & AW_A10_PIT_TIMER_EN) {
121 int oneshot = 0;
122 if (s->control[index] & AW_A10_PIT_TIMER_MODE) {
123 oneshot = 1;
124 }
125 ptimer_run(s->timer[index], oneshot);
126 } else {
127 ptimer_stop(s->timer[index]);
128 }
129 break;
130 case AW_A10_PIT_TIMER_INTERVAL:
131 s->interval[index] = value;
132 ptimer_set_limit(s->timer[index], s->interval[index], 1);
133 break;
134 case AW_A10_PIT_TIMER_COUNT:
135 s->count[index] = value;
136 break;
137 default:
138 qemu_log_mask(LOG_GUEST_ERROR,
139 "%s: Bad offset 0x%x\n", __func__, (int)offset);
140 }
141 break;
142 case AW_A10_PIT_WDOG_CONTROL:
143 s->watch_dog_control = value;
144 break;
145 case AW_A10_PIT_WDOG_MODE:
146 s->watch_dog_mode = value;
147 break;
148 case AW_A10_PIT_COUNT_LO:
149 s->count_lo = value;
150 break;
151 case AW_A10_PIT_COUNT_HI:
152 s->count_hi = value;
153 break;
154 case AW_A10_PIT_COUNT_CTL:
155 s->count_ctl = value;
156 if (s->count_ctl & AW_A10_PIT_COUNT_RL_EN) {
157 uint64_t tmp_count = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
158
159 s->count_lo = tmp_count;
160 s->count_hi = tmp_count >> 32;
161 s->count_ctl &= ~AW_A10_PIT_COUNT_RL_EN;
162 }
163 if (s->count_ctl & AW_A10_PIT_COUNT_CLR_EN) {
164 s->count_lo = 0;
165 s->count_hi = 0;
166 s->count_ctl &= ~AW_A10_PIT_COUNT_CLR_EN;
167 }
168 break;
169 default:
170 qemu_log_mask(LOG_GUEST_ERROR,
171 "%s: Bad offset 0x%x\n", __func__, (int)offset);
172 break;
173 }
174}
175
176static const MemoryRegionOps a10_pit_ops = {
177 .read = a10_pit_read,
178 .write = a10_pit_write,
179 .endianness = DEVICE_NATIVE_ENDIAN,
180};
181
182static Property a10_pit_properties[] = {
183 DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0),
184 DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0),
185 DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0),
186 DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0),
187 DEFINE_PROP_END_OF_LIST(),
188};
189
190static const VMStateDescription vmstate_a10_pit = {
191 .name = "a10.pit",
192 .version_id = 1,
193 .minimum_version_id = 1,
194 .fields = (VMStateField[]) {
195 VMSTATE_UINT32(irq_enable, AwA10PITState),
196 VMSTATE_UINT32(irq_status, AwA10PITState),
197 VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR),
198 VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR),
199 VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR),
200 VMSTATE_UINT32(watch_dog_mode, AwA10PITState),
201 VMSTATE_UINT32(watch_dog_control, AwA10PITState),
202 VMSTATE_UINT32(count_lo, AwA10PITState),
203 VMSTATE_UINT32(count_hi, AwA10PITState),
204 VMSTATE_UINT32(count_ctl, AwA10PITState),
205 VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR),
206 VMSTATE_END_OF_LIST()
207 }
208};
209
210static void a10_pit_reset(DeviceState *dev)
211{
212 AwA10PITState *s = AW_A10_PIT(dev);
213 uint8_t i;
214
215 s->irq_enable = 0;
216 s->irq_status = 0;
217 a10_pit_update_irq(s);
218
219 for (i = 0; i < 6; i++) {
220 s->control[i] = AW_A10_PIT_DEFAULT_CLOCK;
221 s->interval[i] = 0;
222 s->count[i] = 0;
223 ptimer_stop(s->timer[i]);
224 a10_pit_set_freq(s, i);
225 }
226 s->watch_dog_mode = 0;
227 s->watch_dog_control = 0;
228 s->count_lo = 0;
229 s->count_hi = 0;
230 s->count_ctl = 0;
231}
232
233static void a10_pit_timer_cb(void *opaque)
234{
235 AwA10TimerContext *tc = opaque;
236 AwA10PITState *s = tc->container;
237 uint8_t i = tc->index;
238
239 if (s->control[i] & AW_A10_PIT_TIMER_EN) {
240 s->irq_status |= 1 << i;
241 if (s->control[i] & AW_A10_PIT_TIMER_MODE) {
242 ptimer_stop(s->timer[i]);
243 s->control[i] &= ~AW_A10_PIT_TIMER_EN;
244 }
245 a10_pit_update_irq(s);
246 }
247}
248
249static void a10_pit_init(Object *obj)
250{
251 AwA10PITState *s = AW_A10_PIT(obj);
252 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
253 QEMUBH * bh[AW_A10_PIT_TIMER_NR];
254 uint8_t i;
255
256 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
257 sysbus_init_irq(sbd, &s->irq[i]);
258 }
259 memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s,
260 TYPE_AW_A10_PIT, 0x400);
261 sysbus_init_mmio(sbd, &s->iomem);
262
263 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
264 AwA10TimerContext *tc = &s->timer_context[i];
265
266 tc->container = s;
267 tc->index = i;
268 bh[i] = qemu_bh_new(a10_pit_timer_cb, tc);
269 s->timer[i] = ptimer_init(bh[i]);
270 }
271}
272
273static void a10_pit_class_init(ObjectClass *klass, void *data)
274{
275 DeviceClass *dc = DEVICE_CLASS(klass);
276
277 dc->reset = a10_pit_reset;
278 dc->props = a10_pit_properties;
279 dc->desc = "allwinner a10 timer";
280 dc->vmsd = &vmstate_a10_pit;
281}
282
283static const TypeInfo a10_pit_info = {
284 .name = TYPE_AW_A10_PIT,
285 .parent = TYPE_SYS_BUS_DEVICE,
286 .instance_size = sizeof(AwA10PITState),
287 .instance_init = a10_pit_init,
288 .class_init = a10_pit_class_init,
289};
290
291static void a10_register_types(void)
292{
293 type_register_static(&a10_pit_info);
294}
295
296type_init(a10_register_types);
297
