qemu/hw/timer/cadence_ttc.c
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   1/*
   2 * Xilinx Zynq cadence TTC model
   3 *
   4 * Copyright (c) 2011 Xilinx Inc.
   5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
   6 * Copyright (c) 2012 PetaLogix Pty Ltd.
   7 * Written By Haibing Ma
   8 *            M. Habib
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License
  12 * as published by the Free Software Foundation; either version
  13 * 2 of the License, or (at your option) any later version.
  14 *
  15 * You should have received a copy of the GNU General Public License along
  16 * with this program; if not, see <http://www.gnu.org/licenses/>.
  17 */
  18
  19#include "qemu/osdep.h"
  20#include "hw/sysbus.h"
  21#include "qemu/timer.h"
  22
  23#ifdef CADENCE_TTC_ERR_DEBUG
  24#define DB_PRINT(...) do { \
  25    fprintf(stderr,  ": %s: ", __func__); \
  26    fprintf(stderr, ## __VA_ARGS__); \
  27    } while (0);
  28#else
  29    #define DB_PRINT(...)
  30#endif
  31
  32#define COUNTER_INTR_IV     0x00000001
  33#define COUNTER_INTR_M1     0x00000002
  34#define COUNTER_INTR_M2     0x00000004
  35#define COUNTER_INTR_M3     0x00000008
  36#define COUNTER_INTR_OV     0x00000010
  37#define COUNTER_INTR_EV     0x00000020
  38
  39#define COUNTER_CTRL_DIS    0x00000001
  40#define COUNTER_CTRL_INT    0x00000002
  41#define COUNTER_CTRL_DEC    0x00000004
  42#define COUNTER_CTRL_MATCH  0x00000008
  43#define COUNTER_CTRL_RST    0x00000010
  44
  45#define CLOCK_CTRL_PS_EN    0x00000001
  46#define CLOCK_CTRL_PS_V     0x0000001e
  47
  48typedef struct {
  49    QEMUTimer *timer;
  50    int freq;
  51
  52    uint32_t reg_clock;
  53    uint32_t reg_count;
  54    uint32_t reg_value;
  55    uint16_t reg_interval;
  56    uint16_t reg_match[3];
  57    uint32_t reg_intr;
  58    uint32_t reg_intr_en;
  59    uint32_t reg_event_ctrl;
  60    uint32_t reg_event;
  61
  62    uint64_t cpu_time;
  63    unsigned int cpu_time_valid;
  64
  65    qemu_irq irq;
  66} CadenceTimerState;
  67
  68#define TYPE_CADENCE_TTC "cadence_ttc"
  69#define CADENCE_TTC(obj) \
  70    OBJECT_CHECK(CadenceTTCState, (obj), TYPE_CADENCE_TTC)
  71
  72typedef struct CadenceTTCState {
  73    SysBusDevice parent_obj;
  74
  75    MemoryRegion iomem;
  76    CadenceTimerState timer[3];
  77} CadenceTTCState;
  78
  79static void cadence_timer_update(CadenceTimerState *s)
  80{
  81    qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
  82}
  83
  84static CadenceTimerState *cadence_timer_from_addr(void *opaque,
  85                                        hwaddr offset)
  86{
  87    unsigned int index;
  88    CadenceTTCState *s = (CadenceTTCState *)opaque;
  89
  90    index = (offset >> 2) % 3;
  91
  92    return &s->timer[index];
  93}
  94
  95static uint64_t cadence_timer_get_ns(CadenceTimerState *s, uint64_t timer_steps)
  96{
  97    /* timer_steps has max value of 0x100000000. double check it
  98     * (or overflow can happen below) */
  99    assert(timer_steps <= 1ULL << 32);
 100
 101    uint64_t r = timer_steps * 1000000000ULL;
 102    if (s->reg_clock & CLOCK_CTRL_PS_EN) {
 103        r >>= 16 - (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1);
 104    } else {
 105        r >>= 16;
 106    }
 107    r /= (uint64_t)s->freq;
 108    return r;
 109}
 110
 111static uint64_t cadence_timer_get_steps(CadenceTimerState *s, uint64_t ns)
 112{
 113    uint64_t to_divide = 1000000000ULL;
 114
 115    uint64_t r = ns;
 116     /* for very large intervals (> 8s) do some division first to stop
 117      * overflow (costs some prescision) */
 118    while (r >= 8ULL << 30 && to_divide > 1) {
 119        r /= 1000;
 120        to_divide /= 1000;
 121    }
 122    r <<= 16;
 123    /* keep early-dividing as needed */
 124    while (r >= 8ULL << 30 && to_divide > 1) {
 125        r /= 1000;
 126        to_divide /= 1000;
 127    }
 128    r *= (uint64_t)s->freq;
 129    if (s->reg_clock & CLOCK_CTRL_PS_EN) {
 130        r /= 1 << (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1);
 131    }
 132
 133    r /= to_divide;
 134    return r;
 135}
 136
 137/* determine if x is in between a and b, exclusive of a, inclusive of b */
 138
 139static inline int64_t is_between(int64_t x, int64_t a, int64_t b)
 140{
 141    if (a < b) {
 142        return x > a && x <= b;
 143    }
 144    return x < a && x >= b;
 145}
 146
 147static void cadence_timer_run(CadenceTimerState *s)
 148{
 149    int i;
 150    int64_t event_interval, next_value;
 151
 152    assert(s->cpu_time_valid); /* cadence_timer_sync must be called first */
 153
 154    if (s->reg_count & COUNTER_CTRL_DIS) {
 155        s->cpu_time_valid = 0;
 156        return;
 157    }
 158
 159    { /* figure out what's going to happen next (rollover or match) */
 160        int64_t interval = (uint64_t)((s->reg_count & COUNTER_CTRL_INT) ?
 161                (int64_t)s->reg_interval + 1 : 0x10000ULL) << 16;
 162        next_value = (s->reg_count & COUNTER_CTRL_DEC) ? -1ULL : interval;
 163        for (i = 0; i < 3; ++i) {
 164            int64_t cand = (uint64_t)s->reg_match[i] << 16;
 165            if (is_between(cand, (uint64_t)s->reg_value, next_value)) {
 166                next_value = cand;
 167            }
 168        }
 169    }
 170    DB_PRINT("next timer event value: %09llx\n",
 171            (unsigned long long)next_value);
 172
 173    event_interval = next_value - (int64_t)s->reg_value;
 174    event_interval = (event_interval < 0) ? -event_interval : event_interval;
 175
 176    timer_mod(s->timer, s->cpu_time +
 177                cadence_timer_get_ns(s, event_interval));
 178}
 179
 180static void cadence_timer_sync(CadenceTimerState *s)
 181{
 182    int i;
 183    int64_t r, x;
 184    int64_t interval = ((s->reg_count & COUNTER_CTRL_INT) ?
 185            (int64_t)s->reg_interval + 1 : 0x10000ULL) << 16;
 186    uint64_t old_time = s->cpu_time;
 187
 188    s->cpu_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 189    DB_PRINT("cpu time: %lld ns\n", (long long)old_time);
 190
 191    if (!s->cpu_time_valid || old_time == s->cpu_time) {
 192        s->cpu_time_valid = 1;
 193        return;
 194    }
 195
 196    r = (int64_t)cadence_timer_get_steps(s, s->cpu_time - old_time);
 197    x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r);
 198
 199    for (i = 0; i < 3; ++i) {
 200        int64_t m = (int64_t)s->reg_match[i] << 16;
 201        if (m > interval) {
 202            continue;
 203        }
 204        /* check to see if match event has occurred. check m +/- interval
 205         * to account for match events in wrap around cases */
 206        if (is_between(m, s->reg_value, x) ||
 207            is_between(m + interval, s->reg_value, x) ||
 208            is_between(m - interval, s->reg_value, x)) {
 209            s->reg_intr |= (2 << i);
 210        }
 211    }
 212    if ((x < 0) || (x >= interval)) {
 213        s->reg_intr |= (s->reg_count & COUNTER_CTRL_INT) ?
 214            COUNTER_INTR_IV : COUNTER_INTR_OV;
 215    }
 216    while (x < 0) {
 217        x += interval;
 218    }
 219    s->reg_value = (uint32_t)(x % interval);
 220    cadence_timer_update(s);
 221}
 222
 223static void cadence_timer_tick(void *opaque)
 224{
 225    CadenceTimerState *s = opaque;
 226
 227    DB_PRINT("\n");
 228    cadence_timer_sync(s);
 229    cadence_timer_run(s);
 230}
 231
 232static uint32_t cadence_ttc_read_imp(void *opaque, hwaddr offset)
 233{
 234    CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
 235    uint32_t value;
 236
 237    cadence_timer_sync(s);
 238    cadence_timer_run(s);
 239
 240    switch (offset) {
 241    case 0x00: /* clock control */
 242    case 0x04:
 243    case 0x08:
 244        return s->reg_clock;
 245
 246    case 0x0c: /* counter control */
 247    case 0x10:
 248    case 0x14:
 249        return s->reg_count;
 250
 251    case 0x18: /* counter value */
 252    case 0x1c:
 253    case 0x20:
 254        return (uint16_t)(s->reg_value >> 16);
 255
 256    case 0x24: /* reg_interval counter */
 257    case 0x28:
 258    case 0x2c:
 259        return s->reg_interval;
 260
 261    case 0x30: /* match 1 counter */
 262    case 0x34:
 263    case 0x38:
 264        return s->reg_match[0];
 265
 266    case 0x3c: /* match 2 counter */
 267    case 0x40:
 268    case 0x44:
 269        return s->reg_match[1];
 270
 271    case 0x48: /* match 3 counter */
 272    case 0x4c:
 273    case 0x50:
 274        return s->reg_match[2];
 275
 276    case 0x54: /* interrupt register */
 277    case 0x58:
 278    case 0x5c:
 279        /* cleared after read */
 280        value = s->reg_intr;
 281        s->reg_intr = 0;
 282        cadence_timer_update(s);
 283        return value;
 284
 285    case 0x60: /* interrupt enable */
 286    case 0x64:
 287    case 0x68:
 288        return s->reg_intr_en;
 289
 290    case 0x6c:
 291    case 0x70:
 292    case 0x74:
 293        return s->reg_event_ctrl;
 294
 295    case 0x78:
 296    case 0x7c:
 297    case 0x80:
 298        return s->reg_event;
 299
 300    default:
 301        return 0;
 302    }
 303}
 304
 305static uint64_t cadence_ttc_read(void *opaque, hwaddr offset,
 306    unsigned size)
 307{
 308    uint32_t ret = cadence_ttc_read_imp(opaque, offset);
 309
 310    DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)ret);
 311    return ret;
 312}
 313
 314static void cadence_ttc_write(void *opaque, hwaddr offset,
 315        uint64_t value, unsigned size)
 316{
 317    CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
 318
 319    DB_PRINT("addr: %08x data %08x\n", (unsigned)offset, (unsigned)value);
 320
 321    cadence_timer_sync(s);
 322
 323    switch (offset) {
 324    case 0x00: /* clock control */
 325    case 0x04:
 326    case 0x08:
 327        s->reg_clock = value & 0x3F;
 328        break;
 329
 330    case 0x0c: /* counter control */
 331    case 0x10:
 332    case 0x14:
 333        if (value & COUNTER_CTRL_RST) {
 334            s->reg_value = 0;
 335        }
 336        s->reg_count = value & 0x3f & ~COUNTER_CTRL_RST;
 337        break;
 338
 339    case 0x24: /* interval register */
 340    case 0x28:
 341    case 0x2c:
 342        s->reg_interval = value & 0xffff;
 343        break;
 344
 345    case 0x30: /* match register */
 346    case 0x34:
 347    case 0x38:
 348        s->reg_match[0] = value & 0xffff;
 349        break;
 350
 351    case 0x3c: /* match register */
 352    case 0x40:
 353    case 0x44:
 354        s->reg_match[1] = value & 0xffff;
 355        break;
 356
 357    case 0x48: /* match register */
 358    case 0x4c:
 359    case 0x50:
 360        s->reg_match[2] = value & 0xffff;
 361        break;
 362
 363    case 0x54: /* interrupt register */
 364    case 0x58:
 365    case 0x5c:
 366        break;
 367
 368    case 0x60: /* interrupt enable */
 369    case 0x64:
 370    case 0x68:
 371        s->reg_intr_en = value & 0x3f;
 372        break;
 373
 374    case 0x6c: /* event control */
 375    case 0x70:
 376    case 0x74:
 377        s->reg_event_ctrl = value & 0x07;
 378        break;
 379
 380    default:
 381        return;
 382    }
 383
 384    cadence_timer_run(s);
 385    cadence_timer_update(s);
 386}
 387
 388static const MemoryRegionOps cadence_ttc_ops = {
 389    .read = cadence_ttc_read,
 390    .write = cadence_ttc_write,
 391    .endianness = DEVICE_NATIVE_ENDIAN,
 392};
 393
 394static void cadence_timer_reset(CadenceTimerState *s)
 395{
 396   s->reg_count = 0x21;
 397}
 398
 399static void cadence_timer_init(uint32_t freq, CadenceTimerState *s)
 400{
 401    memset(s, 0, sizeof(CadenceTimerState));
 402    s->freq = freq;
 403
 404    cadence_timer_reset(s);
 405
 406    s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cadence_timer_tick, s);
 407}
 408
 409static void cadence_ttc_init(Object *obj)
 410{
 411    CadenceTTCState *s = CADENCE_TTC(obj);
 412    int i;
 413
 414    for (i = 0; i < 3; ++i) {
 415        cadence_timer_init(133000000, &s->timer[i]);
 416        sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->timer[i].irq);
 417    }
 418
 419    memory_region_init_io(&s->iomem, obj, &cadence_ttc_ops, s,
 420                          "timer", 0x1000);
 421    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 422}
 423
 424static void cadence_timer_pre_save(void *opaque)
 425{
 426    cadence_timer_sync((CadenceTimerState *)opaque);
 427}
 428
 429static int cadence_timer_post_load(void *opaque, int version_id)
 430{
 431    CadenceTimerState *s = opaque;
 432
 433    s->cpu_time_valid = 0;
 434    cadence_timer_sync(s);
 435    cadence_timer_run(s);
 436    cadence_timer_update(s);
 437    return 0;
 438}
 439
 440static const VMStateDescription vmstate_cadence_timer = {
 441    .name = "cadence_timer",
 442    .version_id = 1,
 443    .minimum_version_id = 1,
 444    .pre_save = cadence_timer_pre_save,
 445    .post_load = cadence_timer_post_load,
 446    .fields = (VMStateField[]) {
 447        VMSTATE_UINT32(reg_clock, CadenceTimerState),
 448        VMSTATE_UINT32(reg_count, CadenceTimerState),
 449        VMSTATE_UINT32(reg_value, CadenceTimerState),
 450        VMSTATE_UINT16(reg_interval, CadenceTimerState),
 451        VMSTATE_UINT16_ARRAY(reg_match, CadenceTimerState, 3),
 452        VMSTATE_UINT32(reg_intr, CadenceTimerState),
 453        VMSTATE_UINT32(reg_intr_en, CadenceTimerState),
 454        VMSTATE_UINT32(reg_event_ctrl, CadenceTimerState),
 455        VMSTATE_UINT32(reg_event, CadenceTimerState),
 456        VMSTATE_END_OF_LIST()
 457    }
 458};
 459
 460static const VMStateDescription vmstate_cadence_ttc = {
 461    .name = "cadence_TTC",
 462    .version_id = 1,
 463    .minimum_version_id = 1,
 464    .fields = (VMStateField[]) {
 465        VMSTATE_STRUCT_ARRAY(timer, CadenceTTCState, 3, 0,
 466                            vmstate_cadence_timer,
 467                            CadenceTimerState),
 468        VMSTATE_END_OF_LIST()
 469    }
 470};
 471
 472static void cadence_ttc_class_init(ObjectClass *klass, void *data)
 473{
 474    DeviceClass *dc = DEVICE_CLASS(klass);
 475
 476    dc->vmsd = &vmstate_cadence_ttc;
 477}
 478
 479static const TypeInfo cadence_ttc_info = {
 480    .name  = TYPE_CADENCE_TTC,
 481    .parent = TYPE_SYS_BUS_DEVICE,
 482    .instance_size  = sizeof(CadenceTTCState),
 483    .instance_init = cadence_ttc_init,
 484    .class_init = cadence_ttc_class_init,
 485};
 486
 487static void cadence_ttc_register_types(void)
 488{
 489    type_register_static(&cadence_ttc_info);
 490}
 491
 492type_init(cadence_ttc_register_types)
 493