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20#ifndef QEMU_ARM_CPU_QOM_H
21#define QEMU_ARM_CPU_QOM_H
22
23#include "qom/cpu.h"
24
25#define TYPE_ARM_CPU "arm-cpu"
26
27#define ARM_CPU_CLASS(klass) \
28 OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
29#define ARM_CPU(obj) \
30 OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
31#define ARM_CPU_GET_CLASS(obj) \
32 OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
33
34
35
36
37
38
39
40
41typedef struct ARMCPUClass {
42
43 CPUClass parent_class;
44
45
46 DeviceRealize parent_realize;
47 void (*parent_reset)(CPUState *cpu);
48} ARMCPUClass;
49
50
51
52
53
54
55
56typedef struct ARMCPU {
57
58 CPUState parent_obj;
59
60
61 CPUARMState env;
62
63
64 GHashTable *cp_regs;
65
66
67
68
69
70
71
72 uint64_t *cpreg_indexes;
73
74 uint64_t *cpreg_values;
75
76 int32_t cpreg_array_len;
77
78
79
80
81 uint64_t *cpreg_vmstate_indexes;
82 uint64_t *cpreg_vmstate_values;
83 int32_t cpreg_vmstate_array_len;
84
85
86 QEMUTimer *gt_timer[NUM_GTIMERS];
87
88 qemu_irq gt_timer_outputs[NUM_GTIMERS];
89
90
91 MemoryRegion *secure_memory;
92
93
94 const char *dtb_compatible;
95
96
97
98
99
100 uint32_t psci_version;
101
102
103 bool start_powered_off;
104
105 bool powered_off;
106
107 bool has_el3;
108
109
110 bool has_mpu;
111
112 uint32_t pmsav7_dregion;
113
114
115
116
117 uint32_t psci_conduit;
118
119
120
121
122 uint32_t kvm_target;
123
124
125 uint32_t kvm_init_features[7];
126
127
128 bool mp_is_up;
129
130
131
132
133
134
135
136
137
138
139
140 uint32_t midr;
141 uint32_t revidr;
142 uint32_t reset_fpsid;
143 uint32_t mvfr0;
144 uint32_t mvfr1;
145 uint32_t mvfr2;
146 uint32_t ctr;
147 uint32_t reset_sctlr;
148 uint32_t id_pfr0;
149 uint32_t id_pfr1;
150 uint32_t id_dfr0;
151 uint32_t pmceid0;
152 uint32_t pmceid1;
153 uint32_t id_afr0;
154 uint32_t id_mmfr0;
155 uint32_t id_mmfr1;
156 uint32_t id_mmfr2;
157 uint32_t id_mmfr3;
158 uint32_t id_mmfr4;
159 uint32_t id_isar0;
160 uint32_t id_isar1;
161 uint32_t id_isar2;
162 uint32_t id_isar3;
163 uint32_t id_isar4;
164 uint32_t id_isar5;
165 uint64_t id_aa64pfr0;
166 uint64_t id_aa64pfr1;
167 uint64_t id_aa64dfr0;
168 uint64_t id_aa64dfr1;
169 uint64_t id_aa64afr0;
170 uint64_t id_aa64afr1;
171 uint64_t id_aa64isar0;
172 uint64_t id_aa64isar1;
173 uint64_t id_aa64mmfr0;
174 uint64_t id_aa64mmfr1;
175 uint32_t dbgdidr;
176 uint32_t clidr;
177 uint64_t mp_affinity;
178
179
180
181 uint32_t ccsidr[16];
182 uint64_t reset_cbar;
183 uint32_t reset_auxcr;
184 bool reset_hivecs;
185
186 uint32_t dcz_blocksize;
187 uint64_t rvbar;
188} ARMCPU;
189
190#define TYPE_AARCH64_CPU "aarch64-cpu"
191#define AARCH64_CPU_CLASS(klass) \
192 OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
193#define AARCH64_CPU_GET_CLASS(obj) \
194 OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU)
195
196typedef struct AArch64CPUClass {
197
198 ARMCPUClass parent_class;
199
200} AArch64CPUClass;
201
202static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
203{
204 return container_of(env, ARMCPU, env);
205}
206
207#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
208
209#define ENV_OFFSET offsetof(ARMCPU, env)
210
211#ifndef CONFIG_USER_ONLY
212extern const struct VMStateDescription vmstate_arm_cpu;
213#endif
214
215void register_cp_regs_for_features(ARMCPU *cpu);
216void init_cpreg_list(ARMCPU *cpu);
217
218void arm_cpu_do_interrupt(CPUState *cpu);
219void arm_v7m_cpu_do_interrupt(CPUState *cpu);
220bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
221
222void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
223 int flags);
224
225hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
226 MemTxAttrs *attrs);
227
228int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
229int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
230
231int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
232 int cpuid, void *opaque);
233int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
234 int cpuid, void *opaque);
235
236
237void arm_gt_ptimer_cb(void *opaque);
238void arm_gt_vtimer_cb(void *opaque);
239void arm_gt_htimer_cb(void *opaque);
240void arm_gt_stimer_cb(void *opaque);
241
242#define ARM_AFF0_SHIFT 0
243#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
244#define ARM_AFF1_SHIFT 8
245#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
246#define ARM_AFF2_SHIFT 16
247#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
248#define ARM_AFF3_SHIFT 32
249#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
250
251#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
252#define ARM64_AFFINITY_MASK \
253 (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
254
255#ifdef TARGET_AARCH64
256int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
257int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
258#endif
259
260#endif
261