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19#ifndef CPU_ARM_H
20#define CPU_ARM_H
21
22
23#include "kvm-consts.h"
24
25#if defined(TARGET_AARCH64)
26
27# define TARGET_LONG_BITS 64
28#else
29# define TARGET_LONG_BITS 32
30#endif
31
32#define TARGET_IS_BIENDIAN 1
33
34#define CPUArchState struct CPUARMState
35
36#include "qemu-common.h"
37#include "exec/cpu-defs.h"
38
39#include "fpu/softfloat.h"
40
41#define EXCP_UDEF 1
42#define EXCP_SWI 2
43#define EXCP_PREFETCH_ABORT 3
44#define EXCP_DATA_ABORT 4
45#define EXCP_IRQ 5
46#define EXCP_FIQ 6
47#define EXCP_BKPT 7
48#define EXCP_EXCEPTION_EXIT 8
49#define EXCP_KERNEL_TRAP 9
50#define EXCP_STREX 10
51#define EXCP_HVC 11
52#define EXCP_HYP_TRAP 12
53#define EXCP_SMC 13
54#define EXCP_VIRQ 14
55#define EXCP_VFIQ 15
56#define EXCP_SEMIHOST 16
57
58#define ARMV7M_EXCP_RESET 1
59#define ARMV7M_EXCP_NMI 2
60#define ARMV7M_EXCP_HARD 3
61#define ARMV7M_EXCP_MEM 4
62#define ARMV7M_EXCP_BUS 5
63#define ARMV7M_EXCP_USAGE 6
64#define ARMV7M_EXCP_SVC 11
65#define ARMV7M_EXCP_DEBUG 12
66#define ARMV7M_EXCP_PENDSV 14
67#define ARMV7M_EXCP_SYSTICK 15
68
69
70#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
71#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
72#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
73
74
75
76
77
78
79
80#ifdef HOST_WORDS_BIGENDIAN
81#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
82#define offsetofhigh32(S, M) offsetof(S, M)
83#else
84#define offsetoflow32(S, M) offsetof(S, M)
85#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
86#endif
87
88
89#define ARM_CPU_IRQ 0
90#define ARM_CPU_FIQ 1
91#define ARM_CPU_VIRQ 2
92#define ARM_CPU_VFIQ 3
93
94struct arm_boot_info;
95
96#define NB_MMU_MODES 7
97#define TARGET_INSN_START_EXTRA_WORDS 1
98
99
100
101
102
103
104
105
106
107
108typedef struct ARMGenericTimer {
109 uint64_t cval;
110 uint64_t ctl;
111} ARMGenericTimer;
112
113#define GTIMER_PHYS 0
114#define GTIMER_VIRT 1
115#define GTIMER_HYP 2
116#define GTIMER_SEC 3
117#define NUM_GTIMERS 4
118
119typedef struct {
120 uint64_t raw_tcr;
121 uint32_t mask;
122 uint32_t base_mask;
123} TCR;
124
125typedef struct CPUARMState {
126
127 uint32_t regs[16];
128
129
130
131
132
133
134 uint64_t xregs[32];
135 uint64_t pc;
136
137
138
139
140
141
142
143
144
145
146
147 uint32_t pstate;
148 uint32_t aarch64;
149
150
151
152
153 uint32_t uncached_cpsr;
154 uint32_t spsr;
155
156
157 uint64_t banked_spsr[8];
158 uint32_t banked_r13[8];
159 uint32_t banked_r14[8];
160
161
162 uint32_t usr_regs[5];
163 uint32_t fiq_regs[5];
164
165
166 uint32_t CF;
167 uint32_t VF;
168 uint32_t NF;
169 uint32_t ZF;
170 uint32_t QF;
171 uint32_t GE;
172 uint32_t thumb;
173 uint32_t condexec_bits;
174 uint64_t daif;
175
176 uint64_t elr_el[4];
177 uint64_t sp_el[4];
178
179
180 struct {
181 uint32_t c0_cpuid;
182 union {
183 struct {
184 uint64_t _unused_csselr0;
185 uint64_t csselr_ns;
186 uint64_t _unused_csselr1;
187 uint64_t csselr_s;
188 };
189 uint64_t csselr_el[4];
190 };
191 union {
192 struct {
193 uint64_t _unused_sctlr;
194 uint64_t sctlr_ns;
195 uint64_t hsctlr;
196 uint64_t sctlr_s;
197 };
198 uint64_t sctlr_el[4];
199 };
200 uint64_t cpacr_el1;
201 uint64_t cptr_el[4];
202 uint32_t c1_xscaleauxcr;
203 uint64_t sder;
204 uint32_t nsacr;
205 union {
206 struct {
207 uint64_t _unused_ttbr0_0;
208 uint64_t ttbr0_ns;
209 uint64_t _unused_ttbr0_1;
210 uint64_t ttbr0_s;
211 };
212 uint64_t ttbr0_el[4];
213 };
214 union {
215 struct {
216 uint64_t _unused_ttbr1_0;
217 uint64_t ttbr1_ns;
218 uint64_t _unused_ttbr1_1;
219 uint64_t ttbr1_s;
220 };
221 uint64_t ttbr1_el[4];
222 };
223 uint64_t vttbr_el2;
224
225 TCR tcr_el[4];
226 TCR vtcr_el2;
227 uint32_t c2_data;
228 uint32_t c2_insn;
229 union {
230
231
232 struct {
233 uint64_t dacr_ns;
234 uint64_t dacr_s;
235 };
236 struct {
237 uint64_t dacr32_el2;
238 };
239 };
240 uint32_t pmsav5_data_ap;
241 uint32_t pmsav5_insn_ap;
242 uint64_t hcr_el2;
243 uint64_t scr_el3;
244 union {
245 struct {
246 uint64_t ifsr_ns;
247 uint64_t ifsr_s;
248 };
249 struct {
250 uint64_t ifsr32_el2;
251 };
252 };
253 union {
254 struct {
255 uint64_t _unused_dfsr;
256 uint64_t dfsr_ns;
257 uint64_t hsr;
258 uint64_t dfsr_s;
259 };
260 uint64_t esr_el[4];
261 };
262 uint32_t c6_region[8];
263 union {
264 struct {
265 uint64_t _unused_far0;
266#ifdef HOST_WORDS_BIGENDIAN
267 uint32_t ifar_ns;
268 uint32_t dfar_ns;
269 uint32_t ifar_s;
270 uint32_t dfar_s;
271#else
272 uint32_t dfar_ns;
273 uint32_t ifar_ns;
274 uint32_t dfar_s;
275 uint32_t ifar_s;
276#endif
277 uint64_t _unused_far3;
278 };
279 uint64_t far_el[4];
280 };
281 uint64_t hpfar_el2;
282 union {
283 struct {
284 uint64_t _unused_par_0;
285 uint64_t par_ns;
286 uint64_t _unused_par_1;
287 uint64_t par_s;
288 };
289 uint64_t par_el[4];
290 };
291
292 uint32_t c6_rgnr;
293
294 uint32_t c9_insn;
295 uint32_t c9_data;
296 uint64_t c9_pmcr;
297 uint64_t c9_pmcnten;
298 uint32_t c9_pmovsr;
299 uint32_t c9_pmxevtyper;
300 uint32_t c9_pmuserenr;
301 uint32_t c9_pminten;
302 union {
303 struct {
304#ifdef HOST_WORDS_BIGENDIAN
305 uint64_t _unused_mair_0;
306 uint32_t mair1_ns;
307 uint32_t mair0_ns;
308 uint64_t _unused_mair_1;
309 uint32_t mair1_s;
310 uint32_t mair0_s;
311#else
312 uint64_t _unused_mair_0;
313 uint32_t mair0_ns;
314 uint32_t mair1_ns;
315 uint64_t _unused_mair_1;
316 uint32_t mair0_s;
317 uint32_t mair1_s;
318#endif
319 };
320 uint64_t mair_el[4];
321 };
322 union {
323 struct {
324 uint64_t _unused_vbar;
325 uint64_t vbar_ns;
326 uint64_t hvbar;
327 uint64_t vbar_s;
328 };
329 uint64_t vbar_el[4];
330 };
331 uint32_t mvbar;
332 struct {
333 uint32_t fcseidr_ns;
334 uint32_t fcseidr_s;
335 };
336 union {
337 struct {
338 uint64_t _unused_contextidr_0;
339 uint64_t contextidr_ns;
340 uint64_t _unused_contextidr_1;
341 uint64_t contextidr_s;
342 };
343 uint64_t contextidr_el[4];
344 };
345 union {
346 struct {
347 uint64_t tpidrurw_ns;
348 uint64_t tpidrprw_ns;
349 uint64_t htpidr;
350 uint64_t _tpidr_el3;
351 };
352 uint64_t tpidr_el[4];
353 };
354
355 uint64_t tpidrurw_s;
356 uint64_t tpidrprw_s;
357 uint64_t tpidruro_s;
358
359 union {
360 uint64_t tpidruro_ns;
361 uint64_t tpidrro_el[1];
362 };
363 uint64_t c14_cntfrq;
364 uint64_t c14_cntkctl;
365 uint32_t cnthctl_el2;
366 uint64_t cntvoff_el2;
367 ARMGenericTimer c14_timer[NUM_GTIMERS];
368 uint32_t c15_cpar;
369 uint32_t c15_ticonfig;
370 uint32_t c15_i_max;
371 uint32_t c15_i_min;
372 uint32_t c15_threadid;
373 uint32_t c15_config_base_address;
374 uint32_t c15_diagnostic;
375 uint32_t c15_power_diagnostic;
376 uint32_t c15_power_control;
377 uint64_t dbgbvr[16];
378 uint64_t dbgbcr[16];
379 uint64_t dbgwvr[16];
380 uint64_t dbgwcr[16];
381 uint64_t mdscr_el1;
382 uint64_t oslsr_el1;
383 uint64_t mdcr_el2;
384 uint64_t mdcr_el3;
385
386
387
388 uint64_t c15_ccnt;
389 uint64_t pmccfiltr_el0;
390 uint64_t vpidr_el2;
391 uint64_t vmpidr_el2;
392 } cp15;
393
394 struct {
395 uint32_t other_sp;
396 uint32_t vecbase;
397 uint32_t basepri;
398 uint32_t control;
399 int current_sp;
400 int exception;
401 } v7m;
402
403
404
405
406
407
408
409 struct {
410 uint32_t syndrome;
411 uint32_t fsr;
412 uint64_t vaddress;
413 uint32_t target_el;
414
415
416
417 } exception;
418
419
420 uint32_t teecr;
421 uint32_t teehbr;
422
423
424 struct {
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440 float64 regs[64];
441
442 uint32_t xregs[16];
443
444 int vec_len;
445 int vec_stride;
446
447
448 uint32_t scratch[8];
449
450
451
452
453
454
455
456
457
458
459
460
461
462 float_status fp_status;
463 float_status standard_fp_status;
464 } vfp;
465 uint64_t exclusive_addr;
466 uint64_t exclusive_val;
467 uint64_t exclusive_high;
468#if defined(CONFIG_USER_ONLY)
469 uint64_t exclusive_test;
470 uint32_t exclusive_info;
471#endif
472
473
474 struct {
475 uint64_t regs[16];
476 uint64_t val;
477
478 uint32_t cregs[16];
479 } iwmmxt;
480
481#if defined(CONFIG_USER_ONLY)
482
483 int eabi;
484#endif
485
486 struct CPUBreakpoint *cpu_breakpoint[16];
487 struct CPUWatchpoint *cpu_watchpoint[16];
488
489 CPU_COMMON
490
491
492
493
494 uint64_t features;
495
496
497 struct {
498 uint32_t *drbar;
499 uint32_t *drsr;
500 uint32_t *dracr;
501 } pmsav7;
502
503 void *nvic;
504 const struct arm_boot_info *boot_info;
505} CPUARMState;
506
507#include "cpu-qom.h"
508
509ARMCPU *cpu_arm_init(const char *cpu_model);
510int cpu_arm_exec(CPUState *cpu);
511target_ulong do_arm_semihosting(CPUARMState *env);
512void aarch64_sync_32_to_64(CPUARMState *env);
513void aarch64_sync_64_to_32(CPUARMState *env);
514
515static inline bool is_a64(CPUARMState *env)
516{
517 return env->aarch64;
518}
519
520
521
522
523int cpu_arm_signal_handler(int host_signum, void *pinfo,
524 void *puc);
525
526
527
528
529
530
531
532
533
534
535void pmccntr_sync(CPUARMState *env);
536
537
538
539
540
541
542
543#define SCTLR_M (1U << 0)
544#define SCTLR_A (1U << 1)
545#define SCTLR_C (1U << 2)
546#define SCTLR_W (1U << 3)
547#define SCTLR_SA (1U << 3)
548#define SCTLR_P (1U << 4)
549#define SCTLR_SA0 (1U << 4)
550#define SCTLR_D (1U << 5)
551#define SCTLR_CP15BEN (1U << 5)
552#define SCTLR_L (1U << 6)
553#define SCTLR_B (1U << 7)
554#define SCTLR_ITD (1U << 7)
555#define SCTLR_S (1U << 8)
556#define SCTLR_SED (1U << 8)
557#define SCTLR_R (1U << 9)
558#define SCTLR_UMA (1U << 9)
559#define SCTLR_F (1U << 10)
560#define SCTLR_SW (1U << 10)
561#define SCTLR_Z (1U << 11)
562#define SCTLR_I (1U << 12)
563#define SCTLR_V (1U << 13)
564#define SCTLR_RR (1U << 14)
565#define SCTLR_DZE (1U << 14)
566#define SCTLR_L4 (1U << 15)
567#define SCTLR_UCT (1U << 15)
568#define SCTLR_DT (1U << 16)
569#define SCTLR_nTWI (1U << 16)
570#define SCTLR_HA (1U << 17)
571#define SCTLR_BR (1U << 17)
572#define SCTLR_IT (1U << 18)
573#define SCTLR_nTWE (1U << 18)
574#define SCTLR_WXN (1U << 19)
575#define SCTLR_ST (1U << 20)
576#define SCTLR_UWXN (1U << 20)
577#define SCTLR_FI (1U << 21)
578#define SCTLR_U (1U << 22)
579#define SCTLR_XP (1U << 23)
580#define SCTLR_VE (1U << 24)
581#define SCTLR_E0E (1U << 24)
582#define SCTLR_EE (1U << 25)
583#define SCTLR_L2 (1U << 26)
584#define SCTLR_UCI (1U << 26)
585#define SCTLR_NMFI (1U << 27)
586#define SCTLR_TRE (1U << 28)
587#define SCTLR_AFE (1U << 29)
588#define SCTLR_TE (1U << 30)
589
590#define CPTR_TCPAC (1U << 31)
591#define CPTR_TTA (1U << 20)
592#define CPTR_TFP (1U << 10)
593
594#define MDCR_EPMAD (1U << 21)
595#define MDCR_EDAD (1U << 20)
596#define MDCR_SPME (1U << 17)
597#define MDCR_SDD (1U << 16)
598#define MDCR_SPD (3U << 14)
599#define MDCR_TDRA (1U << 11)
600#define MDCR_TDOSA (1U << 10)
601#define MDCR_TDA (1U << 9)
602#define MDCR_TDE (1U << 8)
603#define MDCR_HPME (1U << 7)
604#define MDCR_TPM (1U << 6)
605#define MDCR_TPMCR (1U << 5)
606
607
608#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
609
610#define CPSR_M (0x1fU)
611#define CPSR_T (1U << 5)
612#define CPSR_F (1U << 6)
613#define CPSR_I (1U << 7)
614#define CPSR_A (1U << 8)
615#define CPSR_E (1U << 9)
616#define CPSR_IT_2_7 (0xfc00U)
617#define CPSR_GE (0xfU << 16)
618#define CPSR_IL (1U << 20)
619
620
621
622
623
624#define CPSR_RESERVED (0x7U << 21)
625#define CPSR_J (1U << 24)
626#define CPSR_IT_0_1 (3U << 25)
627#define CPSR_Q (1U << 27)
628#define CPSR_V (1U << 28)
629#define CPSR_C (1U << 29)
630#define CPSR_Z (1U << 30)
631#define CPSR_N (1U << 31)
632#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
633#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
634
635#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
636#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
637 | CPSR_NZCV)
638
639#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
640
641#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
642
643#define CPSR_ERET_MASK (~CPSR_RESERVED)
644
645#define TTBCR_N (7U << 0)
646#define TTBCR_T0SZ (7U << 0)
647#define TTBCR_PD0 (1U << 4)
648#define TTBCR_PD1 (1U << 5)
649#define TTBCR_EPD0 (1U << 7)
650#define TTBCR_IRGN0 (3U << 8)
651#define TTBCR_ORGN0 (3U << 10)
652#define TTBCR_SH0 (3U << 12)
653#define TTBCR_T1SZ (3U << 16)
654#define TTBCR_A1 (1U << 22)
655#define TTBCR_EPD1 (1U << 23)
656#define TTBCR_IRGN1 (3U << 24)
657#define TTBCR_ORGN1 (3U << 26)
658#define TTBCR_SH1 (1U << 28)
659#define TTBCR_EAE (1U << 31)
660
661
662
663
664
665#define PSTATE_SP (1U)
666#define PSTATE_M (0xFU)
667#define PSTATE_nRW (1U << 4)
668#define PSTATE_F (1U << 6)
669#define PSTATE_I (1U << 7)
670#define PSTATE_A (1U << 8)
671#define PSTATE_D (1U << 9)
672#define PSTATE_IL (1U << 20)
673#define PSTATE_SS (1U << 21)
674#define PSTATE_V (1U << 28)
675#define PSTATE_C (1U << 29)
676#define PSTATE_Z (1U << 30)
677#define PSTATE_N (1U << 31)
678#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
679#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
680#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
681
682#define PSTATE_MODE_EL3h 13
683#define PSTATE_MODE_EL3t 12
684#define PSTATE_MODE_EL2h 9
685#define PSTATE_MODE_EL2t 8
686#define PSTATE_MODE_EL1h 5
687#define PSTATE_MODE_EL1t 4
688#define PSTATE_MODE_EL0t 0
689
690
691static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
692{
693 return (el << 2) | handler;
694}
695
696
697
698
699
700static inline uint32_t pstate_read(CPUARMState *env)
701{
702 int ZF;
703
704 ZF = (env->ZF == 0);
705 return (env->NF & 0x80000000) | (ZF << 30)
706 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
707 | env->pstate | env->daif;
708}
709
710static inline void pstate_write(CPUARMState *env, uint32_t val)
711{
712 env->ZF = (~val) & PSTATE_Z;
713 env->NF = val;
714 env->CF = (val >> 29) & 1;
715 env->VF = (val << 3) & 0x80000000;
716 env->daif = val & PSTATE_DAIF;
717 env->pstate = val & ~CACHED_PSTATE_BITS;
718}
719
720
721uint32_t cpsr_read(CPUARMState *env);
722
723typedef enum CPSRWriteType {
724 CPSRWriteByInstr = 0,
725 CPSRWriteExceptionReturn = 1,
726 CPSRWriteRaw = 2,
727 CPSRWriteByGDBStub = 3,
728} CPSRWriteType;
729
730
731void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
732 CPSRWriteType write_type);
733
734
735static inline uint32_t xpsr_read(CPUARMState *env)
736{
737 int ZF;
738 ZF = (env->ZF == 0);
739 return (env->NF & 0x80000000) | (ZF << 30)
740 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
741 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
742 | ((env->condexec_bits & 0xfc) << 8)
743 | env->v7m.exception;
744}
745
746
747static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
748{
749 if (mask & CPSR_NZCV) {
750 env->ZF = (~val) & CPSR_Z;
751 env->NF = val;
752 env->CF = (val >> 29) & 1;
753 env->VF = (val << 3) & 0x80000000;
754 }
755 if (mask & CPSR_Q)
756 env->QF = ((val & CPSR_Q) != 0);
757 if (mask & (1 << 24))
758 env->thumb = ((val & (1 << 24)) != 0);
759 if (mask & CPSR_IT_0_1) {
760 env->condexec_bits &= ~3;
761 env->condexec_bits |= (val >> 25) & 3;
762 }
763 if (mask & CPSR_IT_2_7) {
764 env->condexec_bits &= 3;
765 env->condexec_bits |= (val >> 8) & 0xfc;
766 }
767 if (mask & 0x1ff) {
768 env->v7m.exception = val & 0x1ff;
769 }
770}
771
772#define HCR_VM (1ULL << 0)
773#define HCR_SWIO (1ULL << 1)
774#define HCR_PTW (1ULL << 2)
775#define HCR_FMO (1ULL << 3)
776#define HCR_IMO (1ULL << 4)
777#define HCR_AMO (1ULL << 5)
778#define HCR_VF (1ULL << 6)
779#define HCR_VI (1ULL << 7)
780#define HCR_VSE (1ULL << 8)
781#define HCR_FB (1ULL << 9)
782#define HCR_BSU_MASK (3ULL << 10)
783#define HCR_DC (1ULL << 12)
784#define HCR_TWI (1ULL << 13)
785#define HCR_TWE (1ULL << 14)
786#define HCR_TID0 (1ULL << 15)
787#define HCR_TID1 (1ULL << 16)
788#define HCR_TID2 (1ULL << 17)
789#define HCR_TID3 (1ULL << 18)
790#define HCR_TSC (1ULL << 19)
791#define HCR_TIDCP (1ULL << 20)
792#define HCR_TACR (1ULL << 21)
793#define HCR_TSW (1ULL << 22)
794#define HCR_TPC (1ULL << 23)
795#define HCR_TPU (1ULL << 24)
796#define HCR_TTLB (1ULL << 25)
797#define HCR_TVM (1ULL << 26)
798#define HCR_TGE (1ULL << 27)
799#define HCR_TDZ (1ULL << 28)
800#define HCR_HCD (1ULL << 29)
801#define HCR_TRVM (1ULL << 30)
802#define HCR_RW (1ULL << 31)
803#define HCR_CD (1ULL << 32)
804#define HCR_ID (1ULL << 33)
805#define HCR_MASK ((1ULL << 34) - 1)
806
807#define SCR_NS (1U << 0)
808#define SCR_IRQ (1U << 1)
809#define SCR_FIQ (1U << 2)
810#define SCR_EA (1U << 3)
811#define SCR_FW (1U << 4)
812#define SCR_AW (1U << 5)
813#define SCR_NET (1U << 6)
814#define SCR_SMD (1U << 7)
815#define SCR_HCE (1U << 8)
816#define SCR_SIF (1U << 9)
817#define SCR_RW (1U << 10)
818#define SCR_ST (1U << 11)
819#define SCR_TWI (1U << 12)
820#define SCR_TWE (1U << 13)
821#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
822#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
823
824
825uint32_t vfp_get_fpscr(CPUARMState *env);
826void vfp_set_fpscr(CPUARMState *env, uint32_t val);
827
828
829
830
831
832#define FPSR_MASK 0xf800009f
833#define FPCR_MASK 0x07f79f00
834static inline uint32_t vfp_get_fpsr(CPUARMState *env)
835{
836 return vfp_get_fpscr(env) & FPSR_MASK;
837}
838
839static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
840{
841 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
842 vfp_set_fpscr(env, new_fpscr);
843}
844
845static inline uint32_t vfp_get_fpcr(CPUARMState *env)
846{
847 return vfp_get_fpscr(env) & FPCR_MASK;
848}
849
850static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
851{
852 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
853 vfp_set_fpscr(env, new_fpscr);
854}
855
856enum arm_cpu_mode {
857 ARM_CPU_MODE_USR = 0x10,
858 ARM_CPU_MODE_FIQ = 0x11,
859 ARM_CPU_MODE_IRQ = 0x12,
860 ARM_CPU_MODE_SVC = 0x13,
861 ARM_CPU_MODE_MON = 0x16,
862 ARM_CPU_MODE_ABT = 0x17,
863 ARM_CPU_MODE_HYP = 0x1a,
864 ARM_CPU_MODE_UND = 0x1b,
865 ARM_CPU_MODE_SYS = 0x1f
866};
867
868
869#define ARM_VFP_FPSID 0
870#define ARM_VFP_FPSCR 1
871#define ARM_VFP_MVFR2 5
872#define ARM_VFP_MVFR1 6
873#define ARM_VFP_MVFR0 7
874#define ARM_VFP_FPEXC 8
875#define ARM_VFP_FPINST 9
876#define ARM_VFP_FPINST2 10
877
878
879#define ARM_IWMMXT_wCID 0
880#define ARM_IWMMXT_wCon 1
881#define ARM_IWMMXT_wCSSF 2
882#define ARM_IWMMXT_wCASF 3
883#define ARM_IWMMXT_wCGR0 8
884#define ARM_IWMMXT_wCGR1 9
885#define ARM_IWMMXT_wCGR2 10
886#define ARM_IWMMXT_wCGR3 11
887
888
889
890
891
892enum arm_features {
893 ARM_FEATURE_VFP,
894 ARM_FEATURE_AUXCR,
895 ARM_FEATURE_XSCALE,
896 ARM_FEATURE_IWMMXT,
897 ARM_FEATURE_V6,
898 ARM_FEATURE_V6K,
899 ARM_FEATURE_V7,
900 ARM_FEATURE_THUMB2,
901 ARM_FEATURE_MPU,
902 ARM_FEATURE_VFP3,
903 ARM_FEATURE_VFP_FP16,
904 ARM_FEATURE_NEON,
905 ARM_FEATURE_THUMB_DIV,
906 ARM_FEATURE_M,
907 ARM_FEATURE_OMAPCP,
908 ARM_FEATURE_THUMB2EE,
909 ARM_FEATURE_V7MP,
910 ARM_FEATURE_V4T,
911 ARM_FEATURE_V5,
912 ARM_FEATURE_STRONGARM,
913 ARM_FEATURE_VAPA,
914 ARM_FEATURE_ARM_DIV,
915 ARM_FEATURE_VFP4,
916 ARM_FEATURE_GENERIC_TIMER,
917 ARM_FEATURE_MVFR,
918 ARM_FEATURE_DUMMY_C15_REGS,
919 ARM_FEATURE_CACHE_TEST_CLEAN,
920 ARM_FEATURE_CACHE_DIRTY_REG,
921 ARM_FEATURE_CACHE_BLOCK_OPS,
922 ARM_FEATURE_MPIDR,
923 ARM_FEATURE_PXN,
924 ARM_FEATURE_LPAE,
925 ARM_FEATURE_V8,
926 ARM_FEATURE_AARCH64,
927 ARM_FEATURE_V8_AES,
928 ARM_FEATURE_CBAR,
929 ARM_FEATURE_CRC,
930 ARM_FEATURE_CBAR_RO,
931 ARM_FEATURE_EL2,
932 ARM_FEATURE_EL3,
933 ARM_FEATURE_V8_SHA1,
934 ARM_FEATURE_V8_SHA256,
935 ARM_FEATURE_V8_PMULL,
936 ARM_FEATURE_THUMB_DSP,
937};
938
939static inline int arm_feature(CPUARMState *env, int feature)
940{
941 return (env->features & (1ULL << feature)) != 0;
942}
943
944#if !defined(CONFIG_USER_ONLY)
945
946
947
948
949
950
951static inline bool arm_is_secure_below_el3(CPUARMState *env)
952{
953 if (arm_feature(env, ARM_FEATURE_EL3)) {
954 return !(env->cp15.scr_el3 & SCR_NS);
955 } else {
956
957
958
959 return false;
960 }
961}
962
963
964static inline bool arm_is_secure(CPUARMState *env)
965{
966 if (arm_feature(env, ARM_FEATURE_EL3)) {
967 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
968
969 return true;
970 } else if (!is_a64(env) &&
971 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
972
973 return true;
974 }
975 }
976 return arm_is_secure_below_el3(env);
977}
978
979#else
980static inline bool arm_is_secure_below_el3(CPUARMState *env)
981{
982 return false;
983}
984
985static inline bool arm_is_secure(CPUARMState *env)
986{
987 return false;
988}
989#endif
990
991
992static inline bool arm_el_is_aa64(CPUARMState *env, int el)
993{
994
995
996
997 assert(el >= 1 && el <= 3);
998 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
999
1000
1001
1002
1003
1004 if (el == 3) {
1005 return aa64;
1006 }
1007
1008 if (arm_feature(env, ARM_FEATURE_EL3)) {
1009 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
1010 }
1011
1012 if (el == 2) {
1013 return aa64;
1014 }
1015
1016 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
1017 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
1018 }
1019
1020 return aa64;
1021}
1022
1023
1024
1025
1026
1027
1028
1029
1030static inline bool access_secure_reg(CPUARMState *env)
1031{
1032 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
1033 !arm_el_is_aa64(env, 3) &&
1034 !(env->cp15.scr_el3 & SCR_NS));
1035
1036 return ret;
1037}
1038
1039
1040#define A32_BANKED_REG_GET(_env, _regname, _secure) \
1041 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1042
1043#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1044 do { \
1045 if (_secure) { \
1046 (_env)->cp15._regname##_s = (_val); \
1047 } else { \
1048 (_env)->cp15._regname##_ns = (_val); \
1049 } \
1050 } while (0)
1051
1052
1053
1054
1055
1056
1057#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1058 A32_BANKED_REG_GET((_env), _regname, \
1059 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1060
1061#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1062 A32_BANKED_REG_SET((_env), _regname, \
1063 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1064 (_val))
1065
1066void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1067uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
1068 uint32_t cur_el, bool secure);
1069
1070
1071void armv7m_nvic_set_pending(void *opaque, int irq);
1072int armv7m_nvic_acknowledge_irq(void *opaque);
1073void armv7m_nvic_complete_irq(void *opaque, int irq);
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101#define CP_REG_AA64_SHIFT 28
1102#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1103
1104
1105
1106
1107
1108#define CP_REG_NS_SHIFT 29
1109#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1110
1111#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1112 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1113 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1114
1115#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1116 (CP_REG_AA64_MASK | \
1117 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1118 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1119 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1120 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1121 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1122 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1123
1124
1125
1126
1127static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
1128{
1129 uint32_t cpregid = kvmid;
1130 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
1131 cpregid |= CP_REG_AA64_MASK;
1132 } else {
1133 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
1134 cpregid |= (1 << 15);
1135 }
1136
1137
1138
1139
1140 cpregid |= 1 << CP_REG_NS_SHIFT;
1141 }
1142 return cpregid;
1143}
1144
1145
1146
1147
1148static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
1149{
1150 uint64_t kvmid;
1151
1152 if (cpregid & CP_REG_AA64_MASK) {
1153 kvmid = cpregid & ~CP_REG_AA64_MASK;
1154 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
1155 } else {
1156 kvmid = cpregid & ~(1 << 15);
1157 if (cpregid & (1 << 15)) {
1158 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
1159 } else {
1160 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
1161 }
1162 }
1163 return kvmid;
1164}
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188#define ARM_CP_SPECIAL 1
1189#define ARM_CP_CONST 2
1190#define ARM_CP_64BIT 4
1191#define ARM_CP_SUPPRESS_TB_END 8
1192#define ARM_CP_OVERRIDE 16
1193#define ARM_CP_ALIAS 32
1194#define ARM_CP_IO 64
1195#define ARM_CP_NO_RAW 128
1196#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1197#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
1198#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
1199#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
1200#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1201#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1202
1203#define ARM_CP_SENTINEL 0xffff
1204
1205#define ARM_CP_FLAG_MASK 0xff
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216enum {
1217 ARM_CP_STATE_AA32 = 0,
1218 ARM_CP_STATE_AA64 = 1,
1219 ARM_CP_STATE_BOTH = 2,
1220};
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232enum {
1233 ARM_CP_SECSTATE_S = (1 << 0),
1234 ARM_CP_SECSTATE_NS = (1 << 1),
1235};
1236
1237
1238
1239
1240
1241static inline bool cptype_valid(int cptype)
1242{
1243 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
1244 || ((cptype & ARM_CP_SPECIAL) &&
1245 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
1246}
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265#define PL3_R 0x80
1266#define PL3_W 0x40
1267#define PL2_R (0x20 | PL3_R)
1268#define PL2_W (0x10 | PL3_W)
1269#define PL1_R (0x08 | PL2_R)
1270#define PL1_W (0x04 | PL2_W)
1271#define PL0_R (0x02 | PL1_R)
1272#define PL0_W (0x01 | PL1_W)
1273
1274#define PL3_RW (PL3_R | PL3_W)
1275#define PL2_RW (PL2_R | PL2_W)
1276#define PL1_RW (PL1_R | PL1_W)
1277#define PL0_RW (PL0_R | PL0_W)
1278
1279
1280static inline int arm_highest_el(CPUARMState *env)
1281{
1282 if (arm_feature(env, ARM_FEATURE_EL3)) {
1283 return 3;
1284 }
1285 if (arm_feature(env, ARM_FEATURE_EL2)) {
1286 return 2;
1287 }
1288 return 1;
1289}
1290
1291
1292
1293
1294static inline int arm_current_el(CPUARMState *env)
1295{
1296 if (arm_feature(env, ARM_FEATURE_M)) {
1297 return !((env->v7m.exception == 0) && (env->v7m.control & 1));
1298 }
1299
1300 if (is_a64(env)) {
1301 return extract32(env->pstate, 2, 2);
1302 }
1303
1304 switch (env->uncached_cpsr & 0x1f) {
1305 case ARM_CPU_MODE_USR:
1306 return 0;
1307 case ARM_CPU_MODE_HYP:
1308 return 2;
1309 case ARM_CPU_MODE_MON:
1310 return 3;
1311 default:
1312 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1313
1314
1315
1316 return 3;
1317 }
1318
1319 return 1;
1320 }
1321}
1322
1323typedef struct ARMCPRegInfo ARMCPRegInfo;
1324
1325typedef enum CPAccessResult {
1326
1327 CP_ACCESS_OK = 0,
1328
1329
1330
1331
1332
1333
1334 CP_ACCESS_TRAP = 1,
1335
1336
1337
1338
1339 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
1340
1341 CP_ACCESS_TRAP_EL2 = 3,
1342 CP_ACCESS_TRAP_EL3 = 4,
1343
1344 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
1345 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
1346
1347
1348
1349 CP_ACCESS_TRAP_FP_EL2 = 7,
1350 CP_ACCESS_TRAP_FP_EL3 = 8,
1351} CPAccessResult;
1352
1353
1354
1355
1356typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1357typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
1358 uint64_t value);
1359
1360typedef CPAccessResult CPAccessFn(CPUARMState *env,
1361 const ARMCPRegInfo *opaque,
1362 bool isread);
1363
1364typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1365
1366#define CP_ANY 0xff
1367
1368
1369struct ARMCPRegInfo {
1370
1371 const char *name;
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389 uint8_t cp;
1390 uint8_t crn;
1391 uint8_t crm;
1392 uint8_t opc0;
1393 uint8_t opc1;
1394 uint8_t opc2;
1395
1396 int state;
1397
1398 int type;
1399
1400 int access;
1401
1402 int secure;
1403
1404
1405
1406
1407 void *opaque;
1408
1409
1410
1411 uint64_t resetvalue;
1412
1413
1414
1415
1416
1417
1418 ptrdiff_t fieldoffset;
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431 ptrdiff_t bank_fieldoffsets[2];
1432
1433
1434
1435
1436
1437
1438 CPAccessFn *accessfn;
1439
1440
1441
1442
1443 CPReadFn *readfn;
1444
1445
1446
1447
1448 CPWriteFn *writefn;
1449
1450
1451
1452
1453
1454 CPReadFn *raw_readfn;
1455
1456
1457
1458
1459
1460
1461 CPWriteFn *raw_writefn;
1462
1463
1464
1465
1466 CPResetFn *resetfn;
1467};
1468
1469
1470
1471
1472#define CPREG_FIELD32(env, ri) \
1473 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1474#define CPREG_FIELD64(env, ri) \
1475 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1476
1477#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1478
1479void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1480 const ARMCPRegInfo *regs, void *opaque);
1481void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1482 const ARMCPRegInfo *regs, void *opaque);
1483static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
1484{
1485 define_arm_cp_regs_with_opaque(cpu, regs, 0);
1486}
1487static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
1488{
1489 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
1490}
1491const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
1492
1493
1494void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1495 uint64_t value);
1496
1497uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
1498
1499
1500
1501
1502void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
1503
1504
1505
1506
1507static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
1508{
1509 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
1510}
1511
1512static inline bool cp_access_ok(int current_el,
1513 const ARMCPRegInfo *ri, int isread)
1514{
1515 return (ri->access >> ((current_el * 2) + isread)) & 1;
1516}
1517
1518
1519uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535bool write_list_to_cpustate(ARMCPU *cpu);
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551bool write_cpustate_to_list(ARMCPU *cpu);
1552
1553
1554
1555
1556
1557#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
1558
1559#define ARM_CPUID_TI915T 0x54029152
1560#define ARM_CPUID_TI925T 0x54029252
1561
1562#if defined(CONFIG_USER_ONLY)
1563#define TARGET_PAGE_BITS 12
1564#else
1565
1566
1567
1568#define TARGET_PAGE_BITS 10
1569#endif
1570
1571#if defined(TARGET_AARCH64)
1572# define TARGET_PHYS_ADDR_SPACE_BITS 48
1573# define TARGET_VIRT_ADDR_SPACE_BITS 64
1574#else
1575# define TARGET_PHYS_ADDR_SPACE_BITS 40
1576# define TARGET_VIRT_ADDR_SPACE_BITS 32
1577#endif
1578
1579static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
1580 unsigned int target_el)
1581{
1582 CPUARMState *env = cs->env_ptr;
1583 unsigned int cur_el = arm_current_el(env);
1584 bool secure = arm_is_secure(env);
1585 bool pstate_unmasked;
1586 int8_t unmasked = 0;
1587
1588
1589
1590
1591
1592 if (cur_el > target_el) {
1593 return false;
1594 }
1595
1596 switch (excp_idx) {
1597 case EXCP_FIQ:
1598 pstate_unmasked = !(env->daif & PSTATE_F);
1599 break;
1600
1601 case EXCP_IRQ:
1602 pstate_unmasked = !(env->daif & PSTATE_I);
1603 break;
1604
1605 case EXCP_VFIQ:
1606 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
1607
1608 return false;
1609 }
1610 return !(env->daif & PSTATE_F);
1611 case EXCP_VIRQ:
1612 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
1613
1614 return false;
1615 }
1616 return !(env->daif & PSTATE_I);
1617 default:
1618 g_assert_not_reached();
1619 }
1620
1621
1622
1623
1624
1625 if ((target_el > cur_el) && (target_el != 1)) {
1626
1627 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
1628
1629
1630
1631
1632
1633 if (target_el == 3 || !secure) {
1634 unmasked = 1;
1635 }
1636 } else {
1637
1638
1639
1640
1641 bool hcr, scr;
1642
1643 switch (excp_idx) {
1644 case EXCP_FIQ:
1645
1646
1647
1648
1649
1650
1651 hcr = (env->cp15.hcr_el2 & HCR_FMO);
1652 scr = (env->cp15.scr_el3 & SCR_FIQ);
1653
1654
1655
1656
1657
1658
1659 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
1660 break;
1661 case EXCP_IRQ:
1662
1663
1664
1665
1666
1667
1668 hcr = (env->cp15.hcr_el2 & HCR_IMO);
1669 scr = false;
1670 break;
1671 default:
1672 g_assert_not_reached();
1673 }
1674
1675 if ((scr || hcr) && !secure) {
1676 unmasked = 1;
1677 }
1678 }
1679 }
1680
1681
1682
1683
1684 return unmasked || pstate_unmasked;
1685}
1686
1687#define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
1688
1689#define cpu_exec cpu_arm_exec
1690#define cpu_signal_handler cpu_arm_signal_handler
1691#define cpu_list arm_cpu_list
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744typedef enum ARMMMUIdx {
1745 ARMMMUIdx_S12NSE0 = 0,
1746 ARMMMUIdx_S12NSE1 = 1,
1747 ARMMMUIdx_S1E2 = 2,
1748 ARMMMUIdx_S1E3 = 3,
1749 ARMMMUIdx_S1SE0 = 4,
1750 ARMMMUIdx_S1SE1 = 5,
1751 ARMMMUIdx_S2NS = 6,
1752
1753
1754
1755 ARMMMUIdx_S1NSE0 = 7,
1756 ARMMMUIdx_S1NSE1 = 8,
1757} ARMMMUIdx;
1758
1759#define MMU_USER_IDX 0
1760
1761
1762static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
1763{
1764 assert(mmu_idx < ARMMMUIdx_S2NS);
1765 return mmu_idx & 3;
1766}
1767
1768
1769static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
1770{
1771 int el = arm_current_el(env);
1772
1773 if (el < 2 && arm_is_secure_below_el3(env)) {
1774 return ARMMMUIdx_S1SE0 + el;
1775 }
1776 return el;
1777}
1778
1779
1780typedef enum ARMASIdx {
1781 ARMASIdx_NS = 0,
1782 ARMASIdx_S = 1,
1783} ARMASIdx;
1784
1785
1786static inline int arm_debug_target_el(CPUARMState *env)
1787{
1788 bool secure = arm_is_secure(env);
1789 bool route_to_el2 = false;
1790
1791 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
1792 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
1793 env->cp15.mdcr_el2 & (1 << 8);
1794 }
1795
1796 if (route_to_el2) {
1797 return 2;
1798 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
1799 !arm_el_is_aa64(env, 3) && secure) {
1800 return 3;
1801 } else {
1802 return 1;
1803 }
1804}
1805
1806static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
1807{
1808 if (arm_is_secure(env)) {
1809
1810 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0
1811 || arm_current_el(env) == 3) {
1812 return false;
1813 }
1814 }
1815
1816 if (arm_current_el(env) == arm_debug_target_el(env)) {
1817 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
1818 || (env->daif & PSTATE_D)) {
1819 return false;
1820 }
1821 }
1822 return true;
1823}
1824
1825static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
1826{
1827 int el = arm_current_el(env);
1828
1829 if (el == 0 && arm_el_is_aa64(env, 1)) {
1830 return aa64_generate_debug_exceptions(env);
1831 }
1832
1833 if (arm_is_secure(env)) {
1834 int spd;
1835
1836 if (el == 0 && (env->cp15.sder & 1)) {
1837
1838
1839
1840
1841 return true;
1842 }
1843
1844 spd = extract32(env->cp15.mdcr_el3, 14, 2);
1845 switch (spd) {
1846 case 1:
1847
1848 case 0:
1849
1850
1851
1852
1853
1854 return true;
1855 case 2:
1856 return false;
1857 case 3:
1858 return true;
1859 }
1860 }
1861
1862 return el != 2;
1863}
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879static inline bool arm_generate_debug_exceptions(CPUARMState *env)
1880{
1881 if (env->aarch64) {
1882 return aa64_generate_debug_exceptions(env);
1883 } else {
1884 return aa32_generate_debug_exceptions(env);
1885 }
1886}
1887
1888
1889
1890
1891static inline bool arm_singlestep_active(CPUARMState *env)
1892{
1893 return extract32(env->cp15.mdscr_el1, 0, 1)
1894 && arm_el_is_aa64(env, arm_debug_target_el(env))
1895 && arm_generate_debug_exceptions(env);
1896}
1897
1898static inline bool arm_sctlr_b(CPUARMState *env)
1899{
1900 return
1901
1902
1903
1904
1905#ifndef CONFIG_USER_ONLY
1906 !arm_feature(env, ARM_FEATURE_V7) &&
1907#endif
1908 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
1909}
1910
1911
1912static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
1913{
1914 int cur_el;
1915
1916
1917 if (!is_a64(env)) {
1918 return
1919#ifdef CONFIG_USER_ONLY
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931 arm_sctlr_b(env) ||
1932#endif
1933 ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
1934 }
1935
1936 cur_el = arm_current_el(env);
1937
1938 if (cur_el == 0) {
1939 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
1940 }
1941
1942 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
1943}
1944
1945#include "exec/cpu-all.h"
1946
1947
1948
1949
1950
1951
1952#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
1953#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
1954#define ARM_TBFLAG_MMUIDX_SHIFT 28
1955#define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
1956#define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
1957#define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
1958#define ARM_TBFLAG_PSTATE_SS_SHIFT 26
1959#define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
1960
1961#define ARM_TBFLAG_FPEXC_EL_SHIFT 24
1962#define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
1963
1964
1965#define ARM_TBFLAG_THUMB_SHIFT 0
1966#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
1967#define ARM_TBFLAG_VECLEN_SHIFT 1
1968#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
1969#define ARM_TBFLAG_VECSTRIDE_SHIFT 4
1970#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
1971#define ARM_TBFLAG_VFPEN_SHIFT 7
1972#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
1973#define ARM_TBFLAG_CONDEXEC_SHIFT 8
1974#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
1975#define ARM_TBFLAG_SCTLR_B_SHIFT 16
1976#define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
1977
1978
1979
1980#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
1981#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
1982
1983
1984
1985
1986#define ARM_TBFLAG_NS_SHIFT 19
1987#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
1988#define ARM_TBFLAG_BE_DATA_SHIFT 20
1989#define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
1990
1991
1992
1993
1994#define ARM_TBFLAG_AARCH64_STATE(F) \
1995 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
1996#define ARM_TBFLAG_MMUIDX(F) \
1997 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
1998#define ARM_TBFLAG_SS_ACTIVE(F) \
1999 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
2000#define ARM_TBFLAG_PSTATE_SS(F) \
2001 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
2002#define ARM_TBFLAG_FPEXC_EL(F) \
2003 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
2004#define ARM_TBFLAG_THUMB(F) \
2005 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
2006#define ARM_TBFLAG_VECLEN(F) \
2007 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
2008#define ARM_TBFLAG_VECSTRIDE(F) \
2009 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
2010#define ARM_TBFLAG_VFPEN(F) \
2011 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
2012#define ARM_TBFLAG_CONDEXEC(F) \
2013 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
2014#define ARM_TBFLAG_SCTLR_B(F) \
2015 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
2016#define ARM_TBFLAG_XSCALE_CPAR(F) \
2017 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2018#define ARM_TBFLAG_NS(F) \
2019 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
2020#define ARM_TBFLAG_BE_DATA(F) \
2021 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
2022
2023static inline bool bswap_code(bool sctlr_b)
2024{
2025#ifdef CONFIG_USER_ONLY
2026
2027
2028
2029
2030 return
2031#ifdef TARGET_WORDS_BIGENDIAN
2032 1 ^
2033#endif
2034 sctlr_b;
2035#else
2036
2037
2038
2039 return 0;
2040#endif
2041}
2042
2043
2044
2045
2046static inline int fp_exception_el(CPUARMState *env)
2047{
2048 int fpen;
2049 int cur_el = arm_current_el(env);
2050
2051
2052
2053
2054 if (!arm_feature(env, ARM_FEATURE_V6)) {
2055 return 0;
2056 }
2057
2058
2059
2060
2061
2062
2063 fpen = extract32(env->cp15.cpacr_el1, 20, 2);
2064 switch (fpen) {
2065 case 0:
2066 case 2:
2067 if (cur_el == 0 || cur_el == 1) {
2068
2069 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2070 return 3;
2071 }
2072 return 1;
2073 }
2074 if (cur_el == 3 && !is_a64(env)) {
2075
2076 return 3;
2077 }
2078 break;
2079 case 1:
2080 if (cur_el == 0) {
2081 return 1;
2082 }
2083 break;
2084 case 3:
2085 break;
2086 }
2087
2088
2089
2090
2091
2092
2093 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
2094 && !arm_is_secure_below_el3(env)) {
2095
2096 return 2;
2097 }
2098
2099
2100 if (extract32(env->cp15.cptr_el[3], 10, 1)) {
2101
2102 return 3;
2103 }
2104
2105 return 0;
2106}
2107
2108#ifdef CONFIG_USER_ONLY
2109static inline bool arm_cpu_bswap_data(CPUARMState *env)
2110{
2111 return
2112#ifdef TARGET_WORDS_BIGENDIAN
2113 1 ^
2114#endif
2115 arm_cpu_data_is_big_endian(env);
2116}
2117#endif
2118
2119static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
2120 target_ulong *cs_base, int *flags)
2121{
2122 if (is_a64(env)) {
2123 *pc = env->pc;
2124 *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
2125 } else {
2126 *pc = env->regs[15];
2127 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
2128 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
2129 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
2130 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
2131 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT);
2132 if (!(access_secure_reg(env))) {
2133 *flags |= ARM_TBFLAG_NS_MASK;
2134 }
2135 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
2136 || arm_el_is_aa64(env, 1)) {
2137 *flags |= ARM_TBFLAG_VFPEN_MASK;
2138 }
2139 *flags |= (extract32(env->cp15.c15_cpar, 0, 2)
2140 << ARM_TBFLAG_XSCALE_CPAR_SHIFT);
2141 }
2142
2143 *flags |= (cpu_mmu_index(env, false) << ARM_TBFLAG_MMUIDX_SHIFT);
2144
2145
2146
2147
2148
2149
2150
2151 if (arm_singlestep_active(env)) {
2152 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
2153 if (is_a64(env)) {
2154 if (env->pstate & PSTATE_SS) {
2155 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
2156 }
2157 } else {
2158 if (env->uncached_cpsr & PSTATE_SS) {
2159 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
2160 }
2161 }
2162 }
2163 if (arm_cpu_data_is_big_endian(env)) {
2164 *flags |= ARM_TBFLAG_BE_DATA_MASK;
2165 }
2166 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
2167
2168 *cs_base = 0;
2169}
2170
2171#include "exec/exec-all.h"
2172
2173enum {
2174 QEMU_PSCI_CONDUIT_DISABLED = 0,
2175 QEMU_PSCI_CONDUIT_SMC = 1,
2176 QEMU_PSCI_CONDUIT_HVC = 2,
2177};
2178
2179#ifndef CONFIG_USER_ONLY
2180
2181static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2182{
2183 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
2184}
2185
2186
2187
2188
2189
2190static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
2191{
2192 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
2193}
2194#endif
2195
2196#endif
2197