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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "cpu.h"
27#include "qemu-common.h"
28#include "hw/qdev-properties.h"
29#include "migration/vmstate.h"
30
31static const struct {
32 const char *name;
33 uint8_t version_id;
34} mb_cpu_lookup[] = {
35
36 {"5.00.a", 0x01},
37 {"5.00.b", 0x02},
38 {"5.00.c", 0x03},
39 {"6.00.a", 0x04},
40 {"6.00.b", 0x06},
41 {"7.00.a", 0x05},
42 {"7.00.b", 0x07},
43 {"7.10.a", 0x08},
44 {"7.10.b", 0x09},
45 {"7.10.c", 0x0a},
46 {"7.10.d", 0x0b},
47 {"7.20.a", 0x0c},
48 {"7.20.b", 0x0d},
49 {"7.20.c", 0x0e},
50 {"7.20.d", 0x0f},
51 {"7.30.a", 0x10},
52 {"7.30.b", 0x11},
53 {"8.00.a", 0x12},
54 {"8.00.b", 0x13},
55 {"8.10.a", 0x14},
56 {"8.20.a", 0x15},
57 {"8.20.b", 0x16},
58 {"8.30.a", 0x17},
59 {"8.40.a", 0x18},
60 {"8.40.b", 0x19},
61 {"8.50.a", 0x1A},
62 {"9.0", 0x1B},
63 {"9.1", 0x1D},
64 {"9.2", 0x1F},
65 {"9.3", 0x20},
66 {NULL, 0},
67};
68
69static void mb_cpu_set_pc(CPUState *cs, vaddr value)
70{
71 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
72
73 cpu->env.sregs[SR_PC] = value;
74}
75
76static bool mb_cpu_has_work(CPUState *cs)
77{
78 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
79}
80
81#ifndef CONFIG_USER_ONLY
82static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
83{
84 MicroBlazeCPU *cpu = opaque;
85 CPUState *cs = CPU(cpu);
86 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
87
88 if (level) {
89 cpu_interrupt(cs, type);
90 } else {
91 cpu_reset_interrupt(cs, type);
92 }
93}
94#endif
95
96
97static void mb_cpu_reset(CPUState *s)
98{
99 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
100 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
101 CPUMBState *env = &cpu->env;
102
103 mcc->parent_reset(s);
104
105 memset(env, 0, offsetof(CPUMBState, pvr));
106 env->res_addr = RES_ADDR_NONE;
107 tlb_flush(s, 1);
108
109
110 env->shr = ~0;
111
112 env->sregs[SR_PC] = cpu->cfg.base_vectors;
113
114#if defined(CONFIG_USER_ONLY)
115
116 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
117#else
118 env->sregs[SR_MSR] = 0;
119 mmu_init(&env->mmu);
120 env->mmu.c_mmu = 3;
121 env->mmu.c_mmu_tlb_access = 3;
122 env->mmu.c_mmu_zones = 16;
123#endif
124}
125
126static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
127{
128 info->mach = bfd_arch_microblaze;
129 info->print_insn = print_insn_microblaze;
130}
131
132static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
133{
134 CPUState *cs = CPU(dev);
135 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
136 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
137 CPUMBState *env = &cpu->env;
138 uint8_t version_code = 0;
139 int i = 0;
140
141 qemu_init_vcpu(cs);
142
143 env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
144 | PVR0_USE_DIV_MASK \
145 | PVR0_USE_HW_MUL_MASK \
146 | PVR0_USE_EXC_MASK \
147 | PVR0_USE_ICACHE_MASK \
148 | PVR0_USE_DCACHE_MASK \
149 | (0xb << 8);
150 env->pvr.regs[2] = PVR2_D_OPB_MASK \
151 | PVR2_D_LMB_MASK \
152 | PVR2_I_OPB_MASK \
153 | PVR2_I_LMB_MASK \
154 | PVR2_USE_MSR_INSTR \
155 | PVR2_USE_PCMP_INSTR \
156 | PVR2_USE_BARREL_MASK \
157 | PVR2_USE_DIV_MASK \
158 | PVR2_USE_HW_MUL_MASK \
159 | PVR2_USE_MUL64_MASK \
160 | PVR2_FPU_EXC_MASK \
161 | 0;
162
163 for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
164 if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
165 version_code = mb_cpu_lookup[i].version_id;
166 break;
167 }
168 }
169
170 if (!version_code) {
171 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
172 }
173
174 env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
175 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
176 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
177 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
178 (version_code << 16) |
179 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
180
181 env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
182 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
183
184 env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
185 PVR5_DCACHE_WRITEBACK_MASK : 0;
186
187 env->pvr.regs[10] = 0x0c000000;
188 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
189
190 mcc->parent_realize(dev, errp);
191}
192
193static void mb_cpu_initfn(Object *obj)
194{
195 CPUState *cs = CPU(obj);
196 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
197 CPUMBState *env = &cpu->env;
198 static bool tcg_initialized;
199
200 cs->env_ptr = env;
201 cpu_exec_init(cs, &error_abort);
202
203 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
204
205#ifndef CONFIG_USER_ONLY
206
207 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
208#endif
209
210 if (tcg_enabled() && !tcg_initialized) {
211 tcg_initialized = true;
212 mb_tcg_init();
213 }
214}
215
216static const VMStateDescription vmstate_mb_cpu = {
217 .name = "cpu",
218 .unmigratable = 1,
219};
220
221static Property mb_properties[] = {
222 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
223 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
224 false),
225
226
227
228
229 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
230 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
231 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
232 false),
233 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
234 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
235 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
236 DEFINE_PROP_END_OF_LIST(),
237};
238
239static void mb_cpu_class_init(ObjectClass *oc, void *data)
240{
241 DeviceClass *dc = DEVICE_CLASS(oc);
242 CPUClass *cc = CPU_CLASS(oc);
243 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
244
245 mcc->parent_realize = dc->realize;
246 dc->realize = mb_cpu_realizefn;
247
248 mcc->parent_reset = cc->reset;
249 cc->reset = mb_cpu_reset;
250
251 cc->has_work = mb_cpu_has_work;
252 cc->do_interrupt = mb_cpu_do_interrupt;
253 cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
254 cc->dump_state = mb_cpu_dump_state;
255 cc->set_pc = mb_cpu_set_pc;
256 cc->gdb_read_register = mb_cpu_gdb_read_register;
257 cc->gdb_write_register = mb_cpu_gdb_write_register;
258#ifdef CONFIG_USER_ONLY
259 cc->handle_mmu_fault = mb_cpu_handle_mmu_fault;
260#else
261 cc->do_unassigned_access = mb_cpu_unassigned_access;
262 cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
263#endif
264 dc->vmsd = &vmstate_mb_cpu;
265 dc->props = mb_properties;
266 cc->gdb_num_core_regs = 32 + 5;
267
268 cc->disas_set_info = mb_disas_set_info;
269
270
271
272
273
274 dc->cannot_destroy_with_object_finalize_yet = true;
275}
276
277static const TypeInfo mb_cpu_type_info = {
278 .name = TYPE_MICROBLAZE_CPU,
279 .parent = TYPE_CPU,
280 .instance_size = sizeof(MicroBlazeCPU),
281 .instance_init = mb_cpu_initfn,
282 .class_size = sizeof(MicroBlazeCPUClass),
283 .class_init = mb_cpu_class_init,
284};
285
286static void mb_cpu_register_types(void)
287{
288 type_register_static(&mb_cpu_type_info);
289}
290
291type_init(mb_cpu_register_types)
292
