LXR qemu/target-sparc/win

   1/*
   2 * Helpers for CWP and PSTATE handling
   3 *
   4 *  Copyright (c) 2003-2005 Fabrice Bellard
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include "qemu/osdep.h"
  21#include "cpu.h"
  22#include "exec/helper-proto.h"
  23#include "trace.h"
  24
  25static inline void memcpy32(target_ulong *dst, const target_ulong *src)
  26{
  27    dst[0] = src[0];
  28    dst[1] = src[1];
  29    dst[2] = src[2];
  30    dst[3] = src[3];
  31    dst[4] = src[4];
  32    dst[5] = src[5];
  33    dst[6] = src[6];
  34    dst[7] = src[7];
  35}
  36
  37void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
  38{
  39    /* put the modified wrap registers at their proper location */
  40    if (env->cwp == env->nwindows - 1) {
  41        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
  42    }
  43    env->cwp = new_cwp;
  44
  45    /* put the wrap registers at their temporary location */
  46    if (new_cwp == env->nwindows - 1) {
  47        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
  48    }
  49    env->regwptr = env->regbase + (new_cwp * 16);
  50}
  51
  52target_ulong cpu_get_psr(CPUSPARCState *env)
  53{
  54    helper_compute_psr(env);
  55
  56#if !defined(TARGET_SPARC64)
  57    return env->version | (env->psr & PSR_ICC) |
  58        (env->psref ? PSR_EF : 0) |
  59        (env->psrpil << 8) |
  60        (env->psrs ? PSR_S : 0) |
  61        (env->psrps ? PSR_PS : 0) |
  62        (env->psret ? PSR_ET : 0) | env->cwp;
  63#else
  64    return env->psr & PSR_ICC;
  65#endif
  66}
  67
  68void cpu_put_psr_raw(CPUSPARCState *env, target_ulong val)
  69{
  70    env->psr = val & PSR_ICC;
  71#if !defined(TARGET_SPARC64)
  72    env->psref = (val & PSR_EF) ? 1 : 0;
  73    env->psrpil = (val & PSR_PIL) >> 8;
  74    env->psrs = (val & PSR_S) ? 1 : 0;
  75    env->psrps = (val & PSR_PS) ? 1 : 0;
  76    env->psret = (val & PSR_ET) ? 1 : 0;
  77#endif
  78    env->cc_op = CC_OP_FLAGS;
  79#if !defined(TARGET_SPARC64)
  80    cpu_set_cwp(env, val & PSR_CWP);
  81#endif
  82}
  83
  84void cpu_put_psr(CPUSPARCState *env, target_ulong val)
  85{
  86    cpu_put_psr_raw(env, val);
  87#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
  88    cpu_check_irqs(env);
  89#endif
  90}
  91
  92int cpu_cwp_inc(CPUSPARCState *env, int cwp)
  93{
  94    if (unlikely(cwp >= env->nwindows)) {
  95        cwp -= env->nwindows;
  96    }
  97    return cwp;
  98}
  99
 100int cpu_cwp_dec(CPUSPARCState *env, int cwp)
 101{
 102    if (unlikely(cwp < 0)) {
 103        cwp += env->nwindows;
 104    }
 105    return cwp;
 106}
 107
 108#ifndef TARGET_SPARC64
 109void helper_rett(CPUSPARCState *env)
 110{
 111    unsigned int cwp;
 112
 113    if (env->psret == 1) {
 114        helper_raise_exception(env, TT_ILL_INSN);
 115    }
 116
 117    env->psret = 1;
 118    cwp = cpu_cwp_inc(env, env->cwp + 1) ;
 119    if (env->wim & (1 << cwp)) {
 120        helper_raise_exception(env, TT_WIN_UNF);
 121    }
 122    cpu_set_cwp(env, cwp);
 123    env->psrs = env->psrps;
 124}
 125
 126/* XXX: use another pointer for %iN registers to avoid slow wrapping
 127   handling ? */
 128void helper_save(CPUSPARCState *env)
 129{
 130    uint32_t cwp;
 131
 132    cwp = cpu_cwp_dec(env, env->cwp - 1);
 133    if (env->wim & (1 << cwp)) {
 134        helper_raise_exception(env, TT_WIN_OVF);
 135    }
 136    cpu_set_cwp(env, cwp);
 137}
 138
 139void helper_restore(CPUSPARCState *env)
 140{
 141    uint32_t cwp;
 142
 143    cwp = cpu_cwp_inc(env, env->cwp + 1);
 144    if (env->wim & (1 << cwp)) {
 145        helper_raise_exception(env, TT_WIN_UNF);
 146    }
 147    cpu_set_cwp(env, cwp);
 148}
 149
 150void helper_wrpsr(CPUSPARCState *env, target_ulong new_psr)
 151{
 152    if ((new_psr & PSR_CWP) >= env->nwindows) {
 153        helper_raise_exception(env, TT_ILL_INSN);
 154    } else {
 155        cpu_put_psr(env, new_psr);
 156    }
 157}
 158
 159target_ulong helper_rdpsr(CPUSPARCState *env)
 160{
 161    return cpu_get_psr(env);
 162}
 163
 164#else
 165/* XXX: use another pointer for %iN registers to avoid slow wrapping
 166   handling ? */
 167void helper_save(CPUSPARCState *env)
 168{
 169    uint32_t cwp;
 170
 171    cwp = cpu_cwp_dec(env, env->cwp - 1);
 172    if (env->cansave == 0) {
 173        helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ?
 174                                                (TT_WOTHER |
 175                                                 ((env->wstate & 0x38) >> 1)) :
 176                                                ((env->wstate & 0x7) << 2)));
 177    } else {
 178        if (env->cleanwin - env->canrestore == 0) {
 179            /* XXX Clean windows without trap */
 180            helper_raise_exception(env, TT_CLRWIN);
 181        } else {
 182            env->cansave--;
 183            env->canrestore++;
 184            cpu_set_cwp(env, cwp);
 185        }
 186    }
 187}
 188
 189void helper_restore(CPUSPARCState *env)
 190{
 191    uint32_t cwp;
 192
 193    cwp = cpu_cwp_inc(env, env->cwp + 1);
 194    if (env->canrestore == 0) {
 195        helper_raise_exception(env, TT_FILL | (env->otherwin != 0 ?
 196                                               (TT_WOTHER |
 197                                                ((env->wstate & 0x38) >> 1)) :
 198                                               ((env->wstate & 0x7) << 2)));
 199    } else {
 200        env->cansave++;
 201        env->canrestore--;
 202        cpu_set_cwp(env, cwp);
 203    }
 204}
 205
 206void helper_flushw(CPUSPARCState *env)
 207{
 208    if (env->cansave != env->nwindows - 2) {
 209        helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ?
 210                                                (TT_WOTHER |
 211                                                 ((env->wstate & 0x38) >> 1)) :
 212                                                ((env->wstate & 0x7) << 2)));
 213    }
 214}
 215
 216void helper_saved(CPUSPARCState *env)
 217{
 218    env->cansave++;
 219    if (env->otherwin == 0) {
 220        env->canrestore--;
 221    } else {
 222        env->otherwin--;
 223    }
 224}
 225
 226void helper_restored(CPUSPARCState *env)
 227{
 228    env->canrestore++;
 229    if (env->cleanwin < env->nwindows - 1) {
 230        env->cleanwin++;
 231    }
 232    if (env->otherwin == 0) {
 233        env->cansave--;
 234    } else {
 235        env->otherwin--;
 236    }
 237}
 238
 239target_ulong cpu_get_ccr(CPUSPARCState *env)
 240{
 241    target_ulong psr;
 242
 243    psr = cpu_get_psr(env);
 244
 245    return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20);
 246}
 247
 248void cpu_put_ccr(CPUSPARCState *env, target_ulong val)
 249{
 250    env->xcc = (val >> 4) << 20;
 251    env->psr = (val & 0xf) << 20;
 252    CC_OP = CC_OP_FLAGS;
 253}
 254
 255target_ulong cpu_get_cwp64(CPUSPARCState *env)
 256{
 257    return env->nwindows - 1 - env->cwp;
 258}
 259
 260void cpu_put_cwp64(CPUSPARCState *env, int cwp)
 261{
 262    if (unlikely(cwp >= env->nwindows || cwp < 0)) {
 263        cwp %= env->nwindows;
 264    }
 265    cpu_set_cwp(env, env->nwindows - 1 - cwp);
 266}
 267
 268target_ulong helper_rdccr(CPUSPARCState *env)
 269{
 270    return cpu_get_ccr(env);
 271}
 272
 273void helper_wrccr(CPUSPARCState *env, target_ulong new_ccr)
 274{
 275    cpu_put_ccr(env, new_ccr);
 276}
 277
 278/* CWP handling is reversed in V9, but we still use the V8 register
 279   order. */
 280target_ulong helper_rdcwp(CPUSPARCState *env)
 281{
 282    return cpu_get_cwp64(env);
 283}
 284
 285void helper_wrcwp(CPUSPARCState *env, target_ulong new_cwp)
 286{
 287    cpu_put_cwp64(env, new_cwp);
 288}
 289
 290static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate)
 291{
 292    switch (pstate) {
 293    default:
 294        trace_win_helper_gregset_error(pstate);
 295        /* pass through to normal set of global registers */
 296    case 0:
 297        return env->bgregs;
 298    case PS_AG:
 299        return env->agregs;
 300    case PS_MG:
 301        return env->mgregs;
 302    case PS_IG:
 303        return env->igregs;
 304    }
 305}
 306
 307void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
 308{
 309    uint32_t pstate_regs, new_pstate_regs;
 310    uint64_t *src, *dst;
 311
 312    if (env->def->features & CPU_FEATURE_GL) {
 313        /* PS_AG is not implemented in this case */
 314        new_pstate &= ~PS_AG;
 315    }
 316
 317    pstate_regs = env->pstate & 0xc01;
 318    new_pstate_regs = new_pstate & 0xc01;
 319
 320    if (new_pstate_regs != pstate_regs) {
 321        trace_win_helper_switch_pstate(pstate_regs, new_pstate_regs);
 322
 323        /* Switch global register bank */
 324        src = get_gregset(env, new_pstate_regs);
 325        dst = get_gregset(env, pstate_regs);
 326        memcpy32(dst, env->gregs);
 327        memcpy32(env->gregs, src);
 328    } else {
 329        trace_win_helper_no_switch_pstate(new_pstate_regs);
 330    }
 331    env->pstate = new_pstate;
 332}
 333
 334void helper_wrpstate(CPUSPARCState *env, target_ulong new_state)
 335{
 336    cpu_change_pstate(env, new_state & 0xf3f);
 337
 338#if !defined(CONFIG_USER_ONLY)
 339    if (cpu_interrupts_enabled(env)) {
 340        cpu_check_irqs(env);
 341    }
 342#endif
 343}
 344
 345void helper_wrpil(CPUSPARCState *env, target_ulong new_pil)
 346{
 347#if !defined(CONFIG_USER_ONLY)
 348    trace_win_helper_wrpil(env->psrpil, (uint32_t)new_pil);
 349
 350    env->psrpil = new_pil;
 351
 352    if (cpu_interrupts_enabled(env)) {
 353        cpu_check_irqs(env);
 354    }
 355#endif
 356}
 357
 358void helper_done(CPUSPARCState *env)
 359{
 360    trap_state *tsptr = cpu_tsptr(env);
 361
 362    env->pc = tsptr->tnpc;
 363    env->npc = tsptr->tnpc + 4;
 364    cpu_put_ccr(env, tsptr->tstate >> 32);
 365    env->asi = (tsptr->tstate >> 24) & 0xff;
 366    cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
 367    cpu_put_cwp64(env, tsptr->tstate & 0xff);
 368    env->tl--;
 369
 370    trace_win_helper_done(env->tl);
 371
 372#if !defined(CONFIG_USER_ONLY)
 373    if (cpu_interrupts_enabled(env)) {
 374        cpu_check_irqs(env);
 375    }
 376#endif
 377}
 378
 379void helper_retry(CPUSPARCState *env)
 380{
 381    trap_state *tsptr = cpu_tsptr(env);
 382
 383    env->pc = tsptr->tpc;
 384    env->npc = tsptr->tnpc;
 385    cpu_put_ccr(env, tsptr->tstate >> 32);
 386    env->asi = (tsptr->tstate >> 24) & 0xff;
 387    cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
 388    cpu_put_cwp64(env, tsptr->tstate & 0xff);
 389    env->tl--;
 390
 391    trace_win_helper_retry(env->tl);
 392
 393#if !defined(CONFIG_USER_ONLY)
 394    if (cpu_interrupts_enabled(env)) {
 395        cpu_check_irqs(env);
 396    }
 397#endif
 398}
 399#endif
 400