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24#ifndef TCG_TARGET_I386
25#define TCG_TARGET_I386 1
26
27#define TCG_TARGET_INSN_UNIT_SIZE 1
28#define TCG_TARGET_TLB_DISPLACEMENT_BITS 31
29
30#ifdef __x86_64__
31# define TCG_TARGET_REG_BITS 64
32# define TCG_TARGET_NB_REGS 16
33#else
34# define TCG_TARGET_REG_BITS 32
35# define TCG_TARGET_NB_REGS 8
36#endif
37
38typedef enum {
39 TCG_REG_EAX = 0,
40 TCG_REG_ECX,
41 TCG_REG_EDX,
42 TCG_REG_EBX,
43 TCG_REG_ESP,
44 TCG_REG_EBP,
45 TCG_REG_ESI,
46 TCG_REG_EDI,
47
48
49
50 TCG_REG_R8,
51 TCG_REG_R9,
52 TCG_REG_R10,
53 TCG_REG_R11,
54 TCG_REG_R12,
55 TCG_REG_R13,
56 TCG_REG_R14,
57 TCG_REG_R15,
58 TCG_REG_RAX = TCG_REG_EAX,
59 TCG_REG_RCX = TCG_REG_ECX,
60 TCG_REG_RDX = TCG_REG_EDX,
61 TCG_REG_RBX = TCG_REG_EBX,
62 TCG_REG_RSP = TCG_REG_ESP,
63 TCG_REG_RBP = TCG_REG_EBP,
64 TCG_REG_RSI = TCG_REG_ESI,
65 TCG_REG_RDI = TCG_REG_EDI,
66} TCGReg;
67
68
69#define TCG_REG_CALL_STACK TCG_REG_ESP
70#define TCG_TARGET_STACK_ALIGN 16
71#if defined(_WIN64)
72#define TCG_TARGET_CALL_STACK_OFFSET 32
73#else
74#define TCG_TARGET_CALL_STACK_OFFSET 0
75#endif
76
77extern bool have_bmi1;
78
79
80#define TCG_TARGET_HAS_div2_i32 1
81#define TCG_TARGET_HAS_rot_i32 1
82#define TCG_TARGET_HAS_ext8s_i32 1
83#define TCG_TARGET_HAS_ext16s_i32 1
84#define TCG_TARGET_HAS_ext8u_i32 1
85#define TCG_TARGET_HAS_ext16u_i32 1
86#define TCG_TARGET_HAS_bswap16_i32 1
87#define TCG_TARGET_HAS_bswap32_i32 1
88#define TCG_TARGET_HAS_neg_i32 1
89#define TCG_TARGET_HAS_not_i32 1
90#define TCG_TARGET_HAS_andc_i32 have_bmi1
91#define TCG_TARGET_HAS_orc_i32 0
92#define TCG_TARGET_HAS_eqv_i32 0
93#define TCG_TARGET_HAS_nand_i32 0
94#define TCG_TARGET_HAS_nor_i32 0
95#define TCG_TARGET_HAS_deposit_i32 1
96#define TCG_TARGET_HAS_movcond_i32 1
97#define TCG_TARGET_HAS_add2_i32 1
98#define TCG_TARGET_HAS_sub2_i32 1
99#define TCG_TARGET_HAS_mulu2_i32 1
100#define TCG_TARGET_HAS_muls2_i32 1
101#define TCG_TARGET_HAS_muluh_i32 0
102#define TCG_TARGET_HAS_mulsh_i32 0
103
104#if TCG_TARGET_REG_BITS == 64
105#define TCG_TARGET_HAS_extrl_i64_i32 0
106#define TCG_TARGET_HAS_extrh_i64_i32 0
107#define TCG_TARGET_HAS_div2_i64 1
108#define TCG_TARGET_HAS_rot_i64 1
109#define TCG_TARGET_HAS_ext8s_i64 1
110#define TCG_TARGET_HAS_ext16s_i64 1
111#define TCG_TARGET_HAS_ext32s_i64 1
112#define TCG_TARGET_HAS_ext8u_i64 1
113#define TCG_TARGET_HAS_ext16u_i64 1
114#define TCG_TARGET_HAS_ext32u_i64 1
115#define TCG_TARGET_HAS_bswap16_i64 1
116#define TCG_TARGET_HAS_bswap32_i64 1
117#define TCG_TARGET_HAS_bswap64_i64 1
118#define TCG_TARGET_HAS_neg_i64 1
119#define TCG_TARGET_HAS_not_i64 1
120#define TCG_TARGET_HAS_andc_i64 have_bmi1
121#define TCG_TARGET_HAS_orc_i64 0
122#define TCG_TARGET_HAS_eqv_i64 0
123#define TCG_TARGET_HAS_nand_i64 0
124#define TCG_TARGET_HAS_nor_i64 0
125#define TCG_TARGET_HAS_deposit_i64 1
126#define TCG_TARGET_HAS_movcond_i64 1
127#define TCG_TARGET_HAS_add2_i64 1
128#define TCG_TARGET_HAS_sub2_i64 1
129#define TCG_TARGET_HAS_mulu2_i64 1
130#define TCG_TARGET_HAS_muls2_i64 1
131#define TCG_TARGET_HAS_muluh_i64 0
132#define TCG_TARGET_HAS_mulsh_i64 0
133#endif
134
135#define TCG_TARGET_deposit_i32_valid(ofs, len) \
136 (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
137 ((ofs) == 0 && (len) == 16))
138#define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid
139
140#if TCG_TARGET_REG_BITS == 64
141# define TCG_AREG0 TCG_REG_R14
142#else
143# define TCG_AREG0 TCG_REG_EBP
144#endif
145
146static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
147{
148}
149
150#endif
151