LXR qemu/tcg/tci/tcg-target.h

   1/*
   2 * Tiny Code Generator for QEMU
   3 *
   4 * Copyright (c) 2009, 2011 Stefan Weil
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25/*
  26 * This code implements a TCG which does not generate machine code for some
  27 * real target machine but which generates virtual machine code for an
  28 * interpreter. Interpreted pseudo code is slow, but it works on any host.
  29 *
  30 * Some remarks might help in understanding the code:
  31 *
  32 * "target" or "TCG target" is the machine which runs the generated code.
  33 * This is different to the usual meaning in QEMU where "target" is the
  34 * emulated machine. So normally QEMU host is identical to TCG target.
  35 * Here the TCG target is a virtual machine, but this virtual machine must
  36 * use the same word size like the real machine.
  37 * Therefore, we need both 32 and 64 bit virtual machines (interpreter).
  38 */
  39
  40#if !defined(TCG_TARGET_H)
  41#define TCG_TARGET_H
  42
  43
  44#define TCG_TARGET_INTERPRETER 1
  45#define TCG_TARGET_INSN_UNIT_SIZE 1
  46#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32
  47
  48#if UINTPTR_MAX == UINT32_MAX
  49# define TCG_TARGET_REG_BITS 32
  50#elif UINTPTR_MAX == UINT64_MAX
  51# define TCG_TARGET_REG_BITS 64
  52#else
  53# error Unknown pointer size for tci target
  54#endif
  55
  56#ifdef CONFIG_DEBUG_TCG
  57/* Enable debug output. */
  58#define CONFIG_DEBUG_TCG_INTERPRETER
  59#endif
  60
  61/* Optional instructions. */
  62
  63#define TCG_TARGET_HAS_bswap16_i32      1
  64#define TCG_TARGET_HAS_bswap32_i32      1
  65#define TCG_TARGET_HAS_div_i32          1
  66#define TCG_TARGET_HAS_rem_i32          1
  67#define TCG_TARGET_HAS_ext8s_i32        1
  68#define TCG_TARGET_HAS_ext16s_i32       1
  69#define TCG_TARGET_HAS_ext8u_i32        1
  70#define TCG_TARGET_HAS_ext16u_i32       1
  71#define TCG_TARGET_HAS_andc_i32         0
  72#define TCG_TARGET_HAS_deposit_i32      1
  73#define TCG_TARGET_HAS_eqv_i32          0
  74#define TCG_TARGET_HAS_nand_i32         0
  75#define TCG_TARGET_HAS_nor_i32          0
  76#define TCG_TARGET_HAS_neg_i32          1
  77#define TCG_TARGET_HAS_not_i32          1
  78#define TCG_TARGET_HAS_orc_i32          0
  79#define TCG_TARGET_HAS_rot_i32          1
  80#define TCG_TARGET_HAS_movcond_i32      0
  81#define TCG_TARGET_HAS_muls2_i32        0
  82#define TCG_TARGET_HAS_muluh_i32        0
  83#define TCG_TARGET_HAS_mulsh_i32        0
  84
  85#if TCG_TARGET_REG_BITS == 64
  86#define TCG_TARGET_HAS_extrl_i64_i32    0
  87#define TCG_TARGET_HAS_extrh_i64_i32    0
  88#define TCG_TARGET_HAS_bswap16_i64      1
  89#define TCG_TARGET_HAS_bswap32_i64      1
  90#define TCG_TARGET_HAS_bswap64_i64      1
  91#define TCG_TARGET_HAS_deposit_i64      1
  92#define TCG_TARGET_HAS_div_i64          0
  93#define TCG_TARGET_HAS_rem_i64          0
  94#define TCG_TARGET_HAS_ext8s_i64        1
  95#define TCG_TARGET_HAS_ext16s_i64       1
  96#define TCG_TARGET_HAS_ext32s_i64       1
  97#define TCG_TARGET_HAS_ext8u_i64        1
  98#define TCG_TARGET_HAS_ext16u_i64       1
  99#define TCG_TARGET_HAS_ext32u_i64       1
 100#define TCG_TARGET_HAS_andc_i64         0
 101#define TCG_TARGET_HAS_eqv_i64          0
 102#define TCG_TARGET_HAS_nand_i64         0
 103#define TCG_TARGET_HAS_nor_i64          0
 104#define TCG_TARGET_HAS_neg_i64          1
 105#define TCG_TARGET_HAS_not_i64          1
 106#define TCG_TARGET_HAS_orc_i64          0
 107#define TCG_TARGET_HAS_rot_i64          1
 108#define TCG_TARGET_HAS_movcond_i64      0
 109#define TCG_TARGET_HAS_muls2_i64        0
 110#define TCG_TARGET_HAS_add2_i32         0
 111#define TCG_TARGET_HAS_sub2_i32         0
 112#define TCG_TARGET_HAS_mulu2_i32        0
 113#define TCG_TARGET_HAS_add2_i64         0
 114#define TCG_TARGET_HAS_sub2_i64         0
 115#define TCG_TARGET_HAS_mulu2_i64        0
 116#define TCG_TARGET_HAS_muluh_i64        0
 117#define TCG_TARGET_HAS_mulsh_i64        0
 118#else
 119#define TCG_TARGET_HAS_mulu2_i32        1
 120#endif /* TCG_TARGET_REG_BITS == 64 */
 121
 122/* Number of registers available.
 123   For 32 bit hosts, we need more than 8 registers (call arguments). */
 124/* #define TCG_TARGET_NB_REGS 8 */
 125#define TCG_TARGET_NB_REGS 16
 126/* #define TCG_TARGET_NB_REGS 32 */
 127
 128/* List of registers which are used by TCG. */
 129typedef enum {
 130    TCG_REG_R0 = 0,
 131    TCG_REG_R1,
 132    TCG_REG_R2,
 133    TCG_REG_R3,
 134    TCG_REG_R4,
 135    TCG_REG_R5,
 136    TCG_REG_R6,
 137    TCG_REG_R7,
 138#if TCG_TARGET_NB_REGS >= 16
 139    TCG_REG_R8,
 140    TCG_REG_R9,
 141    TCG_REG_R10,
 142    TCG_REG_R11,
 143    TCG_REG_R12,
 144    TCG_REG_R13,
 145    TCG_REG_R14,
 146    TCG_REG_R15,
 147#if TCG_TARGET_NB_REGS >= 32
 148    TCG_REG_R16,
 149    TCG_REG_R17,
 150    TCG_REG_R18,
 151    TCG_REG_R19,
 152    TCG_REG_R20,
 153    TCG_REG_R21,
 154    TCG_REG_R22,
 155    TCG_REG_R23,
 156    TCG_REG_R24,
 157    TCG_REG_R25,
 158    TCG_REG_R26,
 159    TCG_REG_R27,
 160    TCG_REG_R28,
 161    TCG_REG_R29,
 162    TCG_REG_R30,
 163    TCG_REG_R31,
 164#endif
 165#endif
 166    /* Special value UINT8_MAX is used by TCI to encode constant values. */
 167    TCG_CONST = UINT8_MAX
 168} TCGReg;
 169
 170#define TCG_AREG0                       (TCG_TARGET_NB_REGS - 2)
 171
 172/* Used for function call generation. */
 173#define TCG_REG_CALL_STACK              (TCG_TARGET_NB_REGS - 1)
 174#define TCG_TARGET_CALL_STACK_OFFSET    0
 175#define TCG_TARGET_STACK_ALIGN          16
 176
 177void tci_disas(uint8_t opc);
 178
 179#define HAVE_TCG_QEMU_TB_EXEC
 180
 181static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 182{
 183}
 184
 185#endif /* TCG_TARGET_H */
 186