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27#include "qemu/osdep.h"
28#include "hw/acpi/pcihp.h"
29
30#include "hw/hw.h"
31#include "hw/i386/pc.h"
32#include "hw/pci/pci.h"
33#include "hw/acpi/acpi.h"
34#include "sysemu/sysemu.h"
35#include "exec/ioport.h"
36#include "exec/address-spaces.h"
37#include "hw/pci/pci_bus.h"
38#include "qapi/error.h"
39#include "qom/qom-qobject.h"
40#include "qapi/qmp/qint.h"
41
42
43
44#ifdef DEBUG
45# define ACPI_PCIHP_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
46#else
47# define ACPI_PCIHP_DPRINTF(format, ...) do { } while (0)
48#endif
49
50#define ACPI_PCIHP_ADDR 0xae00
51#define ACPI_PCIHP_SIZE 0x0014
52#define ACPI_PCIHP_LEGACY_SIZE 0x000f
53#define PCI_UP_BASE 0x0000
54#define PCI_DOWN_BASE 0x0004
55#define PCI_EJ_BASE 0x0008
56#define PCI_RMV_BASE 0x000c
57#define PCI_SEL_BASE 0x0010
58
59typedef struct AcpiPciHpFind {
60 int bsel;
61 PCIBus *bus;
62} AcpiPciHpFind;
63
64static int acpi_pcihp_get_bsel(PCIBus *bus)
65{
66 Error *local_err = NULL;
67 int64_t bsel = object_property_get_int(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
68 &local_err);
69
70 if (local_err || bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
71 if (local_err) {
72 error_free(local_err);
73 }
74 return -1;
75 } else {
76 return bsel;
77 }
78}
79
80static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque)
81{
82 AcpiPciHpFind *find = opaque;
83 if (find->bsel == acpi_pcihp_get_bsel(bus)) {
84 find->bus = bus;
85 }
86}
87
88static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel)
89{
90 AcpiPciHpFind find = { .bsel = bsel, .bus = NULL };
91
92 if (bsel < 0) {
93 return NULL;
94 }
95
96 pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find);
97
98
99
100
101
102 if (!bsel && !find.bus) {
103 find.bus = s->root;
104 }
105 return find.bus;
106}
107
108static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev)
109{
110 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
111 DeviceClass *dc = DEVICE_GET_CLASS(dev);
112
113
114
115
116
117 return (pc->is_bridge && !dev->qdev.hotplugged) || !dc->hotpluggable;
118}
119
120static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots)
121{
122 BusChild *kid, *next;
123 int slot = ctz32(slots);
124 PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
125
126 if (!bus) {
127 return;
128 }
129
130
131 s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot);
132 s->acpi_pcihp_pci_status[bsel].up &= ~(1U << slot);
133
134 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
135 DeviceState *qdev = kid->child;
136 PCIDevice *dev = PCI_DEVICE(qdev);
137 if (PCI_SLOT(dev->devfn) == slot) {
138 if (!acpi_pcihp_pc_no_hotplug(s, dev)) {
139 object_unparent(OBJECT(qdev));
140 }
141 }
142 }
143}
144
145static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel)
146{
147 BusChild *kid, *next;
148 PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
149
150
151 while (s->acpi_pcihp_pci_status[bsel].down) {
152 acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down);
153 }
154
155 s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0;
156
157 if (!bus) {
158 return;
159 }
160 QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
161 DeviceState *qdev = kid->child;
162 PCIDevice *pdev = PCI_DEVICE(qdev);
163 int slot = PCI_SLOT(pdev->devfn);
164
165 if (acpi_pcihp_pc_no_hotplug(s, pdev)) {
166 s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot);
167 }
168 }
169}
170
171static void acpi_pcihp_update(AcpiPciHpState *s)
172{
173 int i;
174
175 for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) {
176 acpi_pcihp_update_hotplug_bus(s, i);
177 }
178}
179
180void acpi_pcihp_reset(AcpiPciHpState *s)
181{
182 acpi_pcihp_update(s);
183}
184
185void acpi_pcihp_device_plug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
186 DeviceState *dev, Error **errp)
187{
188 PCIDevice *pdev = PCI_DEVICE(dev);
189 int slot = PCI_SLOT(pdev->devfn);
190 int bsel = acpi_pcihp_get_bsel(pdev->bus);
191 if (bsel < 0) {
192 error_setg(errp, "Unsupported bus. Bus doesn't have property '"
193 ACPI_PCIHP_PROP_BSEL "' set");
194 return;
195 }
196
197
198
199
200 if (!dev->hotplugged) {
201 return;
202 }
203
204 s->acpi_pcihp_pci_status[bsel].up |= (1U << slot);
205 acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS);
206}
207
208void acpi_pcihp_device_unplug_cb(HotplugHandler *hotplug_dev, AcpiPciHpState *s,
209 DeviceState *dev, Error **errp)
210{
211 PCIDevice *pdev = PCI_DEVICE(dev);
212 int slot = PCI_SLOT(pdev->devfn);
213 int bsel = acpi_pcihp_get_bsel(pdev->bus);
214 if (bsel < 0) {
215 error_setg(errp, "Unsupported bus. Bus doesn't have property '"
216 ACPI_PCIHP_PROP_BSEL "' set");
217 return;
218 }
219
220 s->acpi_pcihp_pci_status[bsel].down |= (1U << slot);
221 acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS);
222}
223
224static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
225{
226 AcpiPciHpState *s = opaque;
227 uint32_t val = 0;
228 int bsel = s->hotplug_select;
229
230 if (bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
231 return 0;
232 }
233
234 switch (addr) {
235 case PCI_UP_BASE:
236 val = s->acpi_pcihp_pci_status[bsel].up;
237 if (!s->legacy_piix) {
238 s->acpi_pcihp_pci_status[bsel].up = 0;
239 }
240 ACPI_PCIHP_DPRINTF("pci_up_read %" PRIu32 "\n", val);
241 break;
242 case PCI_DOWN_BASE:
243 val = s->acpi_pcihp_pci_status[bsel].down;
244 ACPI_PCIHP_DPRINTF("pci_down_read %" PRIu32 "\n", val);
245 break;
246 case PCI_EJ_BASE:
247
248 ACPI_PCIHP_DPRINTF("pci_features_read %" PRIu32 "\n", val);
249 break;
250 case PCI_RMV_BASE:
251 val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
252 ACPI_PCIHP_DPRINTF("pci_rmv_read %" PRIu32 "\n", val);
253 break;
254 case PCI_SEL_BASE:
255 val = s->hotplug_select;
256 ACPI_PCIHP_DPRINTF("pci_sel_read %" PRIu32 "\n", val);
257 default:
258 break;
259 }
260
261 return val;
262}
263
264static void pci_write(void *opaque, hwaddr addr, uint64_t data,
265 unsigned int size)
266{
267 AcpiPciHpState *s = opaque;
268 switch (addr) {
269 case PCI_EJ_BASE:
270 if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
271 break;
272 }
273 acpi_pcihp_eject_slot(s, s->hotplug_select, data);
274 ACPI_PCIHP_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
275 addr, data);
276 break;
277 case PCI_SEL_BASE:
278 s->hotplug_select = data;
279 ACPI_PCIHP_DPRINTF("pcisel write %" HWADDR_PRIx " <== %" PRIu64 "\n",
280 addr, data);
281 default:
282 break;
283 }
284}
285
286static const MemoryRegionOps acpi_pcihp_io_ops = {
287 .read = pci_read,
288 .write = pci_write,
289 .endianness = DEVICE_LITTLE_ENDIAN,
290 .valid = {
291 .min_access_size = 4,
292 .max_access_size = 4,
293 },
294};
295
296void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
297 MemoryRegion *address_space_io, bool bridges_enabled)
298{
299 s->io_len = ACPI_PCIHP_SIZE;
300 s->io_base = ACPI_PCIHP_ADDR;
301
302 s->root= root_bus;
303 s->legacy_piix = !bridges_enabled;
304
305 if (s->legacy_piix) {
306 unsigned *bus_bsel = g_malloc(sizeof *bus_bsel);
307
308 s->io_len = ACPI_PCIHP_LEGACY_SIZE;
309
310 *bus_bsel = ACPI_PCIHP_BSEL_DEFAULT;
311 object_property_add_uint32_ptr(OBJECT(root_bus), ACPI_PCIHP_PROP_BSEL,
312 bus_bsel, NULL);
313 }
314
315 memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
316 "acpi-pci-hotplug", s->io_len);
317 memory_region_add_subregion(address_space_io, s->io_base, &s->io);
318
319 object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_BASE_PROP, &s->io_base,
320 &error_abort);
321 object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_LEN_PROP, &s->io_len,
322 &error_abort);
323}
324
325const VMStateDescription vmstate_acpi_pcihp_pci_status = {
326 .name = "acpi_pcihp_pci_status",
327 .version_id = 1,
328 .minimum_version_id = 1,
329 .fields = (VMStateField[]) {
330 VMSTATE_UINT32(up, AcpiPciHpPciStatus),
331 VMSTATE_UINT32(down, AcpiPciHpPciStatus),
332 VMSTATE_END_OF_LIST()
333 }
334};
335