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18#include "qemu/osdep.h"
19#include "qapi/error.h"
20#include "qemu-common.h"
21#include "cpu.h"
22#include "hw/sysbus.h"
23#include "hw/devices.h"
24#include "hw/arm/allwinner-a10.h"
25
26static void aw_a10_init(Object *obj)
27{
28 AwA10State *s = AW_A10(obj);
29
30 object_initialize(&s->cpu, sizeof(s->cpu), "cortex-a8-" TYPE_ARM_CPU);
31 object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
32
33 object_initialize(&s->intc, sizeof(s->intc), TYPE_AW_A10_PIC);
34 qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default());
35
36 object_initialize(&s->timer, sizeof(s->timer), TYPE_AW_A10_PIT);
37 qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
38
39 object_initialize(&s->emac, sizeof(s->emac), TYPE_AW_EMAC);
40 qdev_set_parent_bus(DEVICE(&s->emac), sysbus_get_default());
41
42 if (nd_table[0].used) {
43 qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
44 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
45 }
46
47 object_initialize(&s->sata, sizeof(s->sata), TYPE_ALLWINNER_AHCI);
48 qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
49}
50
51static void aw_a10_realize(DeviceState *dev, Error **errp)
52{
53 AwA10State *s = AW_A10(dev);
54 SysBusDevice *sysbusdev;
55 uint8_t i;
56 qemu_irq fiq, irq;
57 Error *err = NULL;
58
59 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
60 if (err != NULL) {
61 error_propagate(errp, err);
62 return;
63 }
64 irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
65 fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
66
67 object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
68 if (err != NULL) {
69 error_propagate(errp, err);
70 return;
71 }
72 sysbusdev = SYS_BUS_DEVICE(&s->intc);
73 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
74 sysbus_connect_irq(sysbusdev, 0, irq);
75 sysbus_connect_irq(sysbusdev, 1, fiq);
76 for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
77 s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
78 }
79
80 object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
81 if (err != NULL) {
82 error_propagate(errp, err);
83 return;
84 }
85 sysbusdev = SYS_BUS_DEVICE(&s->timer);
86 sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
87 sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
88 sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
89 sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
90 sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
91 sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
92 sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
93
94 object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
95 if (err != NULL) {
96 error_propagate(errp, err);
97 return;
98 }
99 sysbusdev = SYS_BUS_DEVICE(&s->emac);
100 sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
101 sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
102
103 object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
104 if (err) {
105 error_propagate(errp, err);
106 return;
107 }
108 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
109 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
110
111
112 serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
113 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
114}
115
116static void aw_a10_class_init(ObjectClass *oc, void *data)
117{
118 DeviceClass *dc = DEVICE_CLASS(oc);
119
120 dc->realize = aw_a10_realize;
121
122
123
124
125
126 dc->cannot_destroy_with_object_finalize_yet = true;
127}
128
129static const TypeInfo aw_a10_type_info = {
130 .name = TYPE_AW_A10,
131 .parent = TYPE_DEVICE,
132 .instance_size = sizeof(AwA10State),
133 .instance_init = aw_a10_init,
134 .class_init = aw_a10_class_init,
135};
136
137static void aw_a10_register_types(void)
138{
139 type_register_static(&aw_a10_type_info);
140}
141
142type_init(aw_a10_register_types)
143