1
2
3
4
5
6
7
8
9
10#include "qemu/osdep.h"
11#include "qapi/error.h"
12#include "hw/hw.h"
13#include "hw/arm/arm.h"
14#include "hw/arm/linux-boot-if.h"
15#include "sysemu/kvm.h"
16#include "sysemu/sysemu.h"
17#include "sysemu/numa.h"
18#include "hw/boards.h"
19#include "hw/loader.h"
20#include "elf.h"
21#include "sysemu/device_tree.h"
22#include "qemu/config-file.h"
23#include "exec/address-spaces.h"
24
25
26
27
28
29#define KERNEL_ARGS_ADDR 0x100
30#define KERNEL_LOAD_ADDR 0x00010000
31#define KERNEL64_LOAD_ADDR 0x00080000
32
33typedef enum {
34 FIXUP_NONE = 0,
35 FIXUP_TERMINATOR,
36 FIXUP_BOARDID,
37 FIXUP_BOARD_SETUP,
38 FIXUP_ARGPTR,
39 FIXUP_ENTRYPOINT,
40 FIXUP_GIC_CPU_IF,
41 FIXUP_BOOTREG,
42 FIXUP_DSB,
43 FIXUP_MAX,
44} FixupType;
45
46typedef struct ARMInsnFixup {
47 uint32_t insn;
48 FixupType fixup;
49} ARMInsnFixup;
50
51static const ARMInsnFixup bootloader_aarch64[] = {
52 { 0x580000c0 },
53 { 0xaa1f03e1 },
54 { 0xaa1f03e2 },
55 { 0xaa1f03e3 },
56 { 0x58000084 },
57 { 0xd61f0080 },
58 { 0, FIXUP_ARGPTR },
59 { 0 },
60 { 0, FIXUP_ENTRYPOINT },
61 { 0 },
62 { 0, FIXUP_TERMINATOR }
63};
64
65
66
67
68
69
70
71static const ARMInsnFixup bootloader[] = {
72 { 0xe28fe004 },
73 { 0xe51ff004 },
74 { 0, FIXUP_BOARD_SETUP },
75#define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3
76 { 0xe3a00000 },
77 { 0xe59f1004 },
78 { 0xe59f2004 },
79 { 0xe59ff004 },
80 { 0, FIXUP_BOARDID },
81 { 0, FIXUP_ARGPTR },
82 { 0, FIXUP_ENTRYPOINT },
83 { 0, FIXUP_TERMINATOR }
84};
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100#define DSB_INSN 0xf57ff04f
101#define CP15_DSB_INSN 0xee070f9a
102
103static const ARMInsnFixup smpboot[] = {
104 { 0xe59f2028 },
105 { 0xe59f0028 },
106 { 0xe3a01001 },
107 { 0xe5821000 },
108 { 0xe3a010ff },
109 { 0xe5821004 },
110 { 0, FIXUP_DSB },
111 { 0xe320f003 },
112 { 0xe5901000 },
113 { 0xe1110001 },
114 { 0x0afffffb },
115 { 0xe12fff11 },
116 { 0, FIXUP_GIC_CPU_IF },
117 { 0, FIXUP_BOOTREG },
118 { 0, FIXUP_TERMINATOR }
119};
120
121static void write_bootloader(const char *name, hwaddr addr,
122 const ARMInsnFixup *insns, uint32_t *fixupcontext)
123{
124
125
126
127
128
129 int i, len;
130 uint32_t *code;
131
132 len = 0;
133 while (insns[len].fixup != FIXUP_TERMINATOR) {
134 len++;
135 }
136
137 code = g_new0(uint32_t, len);
138
139 for (i = 0; i < len; i++) {
140 uint32_t insn = insns[i].insn;
141 FixupType fixup = insns[i].fixup;
142
143 switch (fixup) {
144 case FIXUP_NONE:
145 break;
146 case FIXUP_BOARDID:
147 case FIXUP_BOARD_SETUP:
148 case FIXUP_ARGPTR:
149 case FIXUP_ENTRYPOINT:
150 case FIXUP_GIC_CPU_IF:
151 case FIXUP_BOOTREG:
152 case FIXUP_DSB:
153 insn = fixupcontext[fixup];
154 break;
155 default:
156 abort();
157 }
158 code[i] = tswap32(insn);
159 }
160
161 rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr);
162
163 g_free(code);
164}
165
166static void default_write_secondary(ARMCPU *cpu,
167 const struct arm_boot_info *info)
168{
169 uint32_t fixupcontext[FIXUP_MAX];
170
171 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr;
172 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr;
173 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
174 fixupcontext[FIXUP_DSB] = DSB_INSN;
175 } else {
176 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
177 }
178
179 write_bootloader("smpboot", info->smp_loader_start,
180 smpboot, fixupcontext);
181}
182
183void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
184 const struct arm_boot_info *info,
185 hwaddr mvbar_addr)
186{
187 int n;
188 uint32_t mvbar_blob[] = {
189
190
191
192
193 0xeafffffe,
194 0xeafffffe,
195 0xe1b0f00e,
196 0xeafffffe,
197 0xeafffffe,
198 0xeafffffe,
199 0xeafffffe,
200 0xeafffffe,
201 };
202 uint32_t board_setup_blob[] = {
203
204 0xe3a00e00 + (mvbar_addr >> 4),
205 0xee0c0f30,
206 0xee110f11,
207 0xe3800031,
208 0xee010f11,
209 0xe1a0100e,
210 0xe1600070,
211 0xe1a0f001,
212 };
213
214
215 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100);
216
217
218 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr)
219 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr));
220
221 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) {
222 mvbar_blob[n] = tswap32(mvbar_blob[n]);
223 }
224 rom_add_blob_fixed("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob),
225 mvbar_addr);
226
227 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
228 board_setup_blob[n] = tswap32(board_setup_blob[n]);
229 }
230 rom_add_blob_fixed("board-setup", board_setup_blob,
231 sizeof(board_setup_blob), info->board_setup_addr);
232}
233
234static void default_reset_secondary(ARMCPU *cpu,
235 const struct arm_boot_info *info)
236{
237 CPUState *cs = CPU(cpu);
238
239 address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr,
240 0, MEMTXATTRS_UNSPECIFIED, NULL);
241 cpu_set_pc(cs, info->smp_loader_start);
242}
243
244static inline bool have_dtb(const struct arm_boot_info *info)
245{
246 return info->dtb_filename || info->get_dtb;
247}
248
249#define WRITE_WORD(p, value) do { \
250 address_space_stl_notdirty(&address_space_memory, p, value, \
251 MEMTXATTRS_UNSPECIFIED, NULL); \
252 p += 4; \
253} while (0)
254
255static void set_kernel_args(const struct arm_boot_info *info)
256{
257 int initrd_size = info->initrd_size;
258 hwaddr base = info->loader_start;
259 hwaddr p;
260
261 p = base + KERNEL_ARGS_ADDR;
262
263 WRITE_WORD(p, 5);
264 WRITE_WORD(p, 0x54410001);
265 WRITE_WORD(p, 1);
266 WRITE_WORD(p, 0x1000);
267 WRITE_WORD(p, 0);
268
269
270 WRITE_WORD(p, 4);
271 WRITE_WORD(p, 0x54410002);
272 WRITE_WORD(p, info->ram_size);
273 WRITE_WORD(p, info->loader_start);
274 if (initrd_size) {
275
276 WRITE_WORD(p, 4);
277 WRITE_WORD(p, 0x54420005);
278 WRITE_WORD(p, info->initrd_start);
279 WRITE_WORD(p, initrd_size);
280 }
281 if (info->kernel_cmdline && *info->kernel_cmdline) {
282
283 int cmdline_size;
284
285 cmdline_size = strlen(info->kernel_cmdline);
286 cpu_physical_memory_write(p + 8, info->kernel_cmdline,
287 cmdline_size + 1);
288 cmdline_size = (cmdline_size >> 2) + 1;
289 WRITE_WORD(p, cmdline_size + 2);
290 WRITE_WORD(p, 0x54410009);
291 p += cmdline_size * 4;
292 }
293 if (info->atag_board) {
294
295 int atag_board_len;
296 uint8_t atag_board_buf[0x1000];
297
298 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
299 WRITE_WORD(p, (atag_board_len + 8) >> 2);
300 WRITE_WORD(p, 0x414f4d50);
301 cpu_physical_memory_write(p, atag_board_buf, atag_board_len);
302 p += atag_board_len;
303 }
304
305 WRITE_WORD(p, 0);
306 WRITE_WORD(p, 0);
307}
308
309static void set_kernel_args_old(const struct arm_boot_info *info)
310{
311 hwaddr p;
312 const char *s;
313 int initrd_size = info->initrd_size;
314 hwaddr base = info->loader_start;
315
316
317 p = base + KERNEL_ARGS_ADDR;
318
319 WRITE_WORD(p, 4096);
320
321 WRITE_WORD(p, info->ram_size / 4096);
322
323 WRITE_WORD(p, 0);
324#define FLAG_READONLY 1
325#define FLAG_RDLOAD 4
326#define FLAG_RDPROMPT 8
327
328 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
329
330 WRITE_WORD(p, (31 << 8) | 0);
331
332 WRITE_WORD(p, 0);
333
334 WRITE_WORD(p, 0);
335
336 WRITE_WORD(p, 0);
337
338 WRITE_WORD(p, 0);
339
340 WRITE_WORD(p, 0);
341
342
343
344
345 WRITE_WORD(p, 0);
346
347 WRITE_WORD(p, 0);
348 WRITE_WORD(p, 0);
349 WRITE_WORD(p, 0);
350 WRITE_WORD(p, 0);
351
352 WRITE_WORD(p, 0);
353
354 if (initrd_size) {
355 WRITE_WORD(p, info->initrd_start);
356 } else {
357 WRITE_WORD(p, 0);
358 }
359
360 WRITE_WORD(p, initrd_size);
361
362 WRITE_WORD(p, 0);
363
364 WRITE_WORD(p, 0);
365
366 WRITE_WORD(p, 0);
367
368 WRITE_WORD(p, 0);
369
370 WRITE_WORD(p, 0);
371
372 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
373 WRITE_WORD(p, 0);
374 }
375 s = info->kernel_cmdline;
376 if (s) {
377 cpu_physical_memory_write(p, s, strlen(s) + 1);
378 } else {
379 WRITE_WORD(p, 0);
380 }
381}
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
404 hwaddr addr_limit)
405{
406 void *fdt = NULL;
407 int size, rc;
408 uint32_t acells, scells;
409 char *nodename;
410 unsigned int i;
411 hwaddr mem_base, mem_len;
412
413 if (binfo->dtb_filename) {
414 char *filename;
415 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
416 if (!filename) {
417 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
418 goto fail;
419 }
420
421 fdt = load_device_tree(filename, &size);
422 if (!fdt) {
423 fprintf(stderr, "Couldn't open dtb file %s\n", filename);
424 g_free(filename);
425 goto fail;
426 }
427 g_free(filename);
428 } else {
429 fdt = binfo->get_dtb(binfo, &size);
430 if (!fdt) {
431 fprintf(stderr, "Board was unable to create a dtb blob\n");
432 goto fail;
433 }
434 }
435
436 if (addr_limit > addr && size > (addr_limit - addr)) {
437
438
439
440
441 g_free(fdt);
442 return 0;
443 }
444
445 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
446 NULL, &error_fatal);
447 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
448 NULL, &error_fatal);
449 if (acells == 0 || scells == 0) {
450 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
451 goto fail;
452 }
453
454 if (scells < 2 && binfo->ram_size >= (1ULL << 32)) {
455
456
457
458 fprintf(stderr, "qemu: dtb file not compatible with "
459 "RAM size > 4GB\n");
460 goto fail;
461 }
462
463 if (nb_numa_nodes > 0) {
464
465
466
467
468 qemu_fdt_nop_node(fdt, "/memory");
469 mem_base = binfo->loader_start;
470 for (i = 0; i < nb_numa_nodes; i++) {
471 mem_len = numa_info[i].node_mem;
472 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base);
473 qemu_fdt_add_subnode(fdt, nodename);
474 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
475 rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
476 acells, mem_base,
477 scells, mem_len);
478 if (rc < 0) {
479 fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename,
480 i);
481 goto fail;
482 }
483
484 qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i);
485 mem_base += mem_len;
486 g_free(nodename);
487 }
488 } else {
489 rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg",
490 acells, binfo->loader_start,
491 scells, binfo->ram_size);
492 if (rc < 0) {
493 fprintf(stderr, "couldn't set /memory/reg\n");
494 goto fail;
495 }
496 }
497
498 if (binfo->kernel_cmdline && *binfo->kernel_cmdline) {
499 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
500 binfo->kernel_cmdline);
501 if (rc < 0) {
502 fprintf(stderr, "couldn't set /chosen/bootargs\n");
503 goto fail;
504 }
505 }
506
507 if (binfo->initrd_size) {
508 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
509 binfo->initrd_start);
510 if (rc < 0) {
511 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
512 goto fail;
513 }
514
515 rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
516 binfo->initrd_start + binfo->initrd_size);
517 if (rc < 0) {
518 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
519 goto fail;
520 }
521 }
522
523 if (binfo->modify_dtb) {
524 binfo->modify_dtb(binfo, fdt);
525 }
526
527 qemu_fdt_dumpdtb(fdt, size);
528
529
530
531
532 rom_add_blob_fixed("dtb", fdt, size, addr);
533
534 g_free(fdt);
535
536 return size;
537
538fail:
539 g_free(fdt);
540 return -1;
541}
542
543static void do_cpu_reset(void *opaque)
544{
545 ARMCPU *cpu = opaque;
546 CPUState *cs = CPU(cpu);
547 CPUARMState *env = &cpu->env;
548 const struct arm_boot_info *info = env->boot_info;
549
550 cpu_reset(cs);
551 if (info) {
552 if (!info->is_linux) {
553 int i;
554
555 uint64_t entry = info->entry;
556
557 switch (info->endianness) {
558 case ARM_ENDIANNESS_LE:
559 env->cp15.sctlr_el[1] &= ~SCTLR_E0E;
560 for (i = 1; i < 4; ++i) {
561 env->cp15.sctlr_el[i] &= ~SCTLR_EE;
562 }
563 env->uncached_cpsr &= ~CPSR_E;
564 break;
565 case ARM_ENDIANNESS_BE8:
566 env->cp15.sctlr_el[1] |= SCTLR_E0E;
567 for (i = 1; i < 4; ++i) {
568 env->cp15.sctlr_el[i] |= SCTLR_EE;
569 }
570 env->uncached_cpsr |= CPSR_E;
571 break;
572 case ARM_ENDIANNESS_BE32:
573 env->cp15.sctlr_el[1] |= SCTLR_B;
574 break;
575 case ARM_ENDIANNESS_UNKNOWN:
576 break;
577 default:
578 g_assert_not_reached();
579 }
580
581 if (!env->aarch64) {
582 env->thumb = info->entry & 1;
583 entry &= 0xfffffffe;
584 }
585 cpu_set_pc(cs, entry);
586 } else {
587
588
589
590
591
592
593 if (arm_feature(env, ARM_FEATURE_EL3)) {
594
595
596
597
598
599
600 if (env->aarch64) {
601 env->cp15.scr_el3 |= SCR_RW;
602 if (arm_feature(env, ARM_FEATURE_EL2)) {
603 env->cp15.hcr_el2 |= HCR_RW;
604 env->pstate = PSTATE_MODE_EL2h;
605 } else {
606 env->pstate = PSTATE_MODE_EL1h;
607 }
608 }
609
610
611 if (!info->secure_boot &&
612 (cs != first_cpu || !info->secure_board_setup)) {
613
614 env->cp15.scr_el3 |= SCR_NS;
615 }
616 }
617
618 if (cs == first_cpu) {
619 cpu_set_pc(cs, info->loader_start);
620
621 if (!have_dtb(info)) {
622 if (old_param) {
623 set_kernel_args_old(info);
624 } else {
625 set_kernel_args(info);
626 }
627 }
628 } else {
629 info->secondary_cpu_reset_hook(cpu, info);
630 }
631 }
632 }
633}
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
653 uint16_t data_key, const char *image_name,
654 bool try_decompress)
655{
656 size_t size = -1;
657 uint8_t *data;
658
659 if (image_name == NULL) {
660 return;
661 }
662
663 if (try_decompress) {
664 size = load_image_gzipped_buffer(image_name,
665 LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
666 }
667
668 if (size == (size_t)-1) {
669 gchar *contents;
670 gsize length;
671
672 if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
673 fprintf(stderr, "failed to load \"%s\"\n", image_name);
674 exit(1);
675 }
676 size = length;
677 data = (uint8_t *)contents;
678 }
679
680 fw_cfg_add_i32(fw_cfg, size_key, size);
681 fw_cfg_add_bytes(fw_cfg, data_key, data, size);
682}
683
684static int do_arm_linux_init(Object *obj, void *opaque)
685{
686 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) {
687 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj);
688 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj);
689 struct arm_boot_info *info = opaque;
690
691 if (albifc->arm_linux_init) {
692 albifc->arm_linux_init(albif, info->secure_boot);
693 }
694 }
695 return 0;
696}
697
698static uint64_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
699 uint64_t *lowaddr, uint64_t *highaddr,
700 int elf_machine)
701{
702 bool elf_is64;
703 union {
704 Elf32_Ehdr h32;
705 Elf64_Ehdr h64;
706 } elf_header;
707 int data_swab = 0;
708 bool big_endian;
709 uint64_t ret = -1;
710 Error *err = NULL;
711
712
713 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err);
714 if (err) {
715 return ret;
716 }
717
718 if (elf_is64) {
719 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB;
720 info->endianness = big_endian ? ARM_ENDIANNESS_BE8
721 : ARM_ENDIANNESS_LE;
722 } else {
723 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB;
724 if (big_endian) {
725 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) {
726 info->endianness = ARM_ENDIANNESS_BE8;
727 } else {
728 info->endianness = ARM_ENDIANNESS_BE32;
729
730
731
732
733
734
735
736 data_swab = 2;
737 }
738 } else {
739 info->endianness = ARM_ENDIANNESS_LE;
740 }
741 }
742
743 ret = load_elf(info->kernel_filename, NULL, NULL,
744 pentry, lowaddr, highaddr, big_endian, elf_machine,
745 1, data_swab);
746 if (ret <= 0) {
747
748 exit(1);
749 }
750
751 return ret;
752}
753
754static void arm_load_kernel_notify(Notifier *notifier, void *data)
755{
756 CPUState *cs;
757 int kernel_size;
758 int initrd_size;
759 int is_linux = 0;
760 uint64_t elf_entry, elf_low_addr, elf_high_addr;
761 int elf_machine;
762 hwaddr entry, kernel_load_offset;
763 static const ARMInsnFixup *primary_loader;
764 ArmLoadKernelNotifier *n = DO_UPCAST(ArmLoadKernelNotifier,
765 notifier, notifier);
766 ARMCPU *cpu = n->cpu;
767 struct arm_boot_info *info =
768 container_of(n, struct arm_boot_info, load_kernel_notifier);
769
770
771
772
773
774 assert(!(info->secure_board_setup && kvm_enabled()));
775
776
777 if (!info->kernel_filename || info->firmware_loaded) {
778
779 if (have_dtb(info)) {
780
781
782
783
784 if (load_dtb(info->loader_start, info, 0) < 0) {
785 exit(1);
786 }
787 }
788
789 if (info->kernel_filename) {
790 FWCfgState *fw_cfg;
791 bool try_decompressing_kernel;
792
793 fw_cfg = fw_cfg_find();
794 try_decompressing_kernel = arm_feature(&cpu->env,
795 ARM_FEATURE_AARCH64);
796
797
798
799
800
801 load_image_to_fw_cfg(fw_cfg,
802 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
803 info->kernel_filename,
804 try_decompressing_kernel);
805 load_image_to_fw_cfg(fw_cfg,
806 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
807 info->initrd_filename, false);
808
809 if (info->kernel_cmdline) {
810 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
811 strlen(info->kernel_cmdline) + 1);
812 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
813 info->kernel_cmdline);
814 }
815 }
816
817
818
819
820 return;
821 }
822
823 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
824 primary_loader = bootloader_aarch64;
825 kernel_load_offset = KERNEL64_LOAD_ADDR;
826 elf_machine = EM_AARCH64;
827 } else {
828 primary_loader = bootloader;
829 if (!info->write_board_setup) {
830 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;
831 }
832 kernel_load_offset = KERNEL_LOAD_ADDR;
833 elf_machine = EM_ARM;
834 }
835
836 info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
837
838 if (!info->secondary_cpu_reset_hook) {
839 info->secondary_cpu_reset_hook = default_reset_secondary;
840 }
841 if (!info->write_secondary_boot) {
842 info->write_secondary_boot = default_write_secondary;
843 }
844
845 if (info->nb_cpus == 0)
846 info->nb_cpus = 1;
847
848
849
850
851
852
853
854
855
856
857
858 info->initrd_start = info->loader_start +
859 MIN(info->ram_size / 2, 128 * 1024 * 1024);
860
861
862 kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr,
863 &elf_high_addr, elf_machine);
864 if (kernel_size > 0 && have_dtb(info)) {
865
866
867
868 if (elf_low_addr > info->loader_start
869 || elf_high_addr < info->loader_start) {
870
871
872
873 if (elf_low_addr < info->loader_start) {
874 elf_low_addr = 0;
875 }
876 if (load_dtb(info->loader_start, info, elf_low_addr) < 0) {
877 exit(1);
878 }
879 }
880 }
881 entry = elf_entry;
882 if (kernel_size < 0) {
883 kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
884 &is_linux, NULL, NULL);
885 }
886
887 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
888 entry = info->loader_start + kernel_load_offset;
889 kernel_size = load_image_gzipped(info->kernel_filename, entry,
890 info->ram_size - kernel_load_offset);
891 is_linux = 1;
892 }
893 if (kernel_size < 0) {
894 entry = info->loader_start + kernel_load_offset;
895 kernel_size = load_image_targphys(info->kernel_filename, entry,
896 info->ram_size - kernel_load_offset);
897 is_linux = 1;
898 }
899 if (kernel_size < 0) {
900 fprintf(stderr, "qemu: could not load kernel '%s'\n",
901 info->kernel_filename);
902 exit(1);
903 }
904 info->entry = entry;
905 if (is_linux) {
906 uint32_t fixupcontext[FIXUP_MAX];
907
908 if (info->initrd_filename) {
909 initrd_size = load_ramdisk(info->initrd_filename,
910 info->initrd_start,
911 info->ram_size -
912 info->initrd_start);
913 if (initrd_size < 0) {
914 initrd_size = load_image_targphys(info->initrd_filename,
915 info->initrd_start,
916 info->ram_size -
917 info->initrd_start);
918 }
919 if (initrd_size < 0) {
920 fprintf(stderr, "qemu: could not load initrd '%s'\n",
921 info->initrd_filename);
922 exit(1);
923 }
924 } else {
925 initrd_size = 0;
926 }
927 info->initrd_size = initrd_size;
928
929 fixupcontext[FIXUP_BOARDID] = info->board_id;
930 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr;
931
932
933
934
935 if (have_dtb(info)) {
936 hwaddr align;
937 hwaddr dtb_start;
938
939 if (elf_machine == EM_AARCH64) {
940
941
942
943
944
945
946
947 align = 2 * 1024 * 1024;
948 } else {
949
950
951
952
953 align = 4096;
954 }
955
956
957 dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size, align);
958 if (load_dtb(dtb_start, info, 0) < 0) {
959 exit(1);
960 }
961 fixupcontext[FIXUP_ARGPTR] = dtb_start;
962 } else {
963 fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR;
964 if (info->ram_size >= (1ULL << 32)) {
965 fprintf(stderr, "qemu: RAM size must be less than 4GB to boot"
966 " Linux kernel using ATAGS (try passing a device tree"
967 " using -dtb)\n");
968 exit(1);
969 }
970 }
971 fixupcontext[FIXUP_ENTRYPOINT] = entry;
972
973 write_bootloader("bootloader", info->loader_start,
974 primary_loader, fixupcontext);
975
976 if (info->nb_cpus > 1) {
977 info->write_secondary_boot(cpu, info);
978 }
979 if (info->write_board_setup) {
980 info->write_board_setup(cpu, info);
981 }
982
983
984
985
986 object_child_foreach_recursive(object_get_root(),
987 do_arm_linux_init, info);
988 }
989 info->is_linux = is_linux;
990
991 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) {
992 ARM_CPU(cs)->env.boot_info = info;
993 }
994}
995
996void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
997{
998 CPUState *cs;
999
1000 info->load_kernel_notifier.cpu = cpu;
1001 info->load_kernel_notifier.notifier.notify = arm_load_kernel_notify;
1002 qemu_add_machine_init_done_notifier(&info->load_kernel_notifier.notifier);
1003
1004
1005
1006
1007
1008
1009 for (cs = CPU(cpu); cs; cs = CPU_NEXT(cs)) {
1010 qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
1011 }
1012}
1013
1014static const TypeInfo arm_linux_boot_if_info = {
1015 .name = TYPE_ARM_LINUX_BOOT_IF,
1016 .parent = TYPE_INTERFACE,
1017 .class_size = sizeof(ARMLinuxBootIfClass),
1018};
1019
1020static void arm_linux_boot_register_types(void)
1021{
1022 type_register_static(&arm_linux_boot_if_info);
1023}
1024
1025type_init(arm_linux_boot_register_types)
1026