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19#include "qemu/osdep.h"
20#include "hw/sysbus.h"
21#include "sysemu/char.h"
22#include "qemu/timer.h"
23#include "qemu/log.h"
24#include "hw/char/cadence_uart.h"
25
26#ifdef CADENCE_UART_ERR_DEBUG
27#define DB_PRINT(...) do { \
28 fprintf(stderr, ": %s: ", __func__); \
29 fprintf(stderr, ## __VA_ARGS__); \
30 } while (0);
31#else
32 #define DB_PRINT(...)
33#endif
34
35#define UART_SR_INTR_RTRIG 0x00000001
36#define UART_SR_INTR_REMPTY 0x00000002
37#define UART_SR_INTR_RFUL 0x00000004
38#define UART_SR_INTR_TEMPTY 0x00000008
39#define UART_SR_INTR_TFUL 0x00000010
40
41#define UART_SR_TTRIG 0x00002000
42#define UART_INTR_TTRIG 0x00000400
43
44
45#define UART_SR_TO_CISR_MASK 0x0000001F
46
47#define UART_INTR_ROVR 0x00000020
48#define UART_INTR_FRAME 0x00000040
49#define UART_INTR_PARE 0x00000080
50#define UART_INTR_TIMEOUT 0x00000100
51#define UART_INTR_DMSI 0x00000200
52#define UART_INTR_TOVR 0x00001000
53
54#define UART_SR_RACTIVE 0x00000400
55#define UART_SR_TACTIVE 0x00000800
56#define UART_SR_FDELT 0x00001000
57
58#define UART_CR_RXRST 0x00000001
59#define UART_CR_TXRST 0x00000002
60#define UART_CR_RX_EN 0x00000004
61#define UART_CR_RX_DIS 0x00000008
62#define UART_CR_TX_EN 0x00000010
63#define UART_CR_TX_DIS 0x00000020
64#define UART_CR_RST_TO 0x00000040
65#define UART_CR_STARTBRK 0x00000080
66#define UART_CR_STOPBRK 0x00000100
67
68#define UART_MR_CLKS 0x00000001
69#define UART_MR_CHRL 0x00000006
70#define UART_MR_CHRL_SH 1
71#define UART_MR_PAR 0x00000038
72#define UART_MR_PAR_SH 3
73#define UART_MR_NBSTOP 0x000000C0
74#define UART_MR_NBSTOP_SH 6
75#define UART_MR_CHMODE 0x00000300
76#define UART_MR_CHMODE_SH 8
77#define UART_MR_UCLKEN 0x00000400
78#define UART_MR_IRMODE 0x00000800
79
80#define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH)
81#define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH)
82#define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH)
83#define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH)
84#define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH)
85#define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH)
86#define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH)
87#define ECHO_MODE (0x1 << UART_MR_CHMODE_SH)
88#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
89#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
90
91#define UART_INPUT_CLK 50000000
92
93#define R_CR (0x00/4)
94#define R_MR (0x04/4)
95#define R_IER (0x08/4)
96#define R_IDR (0x0C/4)
97#define R_IMR (0x10/4)
98#define R_CISR (0x14/4)
99#define R_BRGR (0x18/4)
100#define R_RTOR (0x1C/4)
101#define R_RTRIG (0x20/4)
102#define R_MCR (0x24/4)
103#define R_MSR (0x28/4)
104#define R_SR (0x2C/4)
105#define R_TX_RX (0x30/4)
106#define R_BDIV (0x34/4)
107#define R_FDEL (0x38/4)
108#define R_PMIN (0x3C/4)
109#define R_PWID (0x40/4)
110#define R_TTRIG (0x44/4)
111
112
113static void uart_update_status(CadenceUARTState *s)
114{
115 s->r[R_SR] = 0;
116
117 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
118 : 0;
119 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
120 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
121
122 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
123 : 0;
124 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
125 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
126
127 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
128 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
129 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
130}
131
132static void fifo_trigger_update(void *opaque)
133{
134 CadenceUARTState *s = opaque;
135
136 s->r[R_CISR] |= UART_INTR_TIMEOUT;
137
138 uart_update_status(s);
139}
140
141static void uart_rx_reset(CadenceUARTState *s)
142{
143 s->rx_wpos = 0;
144 s->rx_count = 0;
145 if (s->chr) {
146 qemu_chr_accept_input(s->chr);
147 }
148}
149
150static void uart_tx_reset(CadenceUARTState *s)
151{
152 s->tx_count = 0;
153}
154
155static void uart_send_breaks(CadenceUARTState *s)
156{
157 int break_enabled = 1;
158
159 if (s->chr) {
160 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
161 &break_enabled);
162 }
163}
164
165static void uart_parameters_setup(CadenceUARTState *s)
166{
167 QEMUSerialSetParams ssp;
168 unsigned int baud_rate, packet_size;
169
170 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
171 UART_INPUT_CLK / 8 : UART_INPUT_CLK;
172
173 ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
174 packet_size = 1;
175
176 switch (s->r[R_MR] & UART_MR_PAR) {
177 case UART_PARITY_EVEN:
178 ssp.parity = 'E';
179 packet_size++;
180 break;
181 case UART_PARITY_ODD:
182 ssp.parity = 'O';
183 packet_size++;
184 break;
185 default:
186 ssp.parity = 'N';
187 break;
188 }
189
190 switch (s->r[R_MR] & UART_MR_CHRL) {
191 case UART_DATA_BITS_6:
192 ssp.data_bits = 6;
193 break;
194 case UART_DATA_BITS_7:
195 ssp.data_bits = 7;
196 break;
197 default:
198 ssp.data_bits = 8;
199 break;
200 }
201
202 switch (s->r[R_MR] & UART_MR_NBSTOP) {
203 case UART_STOP_BITS_1:
204 ssp.stop_bits = 1;
205 break;
206 default:
207 ssp.stop_bits = 2;
208 break;
209 }
210
211 packet_size += ssp.data_bits + ssp.stop_bits;
212 s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
213 if (s->chr) {
214 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
215 }
216}
217
218static int uart_can_receive(void *opaque)
219{
220 CadenceUARTState *s = opaque;
221 int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
222 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
223
224 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
225 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
226 }
227 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
228 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
229 }
230 return ret;
231}
232
233static void uart_ctrl_update(CadenceUARTState *s)
234{
235 if (s->r[R_CR] & UART_CR_TXRST) {
236 uart_tx_reset(s);
237 }
238
239 if (s->r[R_CR] & UART_CR_RXRST) {
240 uart_rx_reset(s);
241 }
242
243 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
244
245 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
246 uart_send_breaks(s);
247 }
248}
249
250static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
251{
252 CadenceUARTState *s = opaque;
253 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
254 int i;
255
256 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
257 return;
258 }
259
260 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
261 s->r[R_CISR] |= UART_INTR_ROVR;
262 } else {
263 for (i = 0; i < size; i++) {
264 s->rx_fifo[s->rx_wpos] = buf[i];
265 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
266 s->rx_count++;
267 }
268 timer_mod(s->fifo_trigger_handle, new_rx_time +
269 (s->char_tx_time * 4));
270 }
271 uart_update_status(s);
272}
273
274static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
275 void *opaque)
276{
277 CadenceUARTState *s = opaque;
278 int ret;
279
280
281 if (!s->chr) {
282 s->tx_count = 0;
283 return FALSE;
284 }
285
286 if (!s->tx_count) {
287 return FALSE;
288 }
289
290 ret = qemu_chr_fe_write(s->chr, s->tx_fifo, s->tx_count);
291
292 if (ret >= 0) {
293 s->tx_count -= ret;
294 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
295 }
296
297 if (s->tx_count) {
298 guint r = qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP,
299 cadence_uart_xmit, s);
300 if (!r) {
301 s->tx_count = 0;
302 return FALSE;
303 }
304 }
305
306 uart_update_status(s);
307 return FALSE;
308}
309
310static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
311 int size)
312{
313 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
314 return;
315 }
316
317 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
318 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
319
320
321
322
323
324 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
325 s->r[R_CISR] |= UART_INTR_ROVR;
326 }
327
328 memcpy(s->tx_fifo + s->tx_count, buf, size);
329 s->tx_count += size;
330
331 cadence_uart_xmit(NULL, G_IO_OUT, s);
332}
333
334static void uart_receive(void *opaque, const uint8_t *buf, int size)
335{
336 CadenceUARTState *s = opaque;
337 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
338
339 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
340 uart_write_rx_fifo(opaque, buf, size);
341 }
342 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
343 uart_write_tx_fifo(s, buf, size);
344 }
345}
346
347static void uart_event(void *opaque, int event)
348{
349 CadenceUARTState *s = opaque;
350 uint8_t buf = '\0';
351
352 if (event == CHR_EVENT_BREAK) {
353 uart_write_rx_fifo(opaque, &buf, 1);
354 }
355
356 uart_update_status(s);
357}
358
359static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
360{
361 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
362 return;
363 }
364
365 if (s->rx_count) {
366 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
367 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
368 *c = s->rx_fifo[rx_rpos];
369 s->rx_count--;
370
371 if (s->chr) {
372 qemu_chr_accept_input(s->chr);
373 }
374 } else {
375 *c = 0;
376 }
377
378 uart_update_status(s);
379}
380
381static void uart_write(void *opaque, hwaddr offset,
382 uint64_t value, unsigned size)
383{
384 CadenceUARTState *s = opaque;
385
386 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
387 offset >>= 2;
388 if (offset >= CADENCE_UART_R_MAX) {
389 return;
390 }
391 switch (offset) {
392 case R_IER:
393 s->r[R_IMR] |= value;
394 break;
395 case R_IDR:
396 s->r[R_IMR] &= ~value;
397 break;
398 case R_IMR:
399 break;
400 case R_CISR:
401 s->r[R_CISR] &= ~value;
402 break;
403 case R_TX_RX:
404 switch (s->r[R_MR] & UART_MR_CHMODE) {
405 case NORMAL_MODE:
406 uart_write_tx_fifo(s, (uint8_t *) &value, 1);
407 break;
408 case LOCAL_LOOPBACK:
409 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
410 break;
411 }
412 break;
413 default:
414 s->r[offset] = value;
415 }
416
417 switch (offset) {
418 case R_CR:
419 uart_ctrl_update(s);
420 break;
421 case R_MR:
422 uart_parameters_setup(s);
423 break;
424 }
425 uart_update_status(s);
426}
427
428static uint64_t uart_read(void *opaque, hwaddr offset,
429 unsigned size)
430{
431 CadenceUARTState *s = opaque;
432 uint32_t c = 0;
433
434 offset >>= 2;
435 if (offset >= CADENCE_UART_R_MAX) {
436 c = 0;
437 } else if (offset == R_TX_RX) {
438 uart_read_rx_fifo(s, &c);
439 } else {
440 c = s->r[offset];
441 }
442
443 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
444 return c;
445}
446
447static const MemoryRegionOps uart_ops = {
448 .read = uart_read,
449 .write = uart_write,
450 .endianness = DEVICE_NATIVE_ENDIAN,
451};
452
453static void cadence_uart_reset(DeviceState *dev)
454{
455 CadenceUARTState *s = CADENCE_UART(dev);
456
457 s->r[R_CR] = 0x00000128;
458 s->r[R_IMR] = 0;
459 s->r[R_CISR] = 0;
460 s->r[R_RTRIG] = 0x00000020;
461 s->r[R_BRGR] = 0x0000000F;
462 s->r[R_TTRIG] = 0x00000020;
463
464 uart_rx_reset(s);
465 uart_tx_reset(s);
466
467 uart_update_status(s);
468}
469
470static void cadence_uart_realize(DeviceState *dev, Error **errp)
471{
472 CadenceUARTState *s = CADENCE_UART(dev);
473
474 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
475 fifo_trigger_update, s);
476
477 if (s->chr) {
478 qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
479 uart_event, s);
480 }
481}
482
483static void cadence_uart_init(Object *obj)
484{
485 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
486 CadenceUARTState *s = CADENCE_UART(obj);
487
488 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
489 sysbus_init_mmio(sbd, &s->iomem);
490 sysbus_init_irq(sbd, &s->irq);
491
492 s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
493}
494
495static int cadence_uart_post_load(void *opaque, int version_id)
496{
497 CadenceUARTState *s = opaque;
498
499 uart_parameters_setup(s);
500 uart_update_status(s);
501 return 0;
502}
503
504static const VMStateDescription vmstate_cadence_uart = {
505 .name = "cadence_uart",
506 .version_id = 2,
507 .minimum_version_id = 2,
508 .post_load = cadence_uart_post_load,
509 .fields = (VMStateField[]) {
510 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
511 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
512 CADENCE_UART_RX_FIFO_SIZE),
513 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
514 CADENCE_UART_TX_FIFO_SIZE),
515 VMSTATE_UINT32(rx_count, CadenceUARTState),
516 VMSTATE_UINT32(tx_count, CadenceUARTState),
517 VMSTATE_UINT32(rx_wpos, CadenceUARTState),
518 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
519 VMSTATE_END_OF_LIST()
520 }
521};
522
523static Property cadence_uart_properties[] = {
524 DEFINE_PROP_CHR("chardev", CadenceUARTState, chr),
525 DEFINE_PROP_END_OF_LIST(),
526};
527
528static void cadence_uart_class_init(ObjectClass *klass, void *data)
529{
530 DeviceClass *dc = DEVICE_CLASS(klass);
531
532 dc->realize = cadence_uart_realize;
533 dc->vmsd = &vmstate_cadence_uart;
534 dc->reset = cadence_uart_reset;
535 dc->props = cadence_uart_properties;
536 }
537
538static const TypeInfo cadence_uart_info = {
539 .name = TYPE_CADENCE_UART,
540 .parent = TYPE_SYS_BUS_DEVICE,
541 .instance_size = sizeof(CadenceUARTState),
542 .instance_init = cadence_uart_init,
543 .class_init = cadence_uart_class_init,
544};
545
546static void cadence_uart_register_types(void)
547{
548 type_register_static(&cadence_uart_info);
549}
550
551type_init(cadence_uart_register_types)
552
