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29#include "qemu/osdep.h"
30#include "hw/hw.h"
31#include "hw/sysbus.h"
32#include "sysemu/char.h"
33#include "qemu/log.h"
34
35#include "hw/char/digic-uart.h"
36
37enum {
38 ST_RX_RDY = (1 << 0),
39 ST_TX_RDY = (1 << 1),
40};
41
42static uint64_t digic_uart_read(void *opaque, hwaddr addr,
43 unsigned size)
44{
45 DigicUartState *s = opaque;
46 uint64_t ret = 0;
47
48 addr >>= 2;
49
50 switch (addr) {
51 case R_RX:
52 s->reg_st &= ~(ST_RX_RDY);
53 ret = s->reg_rx;
54 break;
55
56 case R_ST:
57 ret = s->reg_st;
58 break;
59
60 default:
61 qemu_log_mask(LOG_UNIMP,
62 "digic-uart: read access to unknown register 0x"
63 TARGET_FMT_plx, addr << 2);
64 }
65
66 return ret;
67}
68
69static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value,
70 unsigned size)
71{
72 DigicUartState *s = opaque;
73 unsigned char ch = value;
74
75 addr >>= 2;
76
77 switch (addr) {
78 case R_TX:
79 if (s->chr) {
80 qemu_chr_fe_write_all(s->chr, &ch, 1);
81 }
82 break;
83
84 case R_ST:
85
86
87
88
89
90
91
92
93
94
95
96 break;
97
98 default:
99 qemu_log_mask(LOG_UNIMP,
100 "digic-uart: write access to unknown register 0x"
101 TARGET_FMT_plx, addr << 2);
102 }
103}
104
105static const MemoryRegionOps uart_mmio_ops = {
106 .read = digic_uart_read,
107 .write = digic_uart_write,
108 .valid = {
109 .min_access_size = 4,
110 .max_access_size = 4,
111 },
112 .endianness = DEVICE_NATIVE_ENDIAN,
113};
114
115static int uart_can_rx(void *opaque)
116{
117 DigicUartState *s = opaque;
118
119 return !(s->reg_st & ST_RX_RDY);
120}
121
122static void uart_rx(void *opaque, const uint8_t *buf, int size)
123{
124 DigicUartState *s = opaque;
125
126 assert(uart_can_rx(opaque));
127
128 s->reg_st |= ST_RX_RDY;
129 s->reg_rx = *buf;
130}
131
132static void uart_event(void *opaque, int event)
133{
134}
135
136static void digic_uart_reset(DeviceState *d)
137{
138 DigicUartState *s = DIGIC_UART(d);
139
140 s->reg_rx = 0;
141 s->reg_st = ST_TX_RDY;
142}
143
144static void digic_uart_realize(DeviceState *dev, Error **errp)
145{
146 DigicUartState *s = DIGIC_UART(dev);
147
148 if (s->chr) {
149 qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
150 }
151}
152
153static void digic_uart_init(Object *obj)
154{
155 DigicUartState *s = DIGIC_UART(obj);
156
157 memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
158 TYPE_DIGIC_UART, 0x18);
159 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->regs_region);
160}
161
162static const VMStateDescription vmstate_digic_uart = {
163 .name = "digic-uart",
164 .version_id = 1,
165 .minimum_version_id = 1,
166 .fields = (VMStateField[]) {
167 VMSTATE_UINT32(reg_rx, DigicUartState),
168 VMSTATE_UINT32(reg_st, DigicUartState),
169 VMSTATE_END_OF_LIST()
170 }
171};
172
173static Property digic_uart_properties[] = {
174 DEFINE_PROP_CHR("chardev", DigicUartState, chr),
175 DEFINE_PROP_END_OF_LIST(),
176};
177
178static void digic_uart_class_init(ObjectClass *klass, void *data)
179{
180 DeviceClass *dc = DEVICE_CLASS(klass);
181
182 dc->realize = digic_uart_realize;
183 dc->reset = digic_uart_reset;
184 dc->vmsd = &vmstate_digic_uart;
185 dc->props = digic_uart_properties;
186}
187
188static const TypeInfo digic_uart_info = {
189 .name = TYPE_DIGIC_UART,
190 .parent = TYPE_SYS_BUS_DEVICE,
191 .instance_size = sizeof(DigicUartState),
192 .instance_init = digic_uart_init,
193 .class_init = digic_uart_class_init,
194};
195
196static void digic_uart_register_types(void)
197{
198 type_register_static(&digic_uart_info);
199}
200
201type_init(digic_uart_register_types)
202