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25#include "qemu/osdep.h"
26#include "hw/sysbus.h"
27#include "sysemu/char.h"
28#include "qemu/log.h"
29
30#define D(x)
31
32#define RW_TR_CTRL (0x00 / 4)
33#define RW_TR_DMA_EN (0x04 / 4)
34#define RW_REC_CTRL (0x08 / 4)
35#define RW_DOUT (0x1c / 4)
36#define RS_STAT_DIN (0x20 / 4)
37#define R_STAT_DIN (0x24 / 4)
38#define RW_INTR_MASK (0x2c / 4)
39#define RW_ACK_INTR (0x30 / 4)
40#define R_INTR (0x34 / 4)
41#define R_MASKED_INTR (0x38 / 4)
42#define R_MAX (0x3c / 4)
43
44#define STAT_DAV 16
45#define STAT_TR_IDLE 22
46#define STAT_TR_RDY 24
47
48#define TYPE_ETRAX_FS_SERIAL "etraxfs,serial"
49#define ETRAX_SERIAL(obj) \
50 OBJECT_CHECK(ETRAXSerial, (obj), TYPE_ETRAX_FS_SERIAL)
51
52typedef struct ETRAXSerial {
53 SysBusDevice parent_obj;
54
55 MemoryRegion mmio;
56 CharDriverState *chr;
57 qemu_irq irq;
58
59 int pending_tx;
60
61 uint8_t rx_fifo[16];
62 unsigned int rx_fifo_pos;
63 unsigned int rx_fifo_len;
64
65
66 uint32_t regs[R_MAX];
67} ETRAXSerial;
68
69static void ser_update_irq(ETRAXSerial *s)
70{
71
72 if (s->rx_fifo_len) {
73 s->regs[R_INTR] |= 8;
74 } else {
75 s->regs[R_INTR] &= ~8;
76 }
77
78 s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
79 qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
80}
81
82static uint64_t
83ser_read(void *opaque, hwaddr addr, unsigned int size)
84{
85 ETRAXSerial *s = opaque;
86 uint32_t r = 0;
87
88 addr >>= 2;
89 switch (addr)
90 {
91 case R_STAT_DIN:
92 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
93 if (s->rx_fifo_len) {
94 r |= 1 << STAT_DAV;
95 }
96 r |= 1 << STAT_TR_RDY;
97 r |= 1 << STAT_TR_IDLE;
98 break;
99 case RS_STAT_DIN:
100 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
101 if (s->rx_fifo_len) {
102 r |= 1 << STAT_DAV;
103 s->rx_fifo_len--;
104 }
105 r |= 1 << STAT_TR_RDY;
106 r |= 1 << STAT_TR_IDLE;
107 break;
108 default:
109 r = s->regs[addr];
110 D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
111 break;
112 }
113 return r;
114}
115
116static void
117ser_write(void *opaque, hwaddr addr,
118 uint64_t val64, unsigned int size)
119{
120 ETRAXSerial *s = opaque;
121 uint32_t value = val64;
122 unsigned char ch = val64;
123
124 D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value));
125 addr >>= 2;
126 switch (addr)
127 {
128 case RW_DOUT:
129 qemu_chr_fe_write(s->chr, &ch, 1);
130 s->regs[R_INTR] |= 3;
131 s->pending_tx = 1;
132 s->regs[addr] = value;
133 break;
134 case RW_ACK_INTR:
135 if (s->pending_tx) {
136 value &= ~1;
137 s->pending_tx = 0;
138 D(qemu_log("fixedup value=%x r_intr=%x\n",
139 value, s->regs[R_INTR]));
140 }
141 s->regs[addr] = value;
142 s->regs[R_INTR] &= ~value;
143 D(printf("r_intr=%x\n", s->regs[R_INTR]));
144 break;
145 default:
146 s->regs[addr] = value;
147 break;
148 }
149 ser_update_irq(s);
150}
151
152static const MemoryRegionOps ser_ops = {
153 .read = ser_read,
154 .write = ser_write,
155 .endianness = DEVICE_NATIVE_ENDIAN,
156 .valid = {
157 .min_access_size = 4,
158 .max_access_size = 4
159 }
160};
161
162static Property etraxfs_ser_properties[] = {
163 DEFINE_PROP_CHR("chardev", ETRAXSerial, chr),
164 DEFINE_PROP_END_OF_LIST(),
165};
166
167static void serial_receive(void *opaque, const uint8_t *buf, int size)
168{
169 ETRAXSerial *s = opaque;
170 int i;
171
172
173 if (s->rx_fifo_len >= 16) {
174 D(qemu_log("WARNING: UART dropped char.\n"));
175 return;
176 }
177
178 for (i = 0; i < size; i++) {
179 s->rx_fifo[s->rx_fifo_pos] = buf[i];
180 s->rx_fifo_pos++;
181 s->rx_fifo_pos &= 15;
182 s->rx_fifo_len++;
183 }
184
185 ser_update_irq(s);
186}
187
188static int serial_can_receive(void *opaque)
189{
190 ETRAXSerial *s = opaque;
191
192
193 if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
194 return 0;
195 }
196
197 return sizeof(s->rx_fifo) - s->rx_fifo_len;
198}
199
200static void serial_event(void *opaque, int event)
201{
202
203}
204
205static void etraxfs_ser_reset(DeviceState *d)
206{
207 ETRAXSerial *s = ETRAX_SERIAL(d);
208
209
210 s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
211 s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
212
213 s->regs[RW_REC_CTRL] = 0x10000;
214
215}
216
217static void etraxfs_ser_init(Object *obj)
218{
219 ETRAXSerial *s = ETRAX_SERIAL(obj);
220 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
221
222 sysbus_init_irq(dev, &s->irq);
223 memory_region_init_io(&s->mmio, obj, &ser_ops, s,
224 "etraxfs-serial", R_MAX * 4);
225 sysbus_init_mmio(dev, &s->mmio);
226}
227
228static void etraxfs_ser_realize(DeviceState *dev, Error **errp)
229{
230 ETRAXSerial *s = ETRAX_SERIAL(dev);
231
232 if (s->chr) {
233 qemu_chr_add_handlers(s->chr,
234 serial_can_receive, serial_receive,
235 serial_event, s);
236 }
237}
238
239static void etraxfs_ser_class_init(ObjectClass *klass, void *data)
240{
241 DeviceClass *dc = DEVICE_CLASS(klass);
242
243 dc->reset = etraxfs_ser_reset;
244 dc->props = etraxfs_ser_properties;
245 dc->realize = etraxfs_ser_realize;
246}
247
248static const TypeInfo etraxfs_ser_info = {
249 .name = TYPE_ETRAX_FS_SERIAL,
250 .parent = TYPE_SYS_BUS_DEVICE,
251 .instance_size = sizeof(ETRAXSerial),
252 .instance_init = etraxfs_ser_init,
253 .class_init = etraxfs_ser_class_init,
254};
255
256static void etraxfs_serial_register_types(void)
257{
258 type_register_static(&etraxfs_ser_info);
259}
260
261type_init(etraxfs_serial_register_types)
262