LXR qemu/hw/char/imx

   1/*
   2 * IMX31 UARTS
   3 *
   4 * Copyright (c) 2008 OKL
   5 * Originally Written by Hans Jiang
   6 * Copyright (c) 2011 NICTA Pty Ltd.
   7 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
   8 *
   9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10 * See the COPYING file in the top-level directory.
  11 *
  12 * This is a `bare-bones' implementation of the IMX series serial ports.
  13 * TODO:
  14 *  -- implement FIFOs.  The real hardware has 32 word transmit
  15 *                       and receive FIFOs; we currently use a 1-char buffer
  16 *  -- implement DMA
  17 *  -- implement BAUD-rate and modem lines, for when the backend
  18 *     is a real serial device.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "hw/char/imx_serial.h"
  23#include "sysemu/sysemu.h"
  24#include "sysemu/char.h"
  25#include "qemu/log.h"
  26
  27#ifndef DEBUG_IMX_UART
  28#define DEBUG_IMX_UART 0
  29#endif
  30
  31#define DPRINTF(fmt, args...) \
  32    do { \
  33        if (DEBUG_IMX_UART) { \
  34            fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
  35                                             __func__, ##args); \
  36        } \
  37    } while (0)
  38
  39static const VMStateDescription vmstate_imx_serial = {
  40    .name = TYPE_IMX_SERIAL,
  41    .version_id = 1,
  42    .minimum_version_id = 1,
  43    .fields = (VMStateField[]) {
  44        VMSTATE_INT32(readbuff, IMXSerialState),
  45        VMSTATE_UINT32(usr1, IMXSerialState),
  46        VMSTATE_UINT32(usr2, IMXSerialState),
  47        VMSTATE_UINT32(ucr1, IMXSerialState),
  48        VMSTATE_UINT32(uts1, IMXSerialState),
  49        VMSTATE_UINT32(onems, IMXSerialState),
  50        VMSTATE_UINT32(ufcr, IMXSerialState),
  51        VMSTATE_UINT32(ubmr, IMXSerialState),
  52        VMSTATE_UINT32(ubrc, IMXSerialState),
  53        VMSTATE_UINT32(ucr3, IMXSerialState),
  54        VMSTATE_END_OF_LIST()
  55    },
  56};
  57
  58static void imx_update(IMXSerialState *s)
  59{
  60    uint32_t flags;
  61
  62    flags = (s->usr1 & s->ucr1) & (USR1_TRDY|USR1_RRDY);
  63    if (s->ucr1 & UCR1_TXMPTYEN) {
  64        flags |= (s->uts1 & UTS1_TXEMPTY);
  65    } else {
  66        flags &= ~USR1_TRDY;
  67    }
  68
  69    qemu_set_irq(s->irq, !!flags);
  70}
  71
  72static void imx_serial_reset(IMXSerialState *s)
  73{
  74
  75    s->usr1 = USR1_TRDY | USR1_RXDS;
  76    /*
  77     * Fake attachment of a terminal: assert RTS.
  78     */
  79    s->usr1 |= USR1_RTSS;
  80    s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN;
  81    s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY;
  82    s->ucr1 = 0;
  83    s->ucr2 = UCR2_SRST;
  84    s->ucr3 = 0x700;
  85    s->ubmr = 0;
  86    s->ubrc = 4;
  87    s->readbuff = URXD_ERR;
  88}
  89
  90static void imx_serial_reset_at_boot(DeviceState *dev)
  91{
  92    IMXSerialState *s = IMX_SERIAL(dev);
  93
  94    imx_serial_reset(s);
  95
  96    /*
  97     * enable the uart on boot, so messages from the linux decompresser
  98     * are visible.  On real hardware this is done by the boot rom
  99     * before anything else is loaded.
 100     */
 101    s->ucr1 = UCR1_UARTEN;
 102    s->ucr2 = UCR2_TXEN;
 103
 104}
 105
 106static uint64_t imx_serial_read(void *opaque, hwaddr offset,
 107                                unsigned size)
 108{
 109    IMXSerialState *s = (IMXSerialState *)opaque;
 110    uint32_t c;
 111
 112    DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
 113
 114    switch (offset >> 2) {
 115    case 0x0: /* URXD */
 116        c = s->readbuff;
 117        if (!(s->uts1 & UTS1_RXEMPTY)) {
 118            /* Character is valid */
 119            c |= URXD_CHARRDY;
 120            s->usr1 &= ~USR1_RRDY;
 121            s->usr2 &= ~USR2_RDR;
 122            s->uts1 |= UTS1_RXEMPTY;
 123            imx_update(s);
 124            if (s->chr) {
 125                qemu_chr_accept_input(s->chr);
 126            }
 127        }
 128        return c;
 129
 130    case 0x20: /* UCR1 */
 131        return s->ucr1;
 132
 133    case 0x21: /* UCR2 */
 134        return s->ucr2;
 135
 136    case 0x25: /* USR1 */
 137        return s->usr1;
 138
 139    case 0x26: /* USR2 */
 140        return s->usr2;
 141
 142    case 0x2A: /* BRM Modulator */
 143        return s->ubmr;
 144
 145    case 0x2B: /* Baud Rate Count */
 146        return s->ubrc;
 147
 148    case 0x2d: /* Test register */
 149        return s->uts1;
 150
 151    case 0x24: /* UFCR */
 152        return s->ufcr;
 153
 154    case 0x2c:
 155        return s->onems;
 156
 157    case 0x22: /* UCR3 */
 158        return s->ucr3;
 159
 160    case 0x23: /* UCR4 */
 161    case 0x29: /* BRM Incremental */
 162        return 0x0; /* TODO */
 163
 164    default:
 165        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 166                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
 167        return 0;
 168    }
 169}
 170
 171static void imx_serial_write(void *opaque, hwaddr offset,
 172                             uint64_t value, unsigned size)
 173{
 174    IMXSerialState *s = (IMXSerialState *)opaque;
 175    unsigned char ch;
 176
 177    DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
 178            offset, (unsigned int)value, s->chr ? s->chr->label : "NODEV");
 179
 180    switch (offset >> 2) {
 181    case 0x10: /* UTXD */
 182        ch = value;
 183        if (s->ucr2 & UCR2_TXEN) {
 184            if (s->chr) {
 185                qemu_chr_fe_write(s->chr, &ch, 1);
 186            }
 187            s->usr1 &= ~USR1_TRDY;
 188            imx_update(s);
 189            s->usr1 |= USR1_TRDY;
 190            imx_update(s);
 191        }
 192        break;
 193
 194    case 0x20: /* UCR1 */
 195        s->ucr1 = value & 0xffff;
 196
 197        DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
 198
 199        imx_update(s);
 200        break;
 201
 202    case 0x21: /* UCR2 */
 203        /*
 204         * Only a few bits in control register 2 are implemented as yet.
 205         * If it's intended to use a real serial device as a back-end, this
 206         * register will have to be implemented more fully.
 207         */
 208        if (!(value & UCR2_SRST)) {
 209            imx_serial_reset(s);
 210            imx_update(s);
 211            value |= UCR2_SRST;
 212        }
 213        if (value & UCR2_RXEN) {
 214            if (!(s->ucr2 & UCR2_RXEN)) {
 215                if (s->chr) {
 216                    qemu_chr_accept_input(s->chr);
 217                }
 218            }
 219        }
 220        s->ucr2 = value & 0xffff;
 221        break;
 222
 223    case 0x25: /* USR1 */
 224        value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |
 225                 USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;
 226        s->usr1 &= ~value;
 227        break;
 228
 229    case 0x26: /* USR2 */
 230        /*
 231         * Writing 1 to some bits clears them; all other
 232         * values are ignored
 233         */
 234        value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |
 235                 USR2_RIDELT | USR2_IRINT | USR2_WAKE |
 236                 USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;
 237        s->usr2 &= ~value;
 238        break;
 239
 240    /*
 241     * Linux expects to see what it writes to these registers
 242     * We don't currently alter the baud rate
 243     */
 244    case 0x29: /* UBIR */
 245        s->ubrc = value & 0xffff;
 246        break;
 247
 248    case 0x2a: /* UBMR */
 249        s->ubmr = value & 0xffff;
 250        break;
 251
 252    case 0x2c: /* One ms reg */
 253        s->onems = value & 0xffff;
 254        break;
 255
 256    case 0x24: /* FIFO control register */
 257        s->ufcr = value & 0xffff;
 258        break;
 259
 260    case 0x22: /* UCR3 */
 261        s->ucr3 = value & 0xffff;
 262        break;
 263
 264    case 0x2d: /* UTS1 */
 265    case 0x23: /* UCR4 */
 266        qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
 267                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
 268        /* TODO */
 269        break;
 270
 271    default:
 272        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 273                      HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
 274    }
 275}
 276
 277static int imx_can_receive(void *opaque)
 278{
 279    IMXSerialState *s = (IMXSerialState *)opaque;
 280    return !(s->usr1 & USR1_RRDY);
 281}
 282
 283static void imx_put_data(void *opaque, uint32_t value)
 284{
 285    IMXSerialState *s = (IMXSerialState *)opaque;
 286
 287    DPRINTF("received char\n");
 288
 289    s->usr1 |= USR1_RRDY;
 290    s->usr2 |= USR2_RDR;
 291    s->uts1 &= ~UTS1_RXEMPTY;
 292    s->readbuff = value;
 293    imx_update(s);
 294}
 295
 296static void imx_receive(void *opaque, const uint8_t *buf, int size)
 297{
 298    imx_put_data(opaque, *buf);
 299}
 300
 301static void imx_event(void *opaque, int event)
 302{
 303    if (event == CHR_EVENT_BREAK) {
 304        imx_put_data(opaque, URXD_BRK);
 305    }
 306}
 307
 308
 309static const struct MemoryRegionOps imx_serial_ops = {
 310    .read = imx_serial_read,
 311    .write = imx_serial_write,
 312    .endianness = DEVICE_NATIVE_ENDIAN,
 313};
 314
 315static void imx_serial_realize(DeviceState *dev, Error **errp)
 316{
 317    IMXSerialState *s = IMX_SERIAL(dev);
 318
 319    if (s->chr) {
 320        qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,
 321                              imx_event, s);
 322    } else {
 323        DPRINTF("No char dev for uart\n");
 324    }
 325}
 326
 327static void imx_serial_init(Object *obj)
 328{
 329    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 330    IMXSerialState *s = IMX_SERIAL(obj);
 331
 332    memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s,
 333                          TYPE_IMX_SERIAL, 0x1000);
 334    sysbus_init_mmio(sbd, &s->iomem);
 335    sysbus_init_irq(sbd, &s->irq);
 336}
 337
 338static Property imx_serial_properties[] = {
 339    DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
 340    DEFINE_PROP_END_OF_LIST(),
 341};
 342
 343static void imx_serial_class_init(ObjectClass *klass, void *data)
 344{
 345    DeviceClass *dc = DEVICE_CLASS(klass);
 346
 347    dc->realize = imx_serial_realize;
 348    dc->vmsd = &vmstate_imx_serial;
 349    dc->reset = imx_serial_reset_at_boot;
 350    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 351    dc->desc = "i.MX series UART";
 352    dc->props = imx_serial_properties;
 353}
 354
 355static const TypeInfo imx_serial_info = {
 356    .name           = TYPE_IMX_SERIAL,
 357    .parent         = TYPE_SYS_BUS_DEVICE,
 358    .instance_size  = sizeof(IMXSerialState),
 359    .instance_init  = imx_serial_init,
 360    .class_init     = imx_serial_class_init,
 361};
 362
 363static void imx_serial_register_types(void)
 364{
 365    type_register_static(&imx_serial_info);
 366}
 367
 368type_init(imx_serial_register_types)
 369